diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl index a6e0fd407ae1dd577ef193a3f097a590b6435456..bfb454a014dade7c9a99db5efc2eda89e3baab17 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl @@ -82,6 +82,7 @@ read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v read_verilog $soc_vlog/nanosoc_cpu.v read_verilog $soc_vlog/nanosoc_sys_ahb_decode.v read_verilog $soc_vlog/nanosoc_sysio.v +read_verilog $soc_vlog/soclabs_ahb_aes128_ctrl.v read_verilog $soc_vlog/nanosoc_chip.v read_verilog $soc_vlog/nanosoc_chip_pads.v diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v index 7209c105abd57a0d750f616dbed4d3c5164e0abb..2474888b5e032a3238fe5045202cbee9c34aa222 100644 --- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v +++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v @@ -821,44 +821,50 @@ localparam CORTEX_M0 = 1; // ************************************************ // ************************************************ // -// ADD YOUR EXPERIMENTAL AHB-MAPPED I/O HERE +// ADD YOUR EXPERIMENTAL AHB-MAPPED WRAPPER HERE // // // ************************************************ - -// -// dummy interface of the form: -// experimental_ip u_exp ( -// .HCLK (HCLK), -// .HRESETn (HRESETn), -// .HSEL (HSEL_exp), -// .HADDR (HADDR_exp), -// .HTRANS (HTRANS_exp), -// .HWRITE (HWRITE_exp), -// .HSIZE (HSIZE_exp), -// .HBURST (HBURST_exp), -// .HPROT (HPROT_exp), -// .HWDATA (HWDATA_exp), -// .HMASTLOCK (HMASTLOCK_exp), -// .HREADY (HREADYMUX_exp), -// .HRDATA (HRDATA_exp), -// .HREADYOUT (HREADYOUT_exp), -// .HRESP (HRESP_exp) -// ); - - // Default slave - cmsdk_ahb_default_slave u_ahb_exp ( - .HCLK (HCLK), - .HRESETn (HRESETn), - .HSEL (HSEL_exp), - .HTRANS (HTRANS_exp), - .HREADY (HREADYMUX_exp), - .HREADYOUT (HREADYOUT_exp), - .HRESP (HRESP_exp) + soclabs_ahb_aes128_ctrl u_exp_aes128 ( + .ahb_hclk (HCLK), + .ahb_hresetn (HRESETn), + .ahb_hsel (HSEL_exp), + .ahb_haddr16 (HADDR_exp[15:0]), + .ahb_htrans (HTRANS_exp), + .ahb_hwrite (HWRITE_exp), + .ahb_hsize (HSIZE_exp), +// .ahb_hburst (HBURST_exp), + .ahb_hprot (HPROT_exp), + .ahb_hwdata (HWDATA_exp), +// .ahb_hmastlock (HMASTLOCK_exp), + .ahb_hready (HREADYMUX_exp), + .ahb_hrdata (HRDATA_exp), + .ahb_hreadyout (HREADYOUT_exp), + .ahb_hresp (HRESP_exp), + .drq_ipdma128 ( ), + .dlast_ipdma128 (1'b0), + .drq_opdma128 ( ), + .dlast_opdma128 (1'b0), + .irq_key128 ( ), + .irq_ip128 ( ), + .irq_op128 ( ), + .irq_error ( ), + .irq_merged ( ) ); + +// // Default slave +// cmsdk_ahb_default_slave u_ahb_exp ( +// .HCLK (HCLK), +// .HRESETn (HRESETn), +// .HSEL (HSEL_exp), +// .HTRANS (HTRANS_exp), +// .HREADY (HREADYMUX_exp), +// .HREADYOUT (HREADYOUT_exp), +// .HRESP (HRESP_exp) +// ); +// assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data - assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data assign HRUSER_exp = 2'b00; // ************************************************ diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v b/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v index 27796a35dc05fe84ee5c0d2752ef3a9758f3af35..57ac73bcb88ad2b782850a5137bb35ce48f18f8f 100644 --- a/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v +++ b/Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v @@ -419,7 +419,7 @@ reg aes_res_rdy; assign irq_active[REQ_KEYBUF_BIT] = drq_active[REQ_KEYBUF_BIT] & !drq_enable[REQ_KEYBUF_BIT]; assign irq_active[REQ_IP_BUF_BIT] = drq_active[REQ_IP_BUF_BIT] & !drq_enable[REQ_IP_BUF_BIT]; assign irq_active[REQ_OP_BUF_BIT] = drq_active[REQ_OP_BUF_BIT] & !drq_enable[REQ_OP_BUF_BIT]; - assign irq_active[REQ_ERROR_BIT ] = control[CTRL_ERR_REQ_BIT] | (!aes_res_busy & !aes_key_rdy); // error raised in SW + assign irq_active[REQ_ERROR_BIT ] = control[CTRL_ERR_REQ_BIT] | (!aes_res_busy & !aes_key_rdy); // error raised in SW assign irq_key128 = irq_active[REQ_KEYBUF_BIT] & !drq_active[REQ_KEYBUF_BIT]; assign irq_ip128 = irq_active[REQ_IP_BUF_BIT] & !drq_active[REQ_IP_BUF_BIT]; @@ -606,7 +606,7 @@ endmodule // //====================================================================== -`default_nettype none +///`default_nettype none module aes_core( input wire clk, @@ -950,7 +950,7 @@ endmodule // aes_core // //====================================================================== -`default_nettype none +///`default_nettype none module aes_encipher_block( input wire clk, @@ -1438,7 +1438,7 @@ endmodule // aes_encipher_block // //====================================================================== -`default_nettype none +///`default_nettype none module aes_decipher_block( input wire clk, @@ -1963,7 +1963,7 @@ endmodule // aes_decipher_block // //====================================================================== -`default_nettype none +///`default_nettype none module aes_key_mem( input wire clk, @@ -2399,7 +2399,7 @@ endmodule // aes_key_mem // //====================================================================== -`default_nettype none +///`default_nettype none module aes_sbox( input wire [31 : 0] sboxw, @@ -2725,7 +2725,7 @@ endmodule // aes_sbox // //====================================================================== -`default_nettype none +///`default_nettype none module aes_inv_sbox( input wire [31 : 0] sboxw, diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc b/Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc index f79c6d02f1b5b61ca23063536eb0da1375ea2757..07a2b2d9090916693aa49c099ab87c40e388c82e 100644 --- a/Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc +++ b/Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc @@ -106,22 +106,22 @@ // ============= Cortex-M0 Module search path ============= --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog // ============= Cortex-M0 Include file search path ============= -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc b/Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc index 3f3fa70ebc531448973008fbf1edec0c9287d072..d744b3ebe1e9f793f1c49be09c55a6b515cf2faf 100644 --- a/Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc +++ b/Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc @@ -106,16 +106,16 @@ // ============= Cortex-M0 Module search path ============= // guts of core not exposed, periphery only --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog // ============= Cortex-M0 Include file search path ============= // guts of core not exposed, periphery only -+incdi+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog