STarted to generalise build_design

fpga/build_nanosoc_design.tcl → fpga/build_design.tcl

 ###-----------------------------------------------------------------------------
-### Build FPGA Script
+### Build Design Viviado FPGA Script
 ### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 ###
 ### Contributors
@@ -24,6 +24,9 @@ set socket_lib $env(FPGA_SOCKET_LIB)
 set nanosoc_lib $env(FPGA_NANOSOC_LIB)
 set output_dir $env(FPGA_OUTPUT_DIR)
 
+set wrapper_name $env(FPGA_WRAPPER_NAME)
+set pinmap_file $env(FPGA_PINMAP)
+
 #
 # STEP#1: setup design sources and constraints
 #
@@ -31,6 +34,7 @@ set_part $xilinx_part
 set_property TARGET_LANGUAGE Verilog [current_project]
 set_property DEFAULT_LIB work [current_project]
 
+# TODO: Generalise this stage
 set paths [list \
  $socket_lib\
  $nanosoc_lib\
@@ -51,16 +55,16 @@ report_ip_status
 # #
 # # using script written out from GUI capture
 
-create_bd_design nanosoc_design
+create_bd_design $design_name
 
-read_verilog $import_dir/nanosoc_design_wrapper.v
-source $target_tcl_dir/nanosoc_design.tcl
+read_verilog $import_dir/$wrapper_name.v
+source $target_tcl_dir/$design_name.tcl
 create_root_design ""
 
 
-add_files $import_dir/fpga_pinmap.xdc
+add_files $pinmap_file
 
-set_property top nanosoc_design_wrapper [current_fileset]
+set_property top $wrapper_name [current_fileset]
 
 # #
 # # STEP#3: save in Project mode to complete flow

fpga/makefile

@@ -49,6 +49,7 @@ NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
 # Directory to look for FPGA specific implementation files
 TARGET_DIR            ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
 TARGET_TCL_DIR        := $(TARGET_DIR)/vivado_script/$(VIVIADO_VERSION)
+PINMAP_FILE           ?= $(TARGET_DIR)/fpga_pinmap.xdc
 
 # NanoSoC Tech Socket Design Dependencies
 RTL_SOCKET_DIR        := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
@@ -111,15 +112,17 @@ build_nanosoc_design: export FPGA_PROJECT_DIR        = $(PROJECT_DIR)
 build_nanosoc_design: export FPGA_TARGET             = $(TARGET_DIR)
 build_nanosoc_design: export FPGA_TARGET_TCL         = $(TARGET_TCL_DIR)
 build_nanosoc_design: export FPGA_DESIGN_NAME        = $(DESIGN_NAME)
+build_nanosoc_design: export FPGA_WRAPPER_NAME       = $(DESIGN_NAME)_wrapper
 build_nanosoc_design: export FPGA_NANOSOC_LIB        = $(IMP_NANOSOC_DIR)
 build_nanosoc_design: export FPGA_SOCKET_LIB         = $(IMP_SOCKET_DIR)
 build_nanosoc_design: export FPGA_OUTPUT_DIR         = $(OUTPUT_DIR)
+build_nanosoc_design: export FPGA_PINMAP             = $(PINMAP_FILE)
 
 # Synthesise and Implement an FPGA Bitfile
 build_nanosoc_design:
 	@echo Building NanoSoC Design
 	@mkdir -p $(RUN_DIR)
-	@cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_nanosoc_design.tcl
+	@cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_design.tcl
 	@cp $(RUN_DIR)/vivado.log $(TARGET_DIR)
 	@echo Built NanoSoC Design