From ea74e1f0d72a47866a3d56c76395fd39db5f2de5 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Tue, 4 Jul 2023 10:58:36 +0100
Subject: [PATCH] STarted to generalise build_design
---
...build_nanosoc_design.tcl => build_design.tcl} | 16 ++++++++++------
fpga/makefile | 5 ++++-
2 files changed, 14 insertions(+), 7 deletions(-)
rename fpga/{build_nanosoc_design.tcl => build_design.tcl} (86%)
diff --git a/fpga/build_nanosoc_design.tcl b/fpga/build_design.tcl
similarity index 86%
rename from fpga/build_nanosoc_design.tcl
rename to fpga/build_design.tcl
index 4cce371..c33f78b 100644
--- a/fpga/build_nanosoc_design.tcl
+++ b/fpga/build_design.tcl
@@ -1,5 +1,5 @@
###-----------------------------------------------------------------------------
-### Build FPGA Script
+### Build Design Viviado FPGA Script
### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
###
### Contributors
@@ -24,6 +24,9 @@ set socket_lib $env(FPGA_SOCKET_LIB)
set nanosoc_lib $env(FPGA_NANOSOC_LIB)
set output_dir $env(FPGA_OUTPUT_DIR)
+set wrapper_name $env(FPGA_WRAPPER_NAME)
+set pinmap_file $env(FPGA_PINMAP)
+
#
# STEP#1: setup design sources and constraints
#
@@ -31,6 +34,7 @@ set_part $xilinx_part
set_property TARGET_LANGUAGE Verilog [current_project]
set_property DEFAULT_LIB work [current_project]
+# TODO: Generalise this stage
set paths [list \
$socket_lib\
$nanosoc_lib\
@@ -51,16 +55,16 @@ report_ip_status
# #
# # using script written out from GUI capture
-create_bd_design nanosoc_design
+create_bd_design $design_name
-read_verilog $import_dir/nanosoc_design_wrapper.v
-source $target_tcl_dir/nanosoc_design.tcl
+read_verilog $import_dir/$wrapper_name.v
+source $target_tcl_dir/$design_name.tcl
create_root_design ""
-add_files $import_dir/fpga_pinmap.xdc
+add_files $pinmap_file
-set_property top nanosoc_design_wrapper [current_fileset]
+set_property top $wrapper_name [current_fileset]
# #
# # STEP#3: save in Project mode to complete flow
diff --git a/fpga/makefile b/fpga/makefile
index 597b8b3..50ddcd4 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -49,6 +49,7 @@ NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
# Directory to look for FPGA specific implementation files
TARGET_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
TARGET_TCL_DIR := $(TARGET_DIR)/vivado_script/$(VIVIADO_VERSION)
+PINMAP_FILE ?= $(TARGET_DIR)/fpga_pinmap.xdc
# NanoSoC Tech Socket Design Dependencies
RTL_SOCKET_DIR := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
@@ -111,15 +112,17 @@ build_nanosoc_design: export FPGA_PROJECT_DIR = $(PROJECT_DIR)
build_nanosoc_design: export FPGA_TARGET = $(TARGET_DIR)
build_nanosoc_design: export FPGA_TARGET_TCL = $(TARGET_TCL_DIR)
build_nanosoc_design: export FPGA_DESIGN_NAME = $(DESIGN_NAME)
+build_nanosoc_design: export FPGA_WRAPPER_NAME = $(DESIGN_NAME)_wrapper
build_nanosoc_design: export FPGA_NANOSOC_LIB = $(IMP_NANOSOC_DIR)
build_nanosoc_design: export FPGA_SOCKET_LIB = $(IMP_SOCKET_DIR)
build_nanosoc_design: export FPGA_OUTPUT_DIR = $(OUTPUT_DIR)
+build_nanosoc_design: export FPGA_PINMAP = $(PINMAP_FILE)
# Synthesise and Implement an FPGA Bitfile
build_nanosoc_design:
@echo Building NanoSoC Design
@mkdir -p $(RUN_DIR)
- @cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_nanosoc_design.tcl
+ @cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_design.tcl
@cp $(RUN_DIR)/vivado.log $(TARGET_DIR)
@echo Built NanoSoC Design
--
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