Moved commands from tcl to makefile as seperate target

fpga/build_nanosoc_design.tcl

@@ -91,9 +91,4 @@ wait_on_run impl_1
 
 write_hw_platform -fixed -include_bit -force -file $project_dir/$design_name.xsa
 
-exec unzip -u -o $project_dir/$design_name.xsa -d $project_dir/export
-exec mkdir -p $output_dir
-exec cp -p $project_dir/export/$design_name.bit $output_dir
-exec cp -p $project_dir/export/$design_name.hwh $output_dir
-
 exit 0

fpga/makefile

@@ -46,9 +46,6 @@ TCL_OUTPUT_FILELIST  := $(TCL_FLIST_DIR)/gen_flist.tcl
 # NanoSoC Tech Flow Dependencies
 NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
 
-# NanoSoC Defines File
-NANOSOC_DEFINES_FILE  ?= $(NANOSOC_FPGA_FLOW_DIR)/nanosoc_defines.tcl
-
 # Directory to look for FPGA specific implementation files
 TARGET_DIR            ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
 TARGET_TCL_DIR        := $(TARGET_DIR)/vivado_script/$(VIVIADO_VERSION)
@@ -58,9 +55,9 @@ RTL_SOCKET_DIR        := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
 
 # Define Bitfile Output Directory depending on Platform
 ifeq ($(PLATFORM), bare)
-	OUTPUT_DIR ?=  $(FPGA_IMPLEMENTATION_DIR)/output/$(BOARD_NAME)
+	OUTPUT_DIR ?=  $(IMPLEMENTATION_DIR)/output/$(BOARD_NAME)
 else ifeq ($(PLATFORM), pynq)
-	OUTPUT_DIR ?=  $(FPGA_IMPLEMENTATION_DIR)/output/$(BOARD_NAME)/overlays
+	OUTPUT_DIR ?=  $(IMPLEMENTATION_DIR)/output/$(BOARD_NAME)/overlays
 endif
 
 # Is an accelerator subsystem present in the design?
@@ -72,15 +69,19 @@ else
 	ACCELERATOR_SUBSYSTEM = 0
 endif
 
+# Defines to pass to filelist compile
+NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM=$(ACCELERATOR_SUBSYSTEM)
+
 # Compile Testcodes and Bootrom
 code:
-	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) code
+	@echo Compiling Firmware
+	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) compile_all_code
 
 # Generate TCL filelist from flists
 nanosoc_flist:
 	@mkdir -p $(TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR) -d $(NANOSOC_DEFINES);)
 
 # Package NanoSoC Socket Components
 package_socket:
@@ -88,7 +89,6 @@ package_socket:
 
 # Environment Variables for Packaging NanoSoC
 package_nanosoc: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST)
-package_nanosoc: export FPGA_COMPONENT_DEFINES  = $(NANOSOC_DEFINES_FILE)
 package_nanosoc: export FPGA_COMPONENT_LIB      = $(IMP_NANOSOC_DIR)
 package_nanosoc: export FPGA_ACCELERATOR        = $(ACCELERATOR_SUBSYSTEM)
 package_nanosoc: export FPGA_DESIGN_TOP         = $(FPGA_TOP)
@@ -144,4 +144,6 @@ clean_fpga:
 # Clean ALL FPGA Implementation Directory
 clean_fpga_all:
 	@echo Cleaning FPGA Implementation Directory
-	@rm -rf $(IMPLEMENTATION_DIR)
\ No newline at end of file
+	@rm -rf $(IMPLEMENTATION_DIR)
+	@echo Cleaning Firmware
+	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) clean_all_code
\ No newline at end of file

fpga/nanosoc_defines.tcl

-###-----------------------------------------------------------------------------
-### NanoSoC Defines Script
-### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-###
-### Contributors
-###
-### David Mapstone (d.a.mapstone@soton.ac.uk)
-###
-### Copyright  2023, SoC Labs (www.soclabs.org)
-###-----------------------------------------------------------------------------
-
-set_property generic {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
-set_property verilog_define {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
\ No newline at end of file