ICC flow working

synthesis/ICC2/icc_shell.tcl

@@ -11,24 +11,26 @@
 
 
 set design_name nanosoc_chip_pads
+set PHYS_IP_DIR /home/dwn1c21/SoC-Labs/phys_ip
 
-set_app_var link_library  $env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
-create_lib tsmc65lp -technology $env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc9_tech.tf -ref_libs {$env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/rf_sp_hdf.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/rom_via.lef} 
 
-read_parasitic_tech -name {typical} -tlup {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus} -layermap {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
-read_parasitic_tech -name {rcbest} -tlup {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus} -layermap {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
-read_parasitic_tech -name {rcworst} -tlup {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus} -layermap {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
+set_app_var link_library  $PHYS_IP_DIR/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
+create_lib tsmc65lp -technology $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc9_tech.tf -ref_libs [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/rf_sp_hdf.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/rom_via.lef]
+
+read_parasitic_tech -name typical -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+read_parasitic_tech -name rcbest -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
 
 
 read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
 link_block
 
 
-initialize_floorplan -control_type die -keep_pg_route -utilization 0.6 -side_ratio {1 1} -core_offset {50 50} -keep_placement {all}
+initialize_floorplan -control_type die -keep_pg_route -core_utilization 0.55 -side_ratio {1 1} -core_offset {100 100} -keep_placement {all}
 create_io_ring -name main_io
 explore_logic_hierarchy -organize
 
-load_upf nanosoc_chip_pads_power.upf
+load_upf ../nanosoc_chip_pads_power.upf
 commit_upf
 
 set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
@@ -42,16 +44,26 @@ current_mode default
 set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDD]
 set_voltage 3.00 -corner [current_corner] -object_list [get_supply_nets VDDIO]
 
+set_app_options -list {opt.dft.optimize_scan_chain {false}}
+set_app_options -list {opt.dft.do_repartition {false}}
+set_app_options -list {place.coarse.continue_on_missing_scandef {true}}
+
 read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/constraints.sdc
 update_timing
 
 change_selection [explore_logic_hierarchy -create_module_boundary]
 explore_logic_hierarchy -place -rectangular
 
+# Place IO pins
+source place_pins.tcl
+
+#Place and fix memories with boundary
 source place_memories.tcl
 
+#Create power ring and straps
 source power_plan.tcl
 
+#Start Placement
 create_placement 
 legalize_placement -cells [get_cells -design [current_block]]
 
@@ -59,10 +71,8 @@ save_lib -all
 
 report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_opt_placement_timing.rep
 
-set_app_options -list {opt.dft.optimize_scan_chain {false}}
-set_app_options -list {opt.dft.do_repartition {false}}
-set_app_options -list {place.coarse.continue_on_missing_scandef {true}}
 place_opt
+save_lib -all
 
 update_timing -full
 report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_opt_placement_timing.rep
@@ -70,5 +80,15 @@ report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_opt_p
 check_clock_trees -clocks clk
 synthesize_clock_trees -clocks clk
 clock_opt
+update_timing -full
 report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_opt_placement_timing.rep
+save_lib -all
 
+#Start Routing
+route_auto
+update_timing -full
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_timing.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_power.rep
+save_lib -all
+exit
\ No newline at end of file

synthesis/ICC2/place_memories.tcl

-set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] -name origin -value {115 450}
-set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf] -name origin -value {450.0000 150.0000}
-set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf] -name origin -value {115.0000 150.0000}
-set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf] -name origin -value {450 450}
-set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] -name origin -value {260 50}
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset -0.2 -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner tl -anchor_corner tl -offset {0.2 -0.2} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner br -anchor_corner br -offset {-0.2 0.3} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}] -target_orientation R0 -target_corner bl -anchor_corner bl -offset {0.2 0.3} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom}] -target_orientation R0 -target_corner bl -anchor_corner bl -offset {0.4 0.15} -offset_type scalable
+create_macro_relative_location_placement
 
 set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
 set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
@@ -10,4 +11,6 @@ set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_regio
 set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
 set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] -name physical_status -value fixed
 
-create_keepout_margin -type hard -outer {2 2 2 2} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type hard_macro -outer {2 2 2 2} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type soft -outer {4 4 4 4} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];
+create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];
+create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] ref_block];
+

synthesis/ICC2/place_pins.tcl

+set_individual_pin_constraints -ports {P0[15] P0[14] P0[13] P0[12] P0[11] P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]} -sides 1
+set_individual_pin_constraints -ports {P1[15] P1[14] P1[13] P1[12] P1[11] P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]} -sides 3
+set_individual_pin_constraints -ports {XTAL2 XTAL1 VDD VDDIO} -sides 2
+set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIOTMS SWCLKTCK} -sides 4
+
+place_pins -self
\ No newline at end of file

synthesis/ICC2/preferred_port_locations.tcl

-START PHYSICAL PIN CONSTRAINTS;
-    {pins XTAL1} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 277.0000};
-    {pins XTAL2} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 83.8000};
-    {pins NRST} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 139.0000};
-    {pins P0[15]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 194.2000};
-    {pins P0[14]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 249.4000};
-    {pins P0[13]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 304.6000};
-    {pins P0[12]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 359.8000};
-    {pins P0[11]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 415.0000};
-    {pins P0[10]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 470.2000};
-    {pins P0[9]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 525.4000};
-    {pins P0[8]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 32.6000};
-    {pins P0[7]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 94.0000};
-    {pins P0[6]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 155.2000};
-    {pins P0[5]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 216.6000};
-    {pins P0[4]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 277.8000};
-    {pins P0[3]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 339.0000};
-    {pins P0[2]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 400.4000};
-    {pins P0[1]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 461.6000};
-    {pins P0[0]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 523.0000};
-    {pins P1[15]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 522.6000};
-    {pins P1[14]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 461.2000};
-    {pins P1[13]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 400.0000};
-    {pins P1[12]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 338.6000};
-    {pins P1[11]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 277.2000};
-    {pins P1[10]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 215.8000};
-    {pins P1[9]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 154.4000};
-    {pins P1[8]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 93.2000};
-    {pins P1[7]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 31.8000};
-    {pins P1[6]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 521.0000};
-    {pins P1[5]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 459.6000};
-    {pins P1[4]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 398.4000};
-    {pins P1[3]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 337.0000};
-    {pins P1[2]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 275.8000};
-    {pins P1[1]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 214.6000};
-    {pins P1[0]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 153.2000};
-    {pins SWDIOTMS} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 92.0000};
-    {pins SWCLKTCK} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 30.6000};
-END PHYSICAL PIN CONSTRAINTS;
-