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Commit fbc65380 authored by Daniel Newbrook's avatar Daniel Newbrook
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Update ICC flow, up to clock opt

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synthesis/icc_shell.tcl → synthesis/ICC2/icc_shell.tcl
+ 74
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View file @ fbc65380
......@@ -12,19 +12,19 @@
set design_name nanosoc_chip_pads
set_app_var link_library /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
create_lib tsmc65lp -tech /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc9_tech.tf -ref_libs {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/rf_sp_hdf.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/rom_via.lef}
set_app_var link_library $env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
create_lib tsmc65lp -technology $env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc9_tech.tf -ref_libs {$env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/rf_sp_hdf.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/rom_via.lef}
read_parasitic_tech -name {typical} -tlup {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus} -layermap {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
read_parasitic_tech -name {rcbest} -tlup {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus} -layermap {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
read_parasitic_tech -name {rcworst} -tlup {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus} -layermap {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
read_parasitic_tech -name {typical} -tlup {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus} -layermap {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
read_parasitic_tech -name {rcbest} -tlup {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus} -layermap {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
read_parasitic_tech -name {rcworst} -tlup {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus} -layermap {$env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
link_block
initialize_floorplan -control_type die -keep_pg_route -side_ratio {1500 1500} -core_offset {50 50} -keep_placement {all}
initialize_floorplan -control_type die -keep_pg_route -utilization 0.6 -side_ratio {1 1} -core_offset {50 50} -keep_placement {all}
create_io_ring -name main_io
explore_logic_hierarchy -organize
......@@ -40,18 +40,35 @@ current_corner default
set_operating_conditions -max_library sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
current_mode default
set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDD]
read_sdc /home/dwn1c21/SoC-Labs/accelerator-project/nanosoc_tech/synthesis/constraints.sdc
set_voltage 3.00 -corner [current_corner] -object_list [get_supply_nets VDDIO]
read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/constraints.sdc
update_timing
change_selection [explore_logic_hierarchy -create_module_boundary]
explore_logic_hierarchy -place -rectangular
create_keepout_margin -type hard -outer {2 2 2 2} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type hard_macro -outer {2 2 2 2} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type soft -outer {4 4 4 4} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];
source place_memories.tcl
source power_plan.tcl
create_placement
legalize_placement -cells [get_cells -design [current_block]]
save_lib -all
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_opt_placement_timing.rep
set_app_options -list {opt.dft.optimize_scan_chain {false}}
set_app_options -list {opt.dft.do_repartition {false}}
set_app_options -list {place.coarse.continue_on_missing_scandef {true}}
place_opt
connect_pg_net -automatic
create_pg_ring_patter ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2} -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
set_pg_strategy core_ring -pattern {{name:ring_pattern} {nets: {VDD VDDIO VSS VSSIO}}{offset: {3 3}}} -core
compile_pg -strategies core_ring
update_timing -full
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_opt_placement_timing.rep
check_clock_trees -clocks clk
synthesize_clock_trees -clocks clk
clock_opt
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_opt_placement_timing.rep
create_placement -floorplan
\ No newline at end of file
synthesis/ICC2/place_memories.tcl 0 → 100644
+ 13
− 0
View file @ fbc65380
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] -name origin -value {115 450}
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf] -name origin -value {450.0000 150.0000}
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf] -name origin -value {115.0000 150.0000}
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf] -name origin -value {450 450}
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] -name origin -value {260 50}
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom] -name physical_status -value fixed
create_keepout_margin -type hard -outer {2 2 2 2} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type hard_macro -outer {2 2 2 2} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];create_keepout_margin -type soft -outer {4 4 4 4} [get_attribute [get_cells u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf] ref_block];
synthesis/ICC2/power_plan.tcl 0 → 100644
+ 11
− 0
View file @ fbc65380
connect_pg_net -automatic
create_pg_ring_patter ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2} -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
set_pg_strategy core_ring -pattern {{name:ring_pattern} {nets: {VDD VDDIO VSS VSSIO}}{offset: {3 3}}} -core
create_pg_mesh_pattern strap_pattern -layers {{{vertical_layer: M4} {width: 1} {pitch: 50} {spacing: interleaving} {trim: false}}}
set_pg_strategy M4_straps -core -pattern {{name: strap_pattern}{nets: VDD VSS}}
create_pg_std_cell_conn_pattern rail_pattern -layers M1
set_pg_strategy M1_rails -core -pattern {{name: rail_pattern}{nets: VDD VSS}}
compile_pg -strategies {M4_straps M1_rails core_ring}
synthesis/ICC2/preferred_port_locations.tcl 0 → 100644
+ 40
− 0
View file @ fbc65380
START PHYSICAL PIN CONSTRAINTS;
{pins XTAL1} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 277.0000};
{pins XTAL2} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 83.8000};
{pins NRST} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 139.0000};
{pins P0[15]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 194.2000};
{pins P0[14]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 249.4000};
{pins P0[13]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 304.6000};
{pins P0[12]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 359.8000};
{pins P0[11]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 415.0000};
{pins P0[10]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 470.2000};
{pins P0[9]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 525.4000};
{pins P0[8]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 32.6000};
{pins P0[7]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 94.0000};
{pins P0[6]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 155.2000};
{pins P0[5]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 216.6000};
{pins P0[4]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 277.8000};
{pins P0[3]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 339.0000};
{pins P0[2]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 400.4000};
{pins P0[1]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 461.6000};
{pins P0[0]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 523.0000};
{pins P1[15]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 522.6000};
{pins P1[14]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 461.2000};
{pins P1[13]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 400.0000};
{pins P1[12]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 338.6000};
{pins P1[11]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 277.2000};
{pins P1[10]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 215.8000};
{pins P1[9]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 154.4000};
{pins P1[8]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 93.2000};
{pins P1[7]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 31.8000};
{pins P1[6]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 521.0000};
{pins P1[5]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 459.6000};
{pins P1[4]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 398.4000};
{pins P1[3]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 337.0000};
{pins P1[2]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 275.8000};
{pins P1[1]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 214.6000};
{pins P1[0]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 153.2000};
{pins SWDIOTMS} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 92.0000};
{pins SWCLKTCK} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 30.6000};
END PHYSICAL PIN CONSTRAINTS;
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