preferred_port_locations.tcl

START PHYSICAL PIN CONSTRAINTS;
    {pins XTAL1} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 277.0000};
    {pins XTAL2} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 83.8000};
    {pins NRST} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 139.0000};
    {pins P0[15]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 194.2000};
    {pins P0[14]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 249.4000};
    {pins P0[13]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 304.6000};
    {pins P0[12]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 359.8000};
    {pins P0[11]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 415.0000};
    {pins P0[10]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 470.2000};
    {pins P0[9]} {reference nanosoc_chip_pads} {layers M2} {sides 4} {offset 525.4000};
    {pins P0[8]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 32.6000};
    {pins P0[7]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 94.0000};
    {pins P0[6]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 155.2000};
    {pins P0[5]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 216.6000};
    {pins P0[4]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 277.8000};
    {pins P0[3]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 339.0000};
    {pins P0[2]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 400.4000};
    {pins P0[1]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 461.6000};
    {pins P0[0]} {reference nanosoc_chip_pads} {layers M3} {sides 3} {offset 523.0000};
    {pins P1[15]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 522.6000};
    {pins P1[14]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 461.2000};
    {pins P1[13]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 400.0000};
    {pins P1[12]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 338.6000};
    {pins P1[11]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 277.2000};
    {pins P1[10]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 215.8000};
    {pins P1[9]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 154.4000};
    {pins P1[8]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 93.2000};
    {pins P1[7]} {reference nanosoc_chip_pads} {layers M2} {sides 2} {offset 31.8000};
    {pins P1[6]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 521.0000};
    {pins P1[5]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 459.6000};
    {pins P1[4]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 398.4000};
    {pins P1[3]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 337.0000};
    {pins P1[2]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 275.8000};
    {pins P1[1]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 214.6000};
    {pins P1[0]} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 153.2000};
    {pins SWDIOTMS} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 92.0000};
    {pins SWCLKTCK} {reference nanosoc_chip_pads} {layers M3} {sides 1} {offset 30.6000};
END PHYSICAL PIN CONSTRAINTS;