Skip to content
Snippets Groups Projects
Commit d5a2acbb authored by dam1n19's avatar dam1n19
Browse files

SOC1-230: Fixed my surname and updated interconnect subsystem

parent b1f0b4bd
No related branches found
No related tags found
1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
Expand all Hide whitespace changes
Inline Side-by-side
Showing
with 390 additions and 440 deletions
system/nanosoc_interconnect/verilog/nanosoc_interconnect.v deleted 100644 → 0
+ 0
− 415
View file @ b1f0b4bd
//-----------------------------------------------------------------------------
// NanoSoC Interconnect Level - Connects AHB Managers to Device Regions
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.masptone@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_interconnect #(
// AHB System Parameters
parameter SYS_ADDR_W = 32,
parameter SYS_DATA_W = 32,
// Default RAM Instantiation Parameters
parameter RAM_ADDR_W = 14,
parameter RAM_DATA_W = 32,
// System Manager Parameters
parameter DMA_CHANNEL_NUM = 2
)(
// System Clocks and Resets
input wire FCLK, // Free-running Clock
input wire SYSRESETn, // System Reset
input wire PORESETn, // Power On Reset
// Clocks, Gated-Clocks and Reset - Generated from CPU
output wire HCLK, // Clock
output wire SCLK, // System Clock
output wire HCLKG, // Gated Clock
output wire HRESETn, // Reset
// Clocks, Gated-Clocks and Resets - APB
input wire PCLK, // Clock
input wire PCLKG, // Gated Clock
input wire PRESETn, // Reset
// Clocks, Gated-Clocks and Resets - Debug
input wire DCLK, // Clock
input wire DCLKG, // Gated Clock
input wire DBGRESETn, // Reset
// Serial Wire Debug Interface
input wire SWCLK, // SWD data input
input wire SWDI, // SWD clock
output wire SWO, // SWD data output
output wire SWDOEN, // SWD data output enable
// Manager Reset Request Signals
input wire NANOSOC_SYSRESETREQ,
output wire SYSRESETREQ,
output wire WDOGRESETREQ,
output wire ADPRESETREQ,
// CPU Power Control/Status Signals
input wire SLEEPING,
input wire SLEEPDEEP,
input wire WAKEUP,
input wire WICENREQ,
input wire WICENACK,
input wire SLEEPHOLDREQn,
input wire SLEEPHOLDACKn,
input wire CDBGPWRUPACK,
input wire CDBGPWRUPREQ,
// SoCDebug Controller AHB-lite Subordinate Interface
input wire [31:0] HADDR32_SOCDEBUG_o,
input wire [ 2:0] HBURST3_SOCDEBUG_o,
input wire HMASTLOCK_SOCDEBUG_o,
input wire [ 3:0] HPROT4_SOCDEBUG_o,
input wire [ 2:0] HSIZE3_SOCDEBUG_o,
input wire [ 1:0] HTRANS2_SOCDEBUG_o,
input wire [31:0] HWDATA32_SOCDEBUG_o,
input wire HWRITE_SOCDEBUG_o,
output wire [31:0] HRDATA32_SOCDEBUG_i,
output wire HREADY_SOCDEBUG_i,
output wire HRESP_SOCDEBUG_i,
// SoCDebug Controller APB Manager Interface
output wire PSEL_SOCDEBUG_i, // Device select
output wire [11:2] PADDR_SOCDEBUG_i, // Address
output wire PENABLE_SOCDEBUG_i, // Transfer control
output wire PWRITE_SOCDEBUG_i, // Write control
output wire [31:0] PWDATA_SOCDEBUG_i, // Write data
input wire [31:0] PRDATA_SOCDEBUG_o, // Read data
input wire PREADY_SOCDEBUG_o, // Device ready
input wire PSLVERR_SOCDEBUG_o, // Device error response
// TestMode Interface
input wire TESTMODE, // In Testmode
input wire SCANENABLE // Scanmode Enable
);
//--------------------------------
// AHB-lite System Managers
//--------------------------------
//--------------------------------
// CPU_0
//--------------------------------
// Connectivity - AHB
wire [31:0] HADDR_CPU_0;
wire [1:0] HTRANS_CPU_0;
wire HWRITE_CPU_0;
wire [2:0] HSIZE_CPU_0;
wire [2:0] HBURST_CPU_0;
wire [3:0] HPROT_CPU_0;
wire [31:0] HWDATA_CPU_0;
wire HMASTLOCK_CPU_0;
wire [31:0] HREADY_CPU_0;
wire HRDATA_CPU_0;
wire HRESP_CPU_0;
// Connectivity - CPU Sidebank Signals
wire [31:0] SYS_NMI;
wire SYS_APB_IRQ;
// Instantiate Cortex-M0
nanosoc_manager_cortexm0 u_cpu_0 (
.HCLK (HCLKG),
.FCLK (FCLK),
.DCLK (DCLK),
.SCLK (SCLK),
.HRESETn (HRESETn),
.PORESETn (PORESETn),
.DBGRESETn (DBGRESETn),
.RSTBYPASS (TESTMODE),
.DFTSE (SCANENABLE),
// AHB-lite port
.HADDR (HADDR_CPU_0),
.HTRANS (HTRANS_CPU_0),
.HWRITE (HWRITE_CPU_0),
.HSIZE (HSIZE_CPU_0),
.HBURST (HBURST_CPU_0),
.HPROT (HPROT_CPU_0),
.HWDATA (HWDATA_CPU_0),
.HMASTLOCK (HMASTLOCK_CPU_0),
.HREADY (HREADY_CPU_0),
.HRDATA (HRDATA_CPU_0),
.HRESP (HRESP_CPU_0),
// Sideband Signals
.NMI (SYS_NMI), // Non-maskable interrupt input
.IRQ (intisr_cm0[31:0]), // Interrupt request inputs - TODO: Need to generate this in own module/wrapper
.TXEV ( ), // Event output (SEV executed)
.RXEV (RXEV), // Event input
// CPU Control/Status Signals - TODO: Rename, Reroute and Restructure
.SLEEPING (SLEEPING),
.SLEEPDEEP (SLEEPDEEP),
.WAKEUP (WAKEUP), // Wake up request from WIC
.WICENREQ (WICENREQ), // WIC enable request from PMU
.WICENACK (WICENACK), // WIC enable ack to PMU
.SLEEPHOLDREQn (SLEEPHOLDREQn),
.SLEEPHOLDACKn (SLEEPHOLDACKn),
.CDBGPWRUPACK (CDBGPWRUPACK),
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.LOCKUP (LOCKUP), // Core is locked-up
.GATEHCLK (GATEHCLK),
.SYSRESETREQ (SYSRESETREQ), // System reset request
.WDOGRESETREQ (WDOGRESETREQ), // Watchdog HW reset request
.ADPRESETREQ (ADPRESETREQ), // ADP debugger reset request
// Serial Wire Debug Signals
.SWDI (SWDI),
.SWCLK (SWCLK),
.SWDO (SWDO),
.SWDOEN (SWDOEN)
);
//--------------------------------
// DMAC_0
//--------------------------------
// Connectivity - DMAC Interrupt Control
wire [DMA_CHANNEL_NUM-1:0] DMAC_0_CH_DONE;
wire DMAC_0_DONE;
// Instantiate DMA_0 - DMA230
//--------------------------------
// DMAC_1
//--------------------------------
// Instantiate DMA_1 - Not Implemented
//--------------------------------
// AHB-lite Address Regions
//--------------------------------
// Instantiate BootROM Region
//--------------------------------
// AHB-lite Bus Matrix
//--------------------------------
// Instantiate NanoSoC Bus Matrix
nanosoc_busmatrix_lite u_busmatrix (
// AHB Clock and Reset Signals
.HCLK (FCLK),
.HRESETn (SYSRESETn),
// System Address Remap Control
.REMAP ({3'b0, !ROM_REMAP}),
// Manager Input Signals for SoCDebug Controller - Instantiated at Chip Level
.HADDR_SOCDEBUG (HADDR32_SOCDEBUG_o),
.HTRANS_SOCDEBUG (HTRANS2_SOCDEBUG_o),
.HWRITE_SOCDEBUG (HWRITE_SOCDEBUG_o),
.HSIZE_SOCDEBUG (HSIZE3_SOCDEBUG_o),
.HBURST_SOCDEBUG (HBURST3_SOCDEBUG_o),
.HPROT_SOCDEBUG (HPROT4_SOCDEBUG_o),
.HWDATA_SOCDEBUG (HWDATA32_SOCDEBUG_o),
.HMASTLOCK_SOCDEBUG (HMASTLOCK_SOCDEBUG_o),
.HREADY_SOCDEBUG (HREADY_SOCDEBUG_i),
.HRDATA_SOCDEBUG (HRDATA32_SOCDEBUG_i),
.HRESP_SOCDEBUG (HRESP_SOCDEBUG_i),
// Manager Input Signals for DMA Controller 0 - DMA230
.HADDR_DMAC_0 (HADDR_DMAC_0),
.HTRANS_DMAC_0 (HTRANS_DMAC_0),
.HWRITE_DMAC_0 (HWRITE_DMAC_0),
.HSIZE_DMAC_0 (HSIZE_DMAC_0),
.HBURST_DMAC_0 (HBURST_DMAC_0),
.HPROT_DMAC_0 (HPROT_DMAC_0),
.HWDATA_DMAC_0 (HWDATA_DMAC_0),
.HMASTLOCK_DMAC_0 (HMASTLOCK_DMAC_0),
.HREADY_DMAC_0 (HREADY_DMAC_0),
.HRDATA_DMAC_0 (HRDATA_DMAC_0),
.HRESP_DMAC_0 (HRESP_DMAC_0),
// Manager Input Signals for DMA Controller 1 - Not Initialised
.HADDR_DMAC_1 (HADDR_DMAC_1),
.HTRANS_DMAC_1 (HTRANS_DMAC_1),
.HWRITE_DMAC_1 (HWRITE_DMAC_1),
.HSIZE_DMAC_1 (HSIZE_DMAC_1),
.HBURST_DMAC_1 (HBURST_DMAC_1),
.HPROT_DMAC_1 (HPROT_DMAC_1),
.HWDATA_DMAC_1 (HWDATA_DMAC_1),
.HMASTLOCK_DMAC_1 (HMASTLOCK_DMAC_1),
.HREADY_DMAC_1 (HREADY_DMAC_1),
.HRESP_DMAC_1 (HRESP_DMAC_1),
// Manager Input Signals for CPU 0 - Cortex-M0
.HADDR_CPU_0 (HADDR_CPU_0),
.HTRANS_CPU_0 (HTRANS_CPU_0),
.HWRITE_CPU_0 (HWRITE_CPU_0),
.HSIZE_CPU_0 (HSIZE_CPU_0),
.HBURST_CPU_0 (HBURST_CPU_0),
.HPROT_CPU_0 (HPROT_CPU_0),
.HWDATA_CPU_0 (HWDATA_CPU_0),
.HMASTLOCK_CPU_0 (HMASTLOCK_CPU_0),
.HREADY_CPU_0 (HREADY_CPU_0),
.HRDATA_CPU_0 (HRDATA_CPU_0),
.HRESP_CPU_0 (HRESP_CPU_0),
// Subordinate Output Signals for Bootrom Region
.HSEL_BOOTROM (HSEL_BOOTROM),
.HADDR_BOOTROM (HADDR_BOOTROM),
.HTRANS_BOOTROM (HTRANS_BOOTROM),
.HWRITE_BOOTROM (HWRITE_BOOTROM),
.HSIZE_BOOTROM (HSIZE_BOOTROM),
.HBURST_BOOTROM (HBURST_BOOTROM),
.HPROT_BOOTROM (HPROT_BOOTROM),
.HWDATA_BOOTROM (HWDATA_BOOTROM),
.HMASTLOCK_BOOTROM (HMASTLOCK_BOOTROM),
.HREADYMUX_BOOTROM (HREADYMUX_BOOTROM),
.HRDATA_BOOTROM (HRDATA_BOOTROM),
.HREADYOUT_BOOTROM (HREADYOUT_BOOTROM),
.HRESP_BOOTROM (HRESP_BOOTROM),
// Subordinate Output Signals for CPU Instruction Memory Region
.HSEL_IMEM (HSEL_IMEM),
.HADDR_IMEM (HADDR_IMEM),
.HTRANS_IMEM (HTRANS_IMEM),
.HWRITE_IMEM (HWRITE_IMEM),
.HSIZE_IMEM (HSIZE_IMEM),
.HBURST_IMEM (HBURST_IMEM),
.HPROT_IMEM (HPROT_IMEM),
.HWDATA_IMEM (HWDATA_IMEM),
.HMASTLOCK_IMEM (HMASTLOCK_IMEM),
.HREADYMUX_IMEM (HREADYMUX_IMEM),
.HRDATA_IMEM (HRDATA_IMEM),
.HREADYOUT_IMEM (HREADYOUT_IMEM),
.HRESP_IMEM (HRESP_IMEM),
// Subordinate Output Signals for CPU Data Memory Region
.HSEL_DMEM (HSEL_DMEM),
.HADDR_DMEM (HADDR_DMEM),
.HTRANS_DMEM (HTRANS_DMEM),
.HWRITE_DMEM (HWRITE_DMEM),
.HSIZE_DMEM (HSIZE_DMEM),
.HBURST_DMEM (HBURST_DMEM),
.HPROT_DMEM (HPROT_DMEM),
.HWDATA_DMEM (HWDATA_DMEM),
.HMASTLOCK_DMEM (HMASTLOCK_DMEM),
.HREADYMUX_DMEM (HREADYMUX_DMEM),
.HRDATA_DMEM (HRDATA_DMEM),
.HREADYOUT_DMEM (HREADYOUT_DMEM),
.HRESP_DMEM (HRESP_DMEM),
// Subordinate Output Signals for System Peripheral Region
.HSEL_SYSIO (HSEL_SYSIO),
.HADDR_SYSIO (HADDR_SYSIO),
.HTRANS_SYSIO (HTRANS_SYSIO),
.HWRITE_SYSIO (HWRITE_SYSIO),
.HSIZE_SYSIO (HSIZE_SYSIO),
.HBURST_SYSIO (HBURST_SYSIO),
.HPROT_SYSIO (HPROT_SYSIO),
.HWDATA_SYSIO (HWDATA_SYSIO),
.HMASTLOCK_SYSIO (HMASTLOCK_SYSIO),
.HREADYMUX_SYSIO (HREADYMUX_SYSIO),
.HRDATA_SYSIO (HRDATA_SYSIO),
.HREADYOUT_SYSIO (HREADYOUT_SYSIO),
.HRESP_SYSIO (HRESP_SYSIO),
// Subordinate Output Signals for Expansion 0 Region
.HSEL_EXP_0 (HSEL_EXP_0),
.HADDR_EXP_0 (HADDR_EXP_0),
.HTRANS_EXP_0 (HTRANS_EXP_0),
.HWRITE_EXP_0 (HWRITE_EXP_0),
.HSIZE_EXP_0 (HSIZE_EXP_0),
.HBURST_EXP_0 (HBURST_EXP_0),
.HPROT_EXP_0 (HPROT_EXP_0),
.HWDATA_EXP_0 (HWDATA_EXP_0),
.HMASTLOCK_EXP_0 (HMASTLOCK_EXP_0),
.HREADYMUX_EXP_0 (HREADYMUX_EXP_0),
.HRDATA_EXP_0 (HRDATA_EXP_0),
.HREADYOUT_EXP_0 (HREADYOUT_EXP_0),
.HRESP_EXP_0 (HRESP_EXP_0),
// Subordinate Output Signals for Low Expansion RAM Region
.HSEL_EXPRAM_L (HSEL_EXPRAM_L),
.HADDR_EXPRAM_L (HADDR_EXPRAM_L),
.HTRANS_EXPRAM_L (HTRANS_EXPRAM_L),
.HWRITE_EXPRAM_L (HWRITE_EXPRAM_L),
.HSIZE_EXPRAM_L (HSIZE_EXPRAM_L),
.HBURST_EXPRAM_L (HBURST_EXPRAM_L),
.HPROT_EXPRAM_L (HPROT_EXPRAM_L),
.HWDATA_EXPRAM_L (HWDATA_EXPRAM_L),
.HMASTLOCK_EXPRAM_L (HMASTLOCK_EXPRAM_L),
.HREADYMUX_EXPRAM_L (HREADYMUX_EXPRAM_L),
.HRDATA_EXPRAM_L (HRDATA_EXPRAM_L),
.HREADYOUT_EXPRAM_L (HREADYOUT_EXPRAM_L),
.HRESP_EXPRAM_L (HRESP_EXPRAM_L),
// Subordinate Output Signals for High Expansion RAM Region
.HSEL_EXPRAM_H (HSEL_EXPRAM_H),
.HADDR_EXPRAM_H (HADDR_EXPRAM_H),
.HTRANS_EXPRAM_H (HTRANS_EXPRAM_H),
.HWRITE_EXPRAM_H (HWRITE_EXPRAM_H),
.HSIZE_EXPRAM_H (HSIZE_EXPRAM_H),
.HBURST_EXPRAM_H (HBURST_EXPRAM_H),
.HPROT_EXPRAM_H (HPROT_EXPRAM_H),
.HWDATA_EXPRAM_H (HWDATA_EXPRAM_H),
.HMASTLOCK_EXPRAM_H (HMASTLOCK_EXPRAM_H),
.HREADYMUX_EXPRAM_H (HREADYMUX_EXPRAM_H),
.HRDATA_EXPRAM_H (HRDATA_EXPRAM_H),
.HREADYOUT_EXPRAM_H (HREADYOUT_EXPRAM_H),
.HRESP_EXPRAM_H (HRESP_EXPRAM_H),
// Subordinate Output Signals for Expansion 1 Region
.HSEL_EXP_1 (HSEL_EXP_1),
.HADDR_EXP_1 (HADDR_EXP_1),
.HTRANS_EXP_1 (HTRANS_EXP_1),
.HWRITE_EXP_1 (HWRITE_EXP_1),
.HSIZE_EXP_1 (HSIZE_EXP_1),
.HBURST_EXP_1 (HBURST_EXP_1),
.HPROT_EXP_1 (HPROT_EXP_1),
.HWDATA_EXP_1 (HWDATA_EXP_1),
.HMASTLOCK_EXP_1 (HMASTLOCK_EXP_1),
.HREADYMUX_EXP_1 (HREADYMUX_EXP_1),
.HRDATA_EXP_1 (HRDATA_EXP_1),
.HREADYOUT_EXP_1 (HREADYOUT_EXP_1),
.HRESP_EXP_1 (HRESP_EXP_1),
// Subordinate Output Signals for Expansion 2 Region
.HSEL_EXP_2 (HSEL_EXP_2),
.HADDR_EXP_2 (HADDR_EXP_2),
.HTRANS_EXP_2 (HTRANS_EXP_2),
.HWRITE_EXP_2 (HWRITE_EXP_2),
.HSIZE_EXP_2 (HSIZE_EXP_2),
.HBURST_EXP_2 (HBURST_EXP_2),
.HPROT_EXP_2 (HPROT_EXP_2),
.HWDATA_EXP_2 (HWDATA_EXP_2),
.HMASTLOCK_EXP_2 (HMASTLOCK_EXP_2),
.HREADYMUX_EXP_2 (HREADYMUX_EXP_2),
.HRDATA_EXP_2 (HRDATA_EXP_2),
.HREADYOUT_EXP_2 (HREADYOUT_EXP_2),
.HRESP_EXP_2 (HRESP_EXP_2),
// Subordinate Output Signals for System Table Region
.HSEL_SYSTABLE (HSEL_SYSTABLE),
.HADDR_SYSTABLE (HADDR_SYSTABLE),
.HTRANS_SYSTABLE (HTRANS_SYSTABLE),
.HWRITE_SYSTABLE (HWRITE_SYSTABLE),
.HSIZE_SYSTABLE (HSIZE_SYSTABLE),
.HBURST_SYSTABLE (HBURST_SYSTABLE),
.HPROT_SYSTABLE (HPROT_SYSTABLE),
.HWDATA_SYSTABLE (HWDATA_SYSTABLE),
.HMASTLOCK_SYSTABLE (HMASTLOCK_SYSTABLE),
.HREADYMUX_SYSTABLE (HREADYMUX_SYSTABLE),
.HRDATA_SYSTABLE (HRDATA_SYSTABLE),
.HREADYOUT_SYSTABLE (HREADYOUT_SYSTABLE),
.HRESP_SYSTABLE (HRESP_SYSTABLE),
// Scan test dummy signals; not connected until scan insertion
.SCANENABLE (SCANENABLE),
.SCANINHCLK (SCANINHCLK),
.SCANOUTHCLK (SCANOUTHCLK)
);
endmodule
\ No newline at end of file
system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+ 1
− 1
View file @ d5a2acbb
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
// //
// Contributors // Contributors
// //
// David Mapstone (d.a.masptone@soton.ac.uk) // David Mapstone (d.a.mapstone@soton.ac.uk)
// //
// Copyright (C) 2023, SoC Labs (www.soclabs.org) // Copyright (C) 2023, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
......
system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
+ 1
− 1
View file @ d5a2acbb
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
// //
// Contributors // Contributors
// //
// David Mapstone (d.a.masptone@soton.ac.uk) // David Mapstone (d.a.mapstone@soton.ac.uk)
// //
// Copyright (C) 2023, SoC Labs (www.soclabs.org) // Copyright (C) 2023, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
......
system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
+ 1
− 1
View file @ d5a2acbb
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
// //
// Contributors // Contributors
// //
// David Mapstone (d.a.masptone@soton.ac.uk) // David Mapstone (d.a.mapstone@soton.ac.uk)
// //
// Copyright (C) 2023, SoC Labs (www.soclabs.org) // Copyright (C) 2023, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
......
system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v 0 → 100644
+ 386
− 0
View file @ d5a2acbb
This diff is collapsed.
system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+ 1
− 1
View file @ d5a2acbb
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
// //
// Contributors // Contributors
// //
// David Mapstone (d.a.masptone@soton.ac.uk) // David Mapstone (d.a.mapstone@soton.ac.uk)
// //
// Copyright (C) 2023, SoC Labs (www.soclabs.org) // Copyright (C) 2023, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
......
system/nanosoc_system/verilog/nanosoc_system.v 0 → 100644
+ 0
− 0
View file @ d5a2acbb
system/src/nanosoc_busmatrix/logs/nanosoc.log deleted 100644 → 0
+ 0
− 21
View file @ b1f0b4bd
==============================================================
= The confidential and proprietary information contained in this file may
= only be used by a person authorised under and to the extent permitted
= by a subsisting licensing agreement from Arm Limited or its affiliates.
=
= (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.
= ALL RIGHTS RESERVED
=
= This entire notice must be reproduced on all copies of this file
= and copies of this file may only be made by a person if such person is
= permitted to do so under the terms of a subsisting license agreement
= from Arm Limited or its affiliates.
=
= BuildBusMatrix.pl
=
= Run Date : 04/06/2023 08:46:46
==============================================================
ERROR (xmlparser): Cannot open the specified file for reading - aborting!
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment