diff --git a/system/nanosoc_chip/control/verilog/nanosoc_clkctrl.v b/system/nanosoc_control/verilog/nanosoc_clkctrl.v
similarity index 100%
rename from system/nanosoc_chip/control/verilog/nanosoc_clkctrl.v
rename to system/nanosoc_control/verilog/nanosoc_clkctrl.v
diff --git a/system/nanosoc_chip/control/verilog/nanosoc_pin_mux.v b/system/nanosoc_control/verilog/nanosoc_pin_mux.v
similarity index 100%
rename from system/nanosoc_chip/control/verilog/nanosoc_pin_mux.v
rename to system/nanosoc_control/verilog/nanosoc_pin_mux.v
diff --git a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v b/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
deleted file mode 100644
index 0765e09a70ab9a189244449752d81477ac3453bd..0000000000000000000000000000000000000000
--- a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
+++ /dev/null
@@ -1,415 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Interconnect Level - Connects AHB Managers to Device Regions
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.masptone@soton.ac.uk)
-//
-// Copyright (C) 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module nanosoc_interconnect #(
- // AHB System Parameters
- parameter SYS_ADDR_W = 32,
- parameter SYS_DATA_W = 32,
-
- // Default RAM Instantiation Parameters
- parameter RAM_ADDR_W = 14,
- parameter RAM_DATA_W = 32,
-
- // System Manager Parameters
- parameter DMA_CHANNEL_NUM = 2
-)(
- // System Clocks and Resets
- input wire FCLK, // Free-running Clock
- input wire SYSRESETn, // System Reset
- input wire PORESETn, // Power On Reset
-
- // Clocks, Gated-Clocks and Reset - Generated from CPU
- output wire HCLK, // Clock
- output wire SCLK, // System Clock
- output wire HCLKG, // Gated Clock
- output wire HRESETn, // Reset
-
- // Clocks, Gated-Clocks and Resets - APB
- input wire PCLK, // Clock
- input wire PCLKG, // Gated Clock
- input wire PRESETn, // Reset
-
- // Clocks, Gated-Clocks and Resets - Debug
- input wire DCLK, // Clock
- input wire DCLKG, // Gated Clock
- input wire DBGRESETn, // Reset
-
- // Serial Wire Debug Interface
- input wire SWCLK, // SWD data input
- input wire SWDI, // SWD clock
- output wire SWO, // SWD data output
- output wire SWDOEN, // SWD data output enable
-
- // Manager Reset Request Signals
- input wire NANOSOC_SYSRESETREQ,
- output wire SYSRESETREQ,
- output wire WDOGRESETREQ,
- output wire ADPRESETREQ,
-
- // CPU Power Control/Status Signals
- input wire SLEEPING,
- input wire SLEEPDEEP,
- input wire WAKEUP,
- input wire WICENREQ,
- input wire WICENACK,
- input wire SLEEPHOLDREQn,
- input wire SLEEPHOLDACKn,
- input wire CDBGPWRUPACK,
- input wire CDBGPWRUPREQ,
-
-
- // SoCDebug Controller AHB-lite Subordinate Interface
- input wire [31:0] HADDR32_SOCDEBUG_o,
- input wire [ 2:0] HBURST3_SOCDEBUG_o,
- input wire HMASTLOCK_SOCDEBUG_o,
- input wire [ 3:0] HPROT4_SOCDEBUG_o,
- input wire [ 2:0] HSIZE3_SOCDEBUG_o,
- input wire [ 1:0] HTRANS2_SOCDEBUG_o,
- input wire [31:0] HWDATA32_SOCDEBUG_o,
- input wire HWRITE_SOCDEBUG_o,
- output wire [31:0] HRDATA32_SOCDEBUG_i,
- output wire HREADY_SOCDEBUG_i,
- output wire HRESP_SOCDEBUG_i,
-
- // SoCDebug Controller APB Manager Interface
- output wire PSEL_SOCDEBUG_i, // Device select
- output wire [11:2] PADDR_SOCDEBUG_i, // Address
- output wire PENABLE_SOCDEBUG_i, // Transfer control
- output wire PWRITE_SOCDEBUG_i, // Write control
- output wire [31:0] PWDATA_SOCDEBUG_i, // Write data
- input wire [31:0] PRDATA_SOCDEBUG_o, // Read data
- input wire PREADY_SOCDEBUG_o, // Device ready
- input wire PSLVERR_SOCDEBUG_o, // Device error response
-
- // TestMode Interface
- input wire TESTMODE, // In Testmode
- input wire SCANENABLE // Scanmode Enable
-);
- //--------------------------------
- // AHB-lite System Managers
- //--------------------------------
-
- //--------------------------------
- // CPU_0
- //--------------------------------
- // Connectivity - AHB
- wire [31:0] HADDR_CPU_0;
- wire [1:0] HTRANS_CPU_0;
- wire HWRITE_CPU_0;
- wire [2:0] HSIZE_CPU_0;
- wire [2:0] HBURST_CPU_0;
- wire [3:0] HPROT_CPU_0;
- wire [31:0] HWDATA_CPU_0;
- wire HMASTLOCK_CPU_0;
- wire [31:0] HREADY_CPU_0;
- wire HRDATA_CPU_0;
- wire HRESP_CPU_0;
-
- // Connectivity - CPU Sidebank Signals
- wire [31:0] SYS_NMI;
- wire SYS_APB_IRQ;
-
-
- // Instantiate Cortex-M0
- nanosoc_manager_cortexm0 u_cpu_0 (
- .HCLK (HCLKG),
- .FCLK (FCLK),
- .DCLK (DCLK),
- .SCLK (SCLK),
- .HRESETn (HRESETn),
- .PORESETn (PORESETn),
- .DBGRESETn (DBGRESETn),
- .RSTBYPASS (TESTMODE),
- .DFTSE (SCANENABLE),
-
- // AHB-lite port
- .HADDR (HADDR_CPU_0),
- .HTRANS (HTRANS_CPU_0),
- .HWRITE (HWRITE_CPU_0),
- .HSIZE (HSIZE_CPU_0),
- .HBURST (HBURST_CPU_0),
- .HPROT (HPROT_CPU_0),
- .HWDATA (HWDATA_CPU_0),
- .HMASTLOCK (HMASTLOCK_CPU_0),
- .HREADY (HREADY_CPU_0),
- .HRDATA (HRDATA_CPU_0),
- .HRESP (HRESP_CPU_0),
-
- // Sideband Signals
- .NMI (SYS_NMI), // Non-maskable interrupt input
- .IRQ (intisr_cm0[31:0]), // Interrupt request inputs - TODO: Need to generate this in own module/wrapper
- .TXEV ( ), // Event output (SEV executed)
- .RXEV (RXEV), // Event input
-
- // CPU Control/Status Signals - TODO: Rename, Reroute and Restructure
- .SLEEPING (SLEEPING),
- .SLEEPDEEP (SLEEPDEEP),
- .WAKEUP (WAKEUP), // Wake up request from WIC
- .WICENREQ (WICENREQ), // WIC enable request from PMU
- .WICENACK (WICENACK), // WIC enable ack to PMU
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .CDBGPWRUPACK (CDBGPWRUPACK),
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
- .LOCKUP (LOCKUP), // Core is locked-up
- .GATEHCLK (GATEHCLK),
- .SYSRESETREQ (SYSRESETREQ), // System reset request
- .WDOGRESETREQ (WDOGRESETREQ), // Watchdog HW reset request
- .ADPRESETREQ (ADPRESETREQ), // ADP debugger reset request
-
- // Serial Wire Debug Signals
- .SWDI (SWDI),
- .SWCLK (SWCLK),
- .SWDO (SWDO),
- .SWDOEN (SWDOEN)
- );
-
- //--------------------------------
- // DMAC_0
- //--------------------------------
- // Connectivity - DMAC Interrupt Control
- wire [DMA_CHANNEL_NUM-1:0] DMAC_0_CH_DONE;
- wire DMAC_0_DONE;
-
- // Instantiate DMA_0 - DMA230
-
- //--------------------------------
- // DMAC_1
- //--------------------------------
- // Instantiate DMA_1 - Not Implemented
-
- //--------------------------------
- // AHB-lite Address Regions
- //--------------------------------
-
- // Instantiate BootROM Region
-
- //--------------------------------
- // AHB-lite Bus Matrix
- //--------------------------------
-
- // Instantiate NanoSoC Bus Matrix
- nanosoc_busmatrix_lite u_busmatrix (
- // AHB Clock and Reset Signals
- .HCLK (FCLK),
- .HRESETn (SYSRESETn),
-
- // System Address Remap Control
- .REMAP ({3'b0, !ROM_REMAP}),
-
- // Manager Input Signals for SoCDebug Controller - Instantiated at Chip Level
- .HADDR_SOCDEBUG (HADDR32_SOCDEBUG_o),
- .HTRANS_SOCDEBUG (HTRANS2_SOCDEBUG_o),
- .HWRITE_SOCDEBUG (HWRITE_SOCDEBUG_o),
- .HSIZE_SOCDEBUG (HSIZE3_SOCDEBUG_o),
- .HBURST_SOCDEBUG (HBURST3_SOCDEBUG_o),
- .HPROT_SOCDEBUG (HPROT4_SOCDEBUG_o),
- .HWDATA_SOCDEBUG (HWDATA32_SOCDEBUG_o),
- .HMASTLOCK_SOCDEBUG (HMASTLOCK_SOCDEBUG_o),
- .HREADY_SOCDEBUG (HREADY_SOCDEBUG_i),
- .HRDATA_SOCDEBUG (HRDATA32_SOCDEBUG_i),
- .HRESP_SOCDEBUG (HRESP_SOCDEBUG_i),
-
- // Manager Input Signals for DMA Controller 0 - DMA230
- .HADDR_DMAC_0 (HADDR_DMAC_0),
- .HTRANS_DMAC_0 (HTRANS_DMAC_0),
- .HWRITE_DMAC_0 (HWRITE_DMAC_0),
- .HSIZE_DMAC_0 (HSIZE_DMAC_0),
- .HBURST_DMAC_0 (HBURST_DMAC_0),
- .HPROT_DMAC_0 (HPROT_DMAC_0),
- .HWDATA_DMAC_0 (HWDATA_DMAC_0),
- .HMASTLOCK_DMAC_0 (HMASTLOCK_DMAC_0),
- .HREADY_DMAC_0 (HREADY_DMAC_0),
- .HRDATA_DMAC_0 (HRDATA_DMAC_0),
- .HRESP_DMAC_0 (HRESP_DMAC_0),
-
- // Manager Input Signals for DMA Controller 1 - Not Initialised
- .HADDR_DMAC_1 (HADDR_DMAC_1),
- .HTRANS_DMAC_1 (HTRANS_DMAC_1),
- .HWRITE_DMAC_1 (HWRITE_DMAC_1),
- .HSIZE_DMAC_1 (HSIZE_DMAC_1),
- .HBURST_DMAC_1 (HBURST_DMAC_1),
- .HPROT_DMAC_1 (HPROT_DMAC_1),
- .HWDATA_DMAC_1 (HWDATA_DMAC_1),
- .HMASTLOCK_DMAC_1 (HMASTLOCK_DMAC_1),
- .HREADY_DMAC_1 (HREADY_DMAC_1),
- .HRESP_DMAC_1 (HRESP_DMAC_1),
-
- // Manager Input Signals for CPU 0 - Cortex-M0
- .HADDR_CPU_0 (HADDR_CPU_0),
- .HTRANS_CPU_0 (HTRANS_CPU_0),
- .HWRITE_CPU_0 (HWRITE_CPU_0),
- .HSIZE_CPU_0 (HSIZE_CPU_0),
- .HBURST_CPU_0 (HBURST_CPU_0),
- .HPROT_CPU_0 (HPROT_CPU_0),
- .HWDATA_CPU_0 (HWDATA_CPU_0),
- .HMASTLOCK_CPU_0 (HMASTLOCK_CPU_0),
- .HREADY_CPU_0 (HREADY_CPU_0),
- .HRDATA_CPU_0 (HRDATA_CPU_0),
- .HRESP_CPU_0 (HRESP_CPU_0),
-
- // Subordinate Output Signals for Bootrom Region
- .HSEL_BOOTROM (HSEL_BOOTROM),
- .HADDR_BOOTROM (HADDR_BOOTROM),
- .HTRANS_BOOTROM (HTRANS_BOOTROM),
- .HWRITE_BOOTROM (HWRITE_BOOTROM),
- .HSIZE_BOOTROM (HSIZE_BOOTROM),
- .HBURST_BOOTROM (HBURST_BOOTROM),
- .HPROT_BOOTROM (HPROT_BOOTROM),
- .HWDATA_BOOTROM (HWDATA_BOOTROM),
- .HMASTLOCK_BOOTROM (HMASTLOCK_BOOTROM),
- .HREADYMUX_BOOTROM (HREADYMUX_BOOTROM),
- .HRDATA_BOOTROM (HRDATA_BOOTROM),
- .HREADYOUT_BOOTROM (HREADYOUT_BOOTROM),
- .HRESP_BOOTROM (HRESP_BOOTROM),
-
- // Subordinate Output Signals for CPU Instruction Memory Region
- .HSEL_IMEM (HSEL_IMEM),
- .HADDR_IMEM (HADDR_IMEM),
- .HTRANS_IMEM (HTRANS_IMEM),
- .HWRITE_IMEM (HWRITE_IMEM),
- .HSIZE_IMEM (HSIZE_IMEM),
- .HBURST_IMEM (HBURST_IMEM),
- .HPROT_IMEM (HPROT_IMEM),
- .HWDATA_IMEM (HWDATA_IMEM),
- .HMASTLOCK_IMEM (HMASTLOCK_IMEM),
- .HREADYMUX_IMEM (HREADYMUX_IMEM),
- .HRDATA_IMEM (HRDATA_IMEM),
- .HREADYOUT_IMEM (HREADYOUT_IMEM),
- .HRESP_IMEM (HRESP_IMEM),
-
- // Subordinate Output Signals for CPU Data Memory Region
- .HSEL_DMEM (HSEL_DMEM),
- .HADDR_DMEM (HADDR_DMEM),
- .HTRANS_DMEM (HTRANS_DMEM),
- .HWRITE_DMEM (HWRITE_DMEM),
- .HSIZE_DMEM (HSIZE_DMEM),
- .HBURST_DMEM (HBURST_DMEM),
- .HPROT_DMEM (HPROT_DMEM),
- .HWDATA_DMEM (HWDATA_DMEM),
- .HMASTLOCK_DMEM (HMASTLOCK_DMEM),
- .HREADYMUX_DMEM (HREADYMUX_DMEM),
- .HRDATA_DMEM (HRDATA_DMEM),
- .HREADYOUT_DMEM (HREADYOUT_DMEM),
- .HRESP_DMEM (HRESP_DMEM),
-
- // Subordinate Output Signals for System Peripheral Region
- .HSEL_SYSIO (HSEL_SYSIO),
- .HADDR_SYSIO (HADDR_SYSIO),
- .HTRANS_SYSIO (HTRANS_SYSIO),
- .HWRITE_SYSIO (HWRITE_SYSIO),
- .HSIZE_SYSIO (HSIZE_SYSIO),
- .HBURST_SYSIO (HBURST_SYSIO),
- .HPROT_SYSIO (HPROT_SYSIO),
- .HWDATA_SYSIO (HWDATA_SYSIO),
- .HMASTLOCK_SYSIO (HMASTLOCK_SYSIO),
- .HREADYMUX_SYSIO (HREADYMUX_SYSIO),
- .HRDATA_SYSIO (HRDATA_SYSIO),
- .HREADYOUT_SYSIO (HREADYOUT_SYSIO),
- .HRESP_SYSIO (HRESP_SYSIO),
-
- // Subordinate Output Signals for Expansion 0 Region
- .HSEL_EXP_0 (HSEL_EXP_0),
- .HADDR_EXP_0 (HADDR_EXP_0),
- .HTRANS_EXP_0 (HTRANS_EXP_0),
- .HWRITE_EXP_0 (HWRITE_EXP_0),
- .HSIZE_EXP_0 (HSIZE_EXP_0),
- .HBURST_EXP_0 (HBURST_EXP_0),
- .HPROT_EXP_0 (HPROT_EXP_0),
- .HWDATA_EXP_0 (HWDATA_EXP_0),
- .HMASTLOCK_EXP_0 (HMASTLOCK_EXP_0),
- .HREADYMUX_EXP_0 (HREADYMUX_EXP_0),
- .HRDATA_EXP_0 (HRDATA_EXP_0),
- .HREADYOUT_EXP_0 (HREADYOUT_EXP_0),
- .HRESP_EXP_0 (HRESP_EXP_0),
-
- // Subordinate Output Signals for Low Expansion RAM Region
- .HSEL_EXPRAM_L (HSEL_EXPRAM_L),
- .HADDR_EXPRAM_L (HADDR_EXPRAM_L),
- .HTRANS_EXPRAM_L (HTRANS_EXPRAM_L),
- .HWRITE_EXPRAM_L (HWRITE_EXPRAM_L),
- .HSIZE_EXPRAM_L (HSIZE_EXPRAM_L),
- .HBURST_EXPRAM_L (HBURST_EXPRAM_L),
- .HPROT_EXPRAM_L (HPROT_EXPRAM_L),
- .HWDATA_EXPRAM_L (HWDATA_EXPRAM_L),
- .HMASTLOCK_EXPRAM_L (HMASTLOCK_EXPRAM_L),
- .HREADYMUX_EXPRAM_L (HREADYMUX_EXPRAM_L),
- .HRDATA_EXPRAM_L (HRDATA_EXPRAM_L),
- .HREADYOUT_EXPRAM_L (HREADYOUT_EXPRAM_L),
- .HRESP_EXPRAM_L (HRESP_EXPRAM_L),
-
- // Subordinate Output Signals for High Expansion RAM Region
- .HSEL_EXPRAM_H (HSEL_EXPRAM_H),
- .HADDR_EXPRAM_H (HADDR_EXPRAM_H),
- .HTRANS_EXPRAM_H (HTRANS_EXPRAM_H),
- .HWRITE_EXPRAM_H (HWRITE_EXPRAM_H),
- .HSIZE_EXPRAM_H (HSIZE_EXPRAM_H),
- .HBURST_EXPRAM_H (HBURST_EXPRAM_H),
- .HPROT_EXPRAM_H (HPROT_EXPRAM_H),
- .HWDATA_EXPRAM_H (HWDATA_EXPRAM_H),
- .HMASTLOCK_EXPRAM_H (HMASTLOCK_EXPRAM_H),
- .HREADYMUX_EXPRAM_H (HREADYMUX_EXPRAM_H),
- .HRDATA_EXPRAM_H (HRDATA_EXPRAM_H),
- .HREADYOUT_EXPRAM_H (HREADYOUT_EXPRAM_H),
- .HRESP_EXPRAM_H (HRESP_EXPRAM_H),
-
- // Subordinate Output Signals for Expansion 1 Region
- .HSEL_EXP_1 (HSEL_EXP_1),
- .HADDR_EXP_1 (HADDR_EXP_1),
- .HTRANS_EXP_1 (HTRANS_EXP_1),
- .HWRITE_EXP_1 (HWRITE_EXP_1),
- .HSIZE_EXP_1 (HSIZE_EXP_1),
- .HBURST_EXP_1 (HBURST_EXP_1),
- .HPROT_EXP_1 (HPROT_EXP_1),
- .HWDATA_EXP_1 (HWDATA_EXP_1),
- .HMASTLOCK_EXP_1 (HMASTLOCK_EXP_1),
- .HREADYMUX_EXP_1 (HREADYMUX_EXP_1),
- .HRDATA_EXP_1 (HRDATA_EXP_1),
- .HREADYOUT_EXP_1 (HREADYOUT_EXP_1),
- .HRESP_EXP_1 (HRESP_EXP_1),
-
- // Subordinate Output Signals for Expansion 2 Region
- .HSEL_EXP_2 (HSEL_EXP_2),
- .HADDR_EXP_2 (HADDR_EXP_2),
- .HTRANS_EXP_2 (HTRANS_EXP_2),
- .HWRITE_EXP_2 (HWRITE_EXP_2),
- .HSIZE_EXP_2 (HSIZE_EXP_2),
- .HBURST_EXP_2 (HBURST_EXP_2),
- .HPROT_EXP_2 (HPROT_EXP_2),
- .HWDATA_EXP_2 (HWDATA_EXP_2),
- .HMASTLOCK_EXP_2 (HMASTLOCK_EXP_2),
- .HREADYMUX_EXP_2 (HREADYMUX_EXP_2),
- .HRDATA_EXP_2 (HRDATA_EXP_2),
- .HREADYOUT_EXP_2 (HREADYOUT_EXP_2),
- .HRESP_EXP_2 (HRESP_EXP_2),
-
- // Subordinate Output Signals for System Table Region
- .HSEL_SYSTABLE (HSEL_SYSTABLE),
- .HADDR_SYSTABLE (HADDR_SYSTABLE),
- .HTRANS_SYSTABLE (HTRANS_SYSTABLE),
- .HWRITE_SYSTABLE (HWRITE_SYSTABLE),
- .HSIZE_SYSTABLE (HSIZE_SYSTABLE),
- .HBURST_SYSTABLE (HBURST_SYSTABLE),
- .HPROT_SYSTABLE (HPROT_SYSTABLE),
- .HWDATA_SYSTABLE (HWDATA_SYSTABLE),
- .HMASTLOCK_SYSTABLE (HMASTLOCK_SYSTABLE),
- .HREADYMUX_SYSTABLE (HREADYMUX_SYSTABLE),
- .HRDATA_SYSTABLE (HRDATA_SYSTABLE),
- .HREADYOUT_SYSTABLE (HREADYOUT_SYSTABLE),
- .HRESP_SYSTABLE (HRESP_SYSTABLE),
-
- // Scan test dummy signals; not connected until scan insertion
- .SCANENABLE (SCANENABLE),
- .SCANINHCLK (SCANINHCLK),
- .SCANOUTHCLK (SCANOUTHCLK)
- );
-
-endmodule
\ No newline at end of file
diff --git a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
index 8c796e132aa82406ef99029fc4c920d1625da9b5..b50f230f85dff79a3ae61c33fd3eb9440a7a8a72 100644
--- a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+++ b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
@@ -4,7 +4,7 @@
//
// Contributors
//
-// David Mapstone (d.a.masptone@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
diff --git a/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v b/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
index 3b8aa0bace6168e5d0a7794b16ed576c2e61fbb9..3257983772d33c8fbad2c141ddd238fb0552a4b3 100644
--- a/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
+++ b/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
@@ -4,7 +4,7 @@
//
// Contributors
//
-// David Mapstone (d.a.masptone@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
diff --git a/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v b/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
index 9302f0f26a678896056e2c4509f4e369411498ff..3f3cf17edd2d7709f04a93cec38c3a0552e0501b 100644
--- a/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
+++ b/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
@@ -4,7 +4,7 @@
//
// Contributors
//
-// David Mapstone (d.a.masptone@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
diff --git a/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v b/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
new file mode 100644
index 0000000000000000000000000000000000000000..1f5697c7ec0d6cf06178a34ece18dd354a6de053
--- /dev/null
+++ b/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
@@ -0,0 +1,386 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Interconnect Subsystem
+// - Contains AHB Lite Bus Matrix
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright (C) 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_ss_interconnect #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32 // System Data Width
+)(
+ // System Clocks, Resets and Control
+ input wire SYS_HCLK, // AHB System Clock
+ input wire SYS_HRESETn, // AHB System Reset
+ input wire SYS_SCANENABLE, // Scan enable signal
+ input wire INC_SCANINHCLK, // HCLK scan input wire
+ output wire INC_SCANOUTHCLK, // Scan Chain Output
+
+ // System Address Remap control
+ input wire [3:0] SYS_REMAP_CTRL, // System Address REMAP control
+
+ // Debug Master Port
+ input wire [31:0] DEBUG_HADDR, // Address bus
+ input wire [1:0] DEBUG_HTRANS, // Transfer type
+ input wire DEBUG_HWRITE, // Transfer direction
+ input wire [2:0] DEBUG_HSIZE, // Transfer size
+ input wire [2:0] DEBUG_HBURST, // Burst type
+ input wire [3:0] DEBUG_HPROT, // Protection control
+ input wire [31:0] DEBUG_HWDATA, // Write data
+ input wire DEBUG_HMASTLOCK, // Locked Sequence
+ output wire [31:0] DEBUG_HRDATA, // Read data bus
+ output wire DEBUG_HREADY, // HREADY feedback
+ output wire DEBUG_HRESP, // Transfer response
+
+ // DMA Controller 0 Master Port
+ input wire [31:0] DMAC_0_HADDR, // Address bus
+ input wire [1:0] DMAC_0_HTRANS, // Transfer type
+ input wire DMAC_0_HWRITE, // Transfer direction
+ input wire [2:0] DMAC_0_HSIZE, // Transfer size
+ input wire [2:0] DMAC_0_HBURST, // Burst type
+ input wire [3:0] DMAC_0_HPROT, // Protection control
+ input wire [31:0] DMAC_0_HWDATA, // Write data
+ input wire DMAC_0_HMASTLOCK, // Locked Sequence
+ output wire [31:0] DMAC_0_HRDATA, // Read data bus
+ output wire DMAC_0_HREADY, // HREADY feedback
+ output wire DMAC_0_HRESP, // Transfer response
+
+
+ // DMAC Controller 1 Master Port
+ input wire [31:0] DMAC_1_HADDR, // Address bus
+ input wire [1:0] DMAC_1_HTRANS, // Transfer type
+ input wire DMAC_1_HWRITE, // Transfer direction
+ input wire [2:0] DMAC_1_HSIZE, // Transfer size
+ input wire [2:0] DMAC_1_HBURST, // Burst type
+ input wire [3:0] DMAC_1_HPROT, // Protection control
+ input wire [31:0] DMAC_1_HWDATA, // Write data
+ input wire DMAC_1_HMASTLOCK, // Locked Sequence
+ output wire [31:0] DMAC_1_HRDATA, // Read data bus
+ output wire DMAC_1_HREADY, // HREADY feedback
+ output wire DMAC_1_HRESP, // Transfer response
+
+ // CPU 0 Master Port
+ input wire [31:0] CPU_0_HADDR, // Address bus
+ input wire [1:0] CPU_0_HTRANS, // Transfer type
+ input wire CPU_0_HWRITE, // Transfer direction
+ input wire [2:0] CPU_0_HSIZE, // Transfer size
+ input wire [2:0] CPU_0_HBURST, // Burst type
+ input wire [3:0] CPU_0_HPROT, // Protection control
+ input wire [31:0] CPU_0_HWDATA, // Write data
+ input wire CPU_0_HMASTLOCK, // Locked Sequence
+ output wire [31:0] CPU_0_HRDATA, // Read data bus
+ output wire CPU_0_HREADY, // HREADY feedback
+ output wire CPU_0_HRESP, // Transfer response
+
+ // Bootrom 0 Region Slave Port
+ input wire [31:0] BOOTROM_0_HRDATA, // Read data bus
+ input wire BOOTROM_0_HREADYOUT, // HREADY feedback
+ input wire BOOTROM_0_HRESP, // Transfer response
+ output wire BOOTROM_0_HSEL, // Slave Select
+ output wire [31:0] BOOTROM_0_HADDR, // Address bus
+ output wire [1:0] BOOTROM_0_HTRANS, // Transfer type
+ output wire BOOTROM_0_HWRITE, // Transfer direction
+ output wire [2:0] BOOTROM_0_HSIZE, // Transfer size
+ output wire [2:0] BOOTROM_0_HBURST, // Burst type
+ output wire [3:0] BOOTROM_0_HPROT, // Protection control
+ output wire [31:0] BOOTROM_0_HWDATA, // Write data
+ output wire BOOTROM_0_HMASTLOCK, // Locked Sequence
+ output wire BOOTROM_0_HREADYMUX, // Transfer done
+
+ // CPU 0 Instruction Memory Region Slave Port
+ input wire [31:0] IMEM_0_HRDATA, // Read data bus
+ input wire IMEM_0_HREADYOUT, // HREADY feedback
+ input wire IMEM_0_HRESP, // Transfer response
+ output wire IMEM_0_HSEL, // Slave Select
+ output wire [31:0] IMEM_0_HADDR, // Address bus
+ output wire [1:0] IMEM_0_HTRANS, // Transfer type
+ output wire IMEM_0_HWRITE, // Transfer direction
+ output wire [2:0] IMEM_0_HSIZE, // Transfer size
+ output wire [2:0] IMEM_0_HBURST, // Burst type
+ output wire [3:0] IMEM_0_HPROT, // Protection control
+ output wire [31:0] IMEM_0_HWDATA, // Write data
+ output wire IMEM_0_HMASTLOCK, // Locked Sequence
+ output wire IMEM_0_HREADYMUX, // Transfer done
+
+ // CPU 0 Data Memory Region Slave Port
+ input wire [31:0] DMEM_0_HRDATA, // Read data bus
+ input wire DMEM_0_HREADYOUT, // HREADY feedback
+ input wire DMEM_0_HRESP, // Transfer response
+ output wire DMEM_0_HSEL, // Slave Select
+ output wire [31:0] DMEM_0_HADDR, // Address bus
+ output wire [1:0] DMEM_0_HTRANS, // Transfer type
+ output wire DMEM_0_HWRITE, // Transfer direction
+ output wire [2:0] DMEM_0_HSIZE, // Transfer size
+ output wire [2:0] DMEM_0_HBURST, // Burst type
+ output wire [3:0] DMEM_0_HPROT, // Protection control
+ output wire [31:0] DMEM_0_HWDATA, // Write data
+ output wire DMEM_0_HMASTLOCK, // Locked Sequence
+ output wire DMEM_0_HREADYMUX, // Transfer done
+
+ // System Peripheral Region Slave Port
+ input wire [31:0] SYSIO_HRDATA, // Read data bus
+ input wire SYSIO_HREADYOUT, // HREADY feedback
+ input wire SYSIO_HRESP, // Transfer response
+ output wire SYSIO_HSEL, // Slave Select
+ output wire [31:0] SYSIO_HADDR, // Address bus
+ output wire [1:0] SYSIO_HTRANS, // Transfer type
+ output wire SYSIO_HWRITE, // Transfer direction
+ output wire [2:0] SYSIO_HSIZE, // Transfer size
+ output wire [2:0] SYSIO_HBURST, // Burst type
+ output wire [3:0] SYSIO_HPROT, // Protection control
+ output wire [31:0] SYSIO_HWDATA, // Write data
+ output wire SYSIO_HMASTLOCK, // Locked Sequence
+ output wire SYSIO_HREADYMUX, // Transfer done
+
+ // Expansion Memory Low Region Slave Port
+ input wire [31:0] EXPRAM_L_HRDATA, // Read data bus
+ input wire EXPRAM_L_HREADYOUT, // HREADY feedback
+ input wire EXPRAM_L_HRESP, // Transfer response
+ output wire EXPRAM_L_HSEL, // Slave Select
+ output wire [31:0] EXPRAM_L_HADDR, // Address bus
+ output wire [1:0] EXPRAM_L_HTRANS, // Transfer type
+ output wire EXPRAM_L_HWRITE, // Transfer direction
+ output wire [2:0] EXPRAM_L_HSIZE, // Transfer size
+ output wire [2:0] EXPRAM_L_HBURST, // Burst type
+ output wire [3:0] EXPRAM_L_HPROT, // Protection control
+ output wire [31:0] EXPRAM_L_HWDATA, // Write data
+ output wire EXPRAM_L_HMASTLOCK, // Locked Sequence
+ output wire EXPRAM_L_HREADYMUX, // Transfer done
+
+ // Expansion Memory High Region Slave Port
+ input wire [31:0] EXPRAM_H_HRDATA, // Read data bus
+ input wire EXPRAM_H_HREADYOUT, // HREADY feedback
+ input wire EXPRAM_H_HRESP, // Transfer response
+ output wire EXPRAM_H_HSEL, // Slave Select
+ output wire [31:0] EXPRAM_H_HADDR, // Address bus
+ output wire [1:0] EXPRAM_H_HTRANS, // Transfer type
+ output wire EXPRAM_H_HWRITE, // Transfer direction
+ output wire [2:0] EXPRAM_H_HSIZE, // Transfer size
+ output wire [2:0] EXPRAM_H_HBURST, // Burst type
+ output wire [3:0] EXPRAM_H_HPROT, // Protection control
+ output wire [31:0] EXPRAM_H_HWDATA, // Write data
+ output wire EXPRAM_H_HMASTLOCK, // Locked Sequence
+ output wire EXPRAM_H_HREADYMUX, // Transfer done
+
+ // Expansion Region Slave Port
+ input wire [31:0] EXP_HRDATA, // Read data bus
+ input wire EXP_HREADYOUT, // HREADY feedback
+ input wire EXP_HRESP, // Transfer response
+ output wire EXP_HSEL, // Slave Select
+ output wire [31:0] EXP_HADDR, // Address bus
+ output wire [1:0] EXP_HTRANS, // Transfer type
+ output wire EXP_HWRITE, // Transfer direction
+ output wire [2:0] EXP_HSIZE, // Transfer size
+ output wire [2:0] EXP_HBURST, // Burst type
+ output wire [3:0] EXP_HPROT, // Protection control
+ output wire [31:0] EXP_HWDATA, // Write data
+ output wire EXP_HMASTLOCK, // Locked Sequence
+ output wire EXP_HREADYMUX, // Transfer done
+
+ // System ROM Table Region Slave Port
+ input wire [31:0] SYSTABLE_HRDATA, // Read data bus
+ input wire SYSTABLE_HREADYOUT, // HREADY feedback
+ input wire SYSTABLE_HRESP, // Transfer response
+ output wire SYSTABLE_HSEL, // Slave Select
+ output wire [31:0] SYSTABLE_HADDR, // Address bus
+ output wire [1:0] SYSTABLE_HTRANS, // Transfer type
+ output wire SYSTABLE_HWRITE, // Transfer direction
+ output wire [2:0] SYSTABLE_HSIZE, // Transfer size
+ output wire [2:0] SYSTABLE_HBURST, // Burst type
+ output wire [3:0] SYSTABLE_HPROT, // Protection control
+ output wire [31:0] SYSTABLE_HWDATA, // Write data
+ output wire SYSTABLE_HMASTLOCK, // Locked Sequence
+ output wire SYSTABLE_HREADYMUX // Transfer done
+);
+ // -------------------------------
+ // Bus Matrix Instantiation
+ // -------------------------------
+ nanosoc_busmatrix_lite u_busmatrix (
+ // System Clocks, Resets and Control
+ .HCLK (SYS_HCLK), // AHB System Clock
+ .HRESETn (SYS_HRESETn), // AHB System Reset
+ .SCANENABLE (SYS_SCANENABLE), // Scan enable signal
+ .SCANINHCLK (INC_SCANINHCLK), // HCLK scan input wire
+ .SCANOUTHCLK (INC_SCANOUTHCLK), // Scan Chain Output
+
+ // System Address Remap control
+ .REMAP (SYS_REMAP_CTRL), // System Address REMAP control
+
+ // Debug Master Port
+ .HADDR_DEBUG (DEBUG_HADDR), // Address bus
+ .HTRANS_DEBUG (DEBUG_HTRANS), // Transfer type
+ .HWRITE_DEBUG (DEBUG_HWRITE), // Transfer direction
+ .HSIZE_DEBUG (DEBUG_HSIZE), // Transfer size
+ .HBURST_DEBUG (DEBUG_HBURST), // Burst type
+ .HPROT_DEBUG (DEBUG_HPROT), // Protection control
+ .HWDATA_DEBUG (DEBUG_HWDATA), // Write data
+ .HMASTLOCK_DEBUG (DEBUG_HMASTLOCK), // Locked Sequence
+ .HRDATA_DEBUG (DEBUG_HRDATA), // Read data bus
+ .HREADY_DEBUG (DEBUG_HREADY), // HREADY feedback
+ .HRESP_DEBUG (DEBUG_HRESP), // Transfer response
+
+ // DMA Controller 0 Master Port
+ .HADDR_DMAC_0 (DMAC_0_HADDR), // Address bus
+ .HTRANS_DMAC_0 (DMAC_0_HTRANS), // Transfer type
+ .HWRITE_DMAC_0 (DMAC_0_HWRITE), // Transfer direction
+ .HSIZE_DMAC_0 (DMAC_0_HSIZE), // Transfer size
+ .HBURST_DMAC_0 (DMAC_0_HBURST), // Burst type
+ .HPROT_DMAC_0 (DMAC_0_HPROT), // Protection control
+ .HWDATA_DMAC_0 (DMAC_0_HWDATA), // Write data
+ .HMASTLOCK_DMAC_0 (DMAC_0_HMASTLOCK), // Locked Sequence
+ .HRDATA_DMAC_0 (DMAC_0_HRDATA), // Read data bus
+ .HREADY_DMAC_0 (DMAC_0_HREADY), // HREADY feedback
+ .HRESP_DMAC_0 (DMAC_0_HRESP), // Transfer response
+
+ // DMA Controller 1 Master Port
+ .HADDR_DMAC_1 (DMAC_1_HADDR), // Address bus
+ .HTRANS_DMAC_1 (DMAC_1_HTRANS), // Transfer type
+ .HWRITE_DMAC_1 (DMAC_1_HWRITE), // Transfer direction
+ .HSIZE_DMAC_1 (DMAC_1_HSIZE), // Transfer size
+ .HBURST_DMAC_1 (DMAC_1_HBURST), // Burst type
+ .HPROT_DMAC_1 (DMAC_1_HPROT), // Protection control
+ .HWDATA_DMAC_1 (DMAC_1_HWDATA), // Write data
+ .HMASTLOCK_DMAC_1 (DMAC_1_HMASTLOCK), // Locked Sequence
+ .HRDATA_DMAC_1 (DMAC_1_HRDATA), // Read data bus
+ .HREADY_DMAC_1 (DMAC_1_HREADY), // HREADY feedback
+ .HRESP_DMAC_1 (DMAC_1_HRESP), // Transfer response
+
+ // DMA Controller 1 Master Port
+ .HADDR_CPU_0 (CPU_0_HADDR), // Address bus
+ .HTRANS_CPU_0 (CPU_0_HTRANS), // Transfer type
+ .HWRITE_CPU_0 (CPU_0_HWRITE), // Transfer direction
+ .HSIZE_CPU_0 (CPU_0_HSIZE), // Transfer size
+ .HBURST_CPU_0 (CPU_0_HBURST), // Burst type
+ .HPROT_CPU_0 (CPU_0_HPROT), // Protection control
+ .HWDATA_CPU_0 (CPU_0_HWDATA), // Write data
+ .HMASTLOCK_CPU_0 (CPU_0_HMASTLOCK), // Locked Sequence
+ .HRDATA_CPU_0 (CPU_0_HRDATA), // Read data bus
+ .HREADY_CPU_0 (CPU_0_HREADY), // HREADY feedback
+ .HRESP_CPU_0 (CPU_0_HRESP), // Transfer response
+
+ // CPU 0 Bootrom Memory Region Slave Port
+ .HRDATA_BOOTROM_0 (BOOTROM_0_HRDATA), // Read data bus
+ .HREADYOUT_BOOTROM_0 (BOOTROM_0_HREADYOUT), // HREADY feedback
+ .HRESP_BOOTROM_0 (BOOTROM_0_HRESP), // Transfer response
+ .HSEL_BOOTROM_0 (BOOTROM_0_HSEL), // Slave Select
+ .HADDR_BOOTROM_0 (BOOTROM_0_HADDR), // Address bus
+ .HTRANS_BOOTROM_0 (BOOTROM_0_HTRANS), // Transfer type
+ .HWRITE_BOOTROM_0 (BOOTROM_0_HWRITE), // Transfer direction
+ .HSIZE_BOOTROM_0 (BOOTROM_0_HSIZE), // Transfer size
+ .HBURST_BOOTROM_0 (BOOTROM_0_HBURST), // Burst type
+ .HPROT_BOOTROM_0 (BOOTROM_0_HPROT), // Protection control
+ .HWDATA_BOOTROM_0 (BOOTROM_0_HWDATA), // Write data
+ .HMASTLOCK_BOOTROM_0 (BOOTROM_0_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_BOOTROM_0 (BOOTROM_0_HREADYMUX), // Transfer done
+
+ // CPU 0 Instruction Memory Region Slave Port
+ .HRDATA_IMEM_0 (IMEM_0_HRDATA), // Read data bus
+ .HREADYOUT_IMEM_0 (IMEM_0_HREADYOUT), // HREADY feedback
+ .HRESP_IMEM_0 (IMEM_0_HRESP), // Transfer response
+ .HSEL_IMEM_0 (IMEM_0_HSEL), // Slave Select
+ .HADDR_IMEM_0 (IMEM_0_HADDR), // Address bus
+ .HTRANS_IMEM_0 (IMEM_0_HTRANS), // Transfer type
+ .HWRITE_IMEM_0 (IMEM_0_HWRITE), // Transfer direction
+ .HSIZE_IMEM_0 (IMEM_0_HSIZE), // Transfer size
+ .HBURST_IMEM_0 (IMEM_0_HBURST), // Burst type
+ .HPROT_IMEM_0 (IMEM_0_HPROT), // Protection control
+ .HWDATA_IMEM_0 (IMEM_0_HWDATA), // Write data
+ .HMASTLOCK_IMEM_0 (IMEM_0_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_IMEM_0 (IMEM_0_HREADYMUX), // Transfer done
+
+ // CPU 0 Data Memory Region Slave Port
+ .HRDATA_DMEM_0 (DMEM_0_HRDATA), // Read data bus
+ .HREADYOUT_DMEM_0 (DMEM_0_HREADYOUT), // HREADY feedback
+ .HRESP_DMEM_0 (DMEM_0_HRESP), // Transfer response
+ .HSEL_DMEM_0 (DMEM_0_HSEL), // Slave Select
+ .HADDR_DMEM_0 (DMEM_0_HADDR), // Address bus
+ .HTRANS_DMEM_0 (DMEM_0_HTRANS), // Transfer type
+ .HWRITE_DMEM_0 (DMEM_0_HWRITE), // Transfer direction
+ .HSIZE_DMEM_0 (DMEM_0_HSIZE), // Transfer size
+ .HBURST_DMEM_0 (DMEM_0_HBURST), // Burst type
+ .HPROT_DMEM_0 (DMEM_0_HPROT), // Protection control
+ .HWDATA_DMEM_0 (DMEM_0_HWDATA), // Write data
+ .HMASTLOCK_DMEM_0 (DMEM_0_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_DMEM_0 (DMEM_0_HREADYMUX), // Transfer done
+
+ // System Peripheral Region Slave Port
+ .HRDATA_SYSIO (SYSIO_HRDATA), // Read data bus
+ .HREADYOUT_SYSIO (SYSIO_HREADYOUT), // HREADY feedback
+ .HRESP_SYSIO (SYSIO_HRESP), // Transfer response
+ .HSEL_SYSIO (SYSIO_HSEL), // Slave Select
+ .HADDR_SYSIO (SYSIO_HADDR), // Address bus
+ .HTRANS_SYSIO (SYSIO_HTRANS), // Transfer type
+ .HWRITE_SYSIO (SYSIO_HWRITE), // Transfer direction
+ .HSIZE_SYSIO (SYSIO_HSIZE), // Transfer size
+ .HBURST_SYSIO (SYSIO_HBURST), // Burst type
+ .HPROT_SYSIO (SYSIO_HPROT), // Protection control
+ .HWDATA_SYSIO (SYSIO_HWDATA), // Write data
+ .HMASTLOCK_SYSIO (SYSIO_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_SYSIO (SYSIO_HREADYMUX), // Transfer done
+
+ // Expansion Memory Low Region Slave Port
+ .HRDATA_EXPRAM_L (EXPRAM_L_HRDATA), // Read data bus
+ .HREADYOUT_EXPRAM_L (EXPRAM_L_HREADYOUT), // HREADY feedback
+ .HRESP_EXPRAM_L (EXPRAM_L_HRESP), // Transfer response
+ .HSEL_EXPRAM_L (EXPRAM_L_HSEL), // Slave Select
+ .HADDR_EXPRAM_L (EXPRAM_L_HADDR), // Address bus
+ .HTRANS_EXPRAM_L (EXPRAM_L_HTRANS), // Transfer type
+ .HWRITE_EXPRAM_L (EXPRAM_L_HWRITE), // Transfer direction
+ .HSIZE_EXPRAM_L (EXPRAM_L_HSIZE), // Transfer size
+ .HBURST_EXPRAM_L (EXPRAM_L_HBURST), // Burst type
+ .HPROT_EXPRAM_L (EXPRAM_L_HPROT), // Protection control
+ .HWDATA_EXPRAM_L (EXPRAM_L_HWDATA), // Write data
+ .HMASTLOCK_EXPRAM_L (EXPRAM_L_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_EXPRAM_L (EXPRAM_L_HREADYMUX), // Transfer done
+
+ // Expansion Memory High Region Slave Port
+ .HRDATA_EXPRAM_H (EXPRAM_H_HRDATA), // Read data bus
+ .HREADYOUT_EXPRAM_H (EXPRAM_H_HREADYOUT), // HREADY feedback
+ .HRESP_EXPRAM_H (EXPRAM_H_HRESP), // Transfer response
+ .HSEL_EXPRAM_H (EXPRAM_H_HSEL), // Slave Select
+ .HADDR_EXPRAM_H (EXPRAM_H_HADDR), // Address bus
+ .HTRANS_EXPRAM_H (EXPRAM_H_HTRANS), // Transfer type
+ .HWRITE_EXPRAM_H (EXPRAM_H_HWRITE), // Transfer direction
+ .HSIZE_EXPRAM_H (EXPRAM_H_HSIZE), // Transfer size
+ .HBURST_EXPRAM_H (EXPRAM_H_HBURST), // Burst type
+ .HPROT_EXPRAM_H (EXPRAM_H_HPROT), // Protection control
+ .HWDATA_EXPRAM_H (EXPRAM_H_HWDATA), // Write data
+ .HMASTLOCK_EXPRAM_H (EXPRAM_H_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_EXPRAM_H (EXPRAM_H_HREADYMUX), // Transfer done
+
+ // Expansion Region Slave Port
+ .HRDATA_EXP (EXP_HRDATA), // Read data bus
+ .HREADYOUT_EXP (EXP_HREADYOUT), // HREADY feedback
+ .HRESP_EXP (EXP_HRESP), // Transfer response
+ .HSEL_EXP (EXP_HSEL), // Slave Select
+ .HADDR_EXP (EXP_HADDR), // Address bus
+ .HTRANS_EXP (EXP_HTRANS), // Transfer type
+ .HWRITE_EXP (EXP_HWRITE), // Transfer direction
+ .HSIZE_EXP (EXP_HSIZE), // Transfer size
+ .HBURST_EXP (EXP_HBURST), // Burst type
+ .HPROT_EXP (EXP_HPROT), // Protection control
+ .HWDATA_EXP (EXP_HWDATA), // Write data
+ .HMASTLOCK_EXP (EXP_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_EXP (EXP_HREADYMUX), // Transfer done
+
+ // System ROM Table Region Slave Port
+ .HRDATA_SYSTABLE (SYSTABLE_HRDATA), // Read data bus
+ .HREADYOUT_SYSTABLE (SYSTABLE_HREADYOUT), // HREADY feedback
+ .HRESP_SYSTABLE (SYSTABLE_HRESP), // Transfer response
+ .HSEL_SYSTABLE (SYSTABLE_HSEL), // Slave Select
+ .HADDR_SYSTABLE (SYSTABLE_HADDR), // Address bus
+ .HTRANS_SYSTABLE (SYSTABLE_HTRANS), // Transfer type
+ .HWRITE_SYSTABLE (SYSTABLE_HWRITE), // Transfer direction
+ .HSIZE_SYSTABLE (SYSTABLE_HSIZE), // Transfer size
+ .HBURST_SYSTABLE (SYSTABLE_HBURST), // Burst type
+ .HPROT_SYSTABLE (SYSTABLE_HPROT), // Protection control
+ .HWDATA_SYSTABLE (SYSTABLE_HWDATA), // Write data
+ .HMASTLOCK_SYSTABLE (SYSTABLE_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_SYSTABLE (SYSTABLE_HREADYMUX) // Transfer done
+ );
+endmodule
\ No newline at end of file
diff --git a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index d4bddaf627ac6603d24b7bb3961ef424f05d2975..8385c372690cd64a22db84d7cc7919b7aee89cf3 100644
--- a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -5,7 +5,7 @@
//
// Contributors
//
-// David Mapstone (d.a.masptone@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
diff --git a/system/nanosoc_system/verilog/nanosoc_system.v b/system/nanosoc_system/verilog/nanosoc_system.v
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/system/src/nanosoc_busmatrix/logs/nanosoc.log b/system/src/nanosoc_busmatrix/logs/nanosoc.log
deleted file mode 100644
index 3c43290c7b9d6adbcd8a6d97215cf0750d2be790..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_busmatrix/logs/nanosoc.log
+++ /dev/null
@@ -1,21 +0,0 @@
-
-==============================================================
-= The confidential and proprietary information contained in this file may
-= only be used by a person authorised under and to the extent permitted
-= by a subsisting licensing agreement from Arm Limited or its affiliates.
-=
-= (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.
-= ALL RIGHTS RESERVED
-=
-= This entire notice must be reproduced on all copies of this file
-= and copies of this file may only be made by a person if such person is
-= permitted to do so under the terms of a subsisting license agreement
-= from Arm Limited or its affiliates.
-=
-= BuildBusMatrix.pl
-=
-= Run Date : 04/06/2023 08:46:46
-==============================================================
-
-ERROR (xmlparser): Cannot open the specified file for reading - aborting!
-