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Commit b1f0b4bd authored by dam1n19's avatar dam1n19
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SOC1-230: Added clock control and pin mux to systemctrl subsystem

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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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system/nanosoc_managers/socdebug/verilog/nanosoc_manager_socdebug.v deleted 100644 → 0
+ 0
− 106
View file @ 7b575353
//-----------------------------------------------------------------------------
// NanoSoC Wrapper for SoCDebug Chip Debug Manager
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_manager_socdebug #(
parameter PROMPT_CHAR = "]",
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
parameter integer FT1248_CLKON = 0 // FTDI clock always on - else quiet when no access
)(
// AHB-lite Master Interface - ADP
input wire HCLK,
input wire HRESETn,
output wire [31:0] HADDR32_o,
output wire [ 2:0] HBURST3_o,
output wire HMASTLOCK_o,
output wire [ 3:0] HPROT4_o,
output wire [ 2:0] HSIZE3_o,
output wire [ 1:0] HTRANS2_o,
output wire [31:0] HWDATA32_o,
output wire HWRITE_o,
input wire [31:0] HRDATA32_i,
input wire HREADY_i,
input wire HRESP_i,
// APB Slave Interface - USRT
input wire PCLK, // Clock
input wire PCLKG, // Gated Clock
input wire PRESETn, // Reset
input wire PSEL_i, // Device select
input wire [11:2] PADDR_i, // Address
input wire PENABLE_i, // Transfer control
input wire PWRITE_i, // Write control
input wire [31:0] PWDATA_i, // Write data
output wire [31:0] PRDATA_o, // Read data
output wire PREADY_o, // Device ready
output wire PSLVERR_o, // Device error response
// FT1248 Interace - FT1248
output wire FT_CLK_O, // SCLK
output wire FT_SSN_O, // SS_N
input wire FT_MISO_I, // MISO
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
// GPIO interface
output wire [7:0] GPO8_o,
input wire [7:0] GPI8_i
);
// Instantiate SoCDebug Controller
socdebug_ahb u_socdebug (
// AHB-lite Master Interface - ADP
.HCLK (HCLK),
.HRESETn (HRESETn),
.HADDR32_o (HADDR32_o),
.HBURST3_o (HBURST3_o),
.HMASTLOCK_o (HMASTLOCK_o),
.HPROT4_o (HPROT4_o),
.HSIZE3_o (HSIZE3_o),
.HTRANS2_o (HTRANS2_o),
.HWDATA32_o (HWDATA32_o),
.HWRITE_o (HWRITE_o),
.HRDATA32_i (HRDATA32_i),
.HREADY_i (HREADY_i),
.HRESP_i (HRESP_i),
// APB Slave Interface - USRT
.PCLK (PCLK),
.PCLKG (PCLKG),
.PRESETn (PRESETn),
.PSEL_i (PSEL_i),
.PADDR_i (PADDR_i),
.PENABLE_i (PENABLE_i),
.PWRITE_i (PWRITE_i),
.PWDATA_i (PWDATA_i),
.PRDATA_o (PRDATA_o),
.PREADY_o (PREADY_o),
.PSLVERR_o (PSLVERR_o),
// FT1248 Interace - FT1248
.FT_CLK_O (FT_CLK_O),
.FT_SSN_O (FT_SSN_O),
.FT_MISO_I (FT_MISO_I),
.FT_MIOSIO_O (FT_MIOSIO_O),
.FT_MIOSIO_E (FT_MIOSIO_E),
.FT_MIOSIO_Z (FT_MIOSIO_Z),
.FT_MIOSIO_I (FT_MIOSIO_I),
.FT_CLKDIV (FT_CLKDIV),
// GPIO interface
.GPO8_o (GPO8_o),
.GPI8_i (GPI8_i)
);
endmodule
\ No newline at end of file
system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+ 12
− 54
View file @ b1f0b4bd
...@@ -108,7 +108,6 @@ module nanosoc_region_sysio #( ...@@ -108,7 +108,6 @@ module nanosoc_region_sysio #(
localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
localparam BE = 0; localparam BE = 0;
// ------------------------------------------------------------ // ------------------------------------------------------------
...@@ -140,18 +139,11 @@ module nanosoc_region_sysio #( ...@@ -140,18 +139,11 @@ module nanosoc_region_sysio #(
wire [SYS_DATA_W-1:0] sysctrl_hrdata; wire [SYS_DATA_W-1:0] sysctrl_hrdata;
wire sysctrl_hresp; wire sysctrl_hresp;
// System ROM Table
wire sysrom_hsel; // AHB to System ROM Table - select
wire sysrom_hreadyout;
wire [SYS_DATA_W-1:0] sysrom_hrdata;
wire sysrom_hresp;
// AHB address decode // AHB address decode
nanosoc_sysio_decode #( nanosoc_sysio_decode #(
.BASEADDR_GPIO0 (BASEADDR_GPIO0), .BASEADDR_GPIO0 (BASEADDR_GPIO0),
.BASEADDR_GPIO1 (BASEADDR_GPIO1), .BASEADDR_GPIO1 (BASEADDR_GPIO1)
.BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE)
) u_addr_decode ( ) u_addr_decode (
// System Address // System Address
.hsel (HSEL), .hsel (HSEL),
...@@ -160,7 +152,6 @@ module nanosoc_region_sysio #( ...@@ -160,7 +152,6 @@ module nanosoc_region_sysio #(
.gpio0_hsel (gpio0_hsel), .gpio0_hsel (gpio0_hsel),
.gpio1_hsel (gpio1_hsel), .gpio1_hsel (gpio1_hsel),
.sysctrl_hsel (sysctrl_hsel), .sysctrl_hsel (sysctrl_hsel),
.sysrom_hsel (sysrom_hsel),
.defslv_hsel (defslv_hsel) .defslv_hsel (defslv_hsel)
); );
...@@ -170,8 +161,8 @@ module nanosoc_region_sysio #( ...@@ -170,8 +161,8 @@ module nanosoc_region_sysio #(
.PORT1_ENABLE (1), // GPIO Port 0 .PORT1_ENABLE (1), // GPIO Port 0
.PORT2_ENABLE (1), // GPIO Port 1 .PORT2_ENABLE (1), // GPIO Port 1
.PORT3_ENABLE (1), // SYS control .PORT3_ENABLE (1), // SYS control
.PORT4_ENABLE (1), // SYS ROM table .PORT4_ENABLE (1), // default
.PORT5_ENABLE (1), // default .PORT5_ENABLE (0),
.PORT6_ENABLE (0), .PORT6_ENABLE (0),
.PORT7_ENABLE (0), .PORT7_ENABLE (0),
.PORT8_ENABLE (0), .PORT8_ENABLE (0),
...@@ -197,11 +188,11 @@ module nanosoc_region_sysio #( ...@@ -197,11 +188,11 @@ module nanosoc_region_sysio #(
.HREADYOUT3 (sysctrl_hreadyout), .HREADYOUT3 (sysctrl_hreadyout),
.HRESP3 (sysctrl_hresp), .HRESP3 (sysctrl_hresp),
.HRDATA3 (sysctrl_hrdata), .HRDATA3 (sysctrl_hrdata),
.HSEL4 (sysrom_hsel), // Input Port 4 .HSEL4 (defslv_hsel), // Input Port 4
.HREADYOUT4 (sysrom_hreadyout), .HREADYOUT4 (defslv_hreadyout),
.HRESP4 (sysrom_hresp), .HRESP4 (defslv_hresp),
.HRDATA4 (sysrom_hrdata), .HRDATA4 (defslv_hrdata),
.HSEL5 (defslv_hsel), // Input Port 5 .HSEL5 (1'b0), // Input Port 5
.HREADYOUT5 (defslv_hreadyout), .HREADYOUT5 (defslv_hreadyout),
.HRESP5 (defslv_hresp), .HRESP5 (defslv_hresp),
.HRDATA5 (defslv_hrdata), .HRDATA5 (defslv_hrdata),
...@@ -240,39 +231,6 @@ module nanosoc_region_sysio #( ...@@ -240,39 +231,6 @@ module nanosoc_region_sysio #(
assign defslv_hrdata = 32'h00000000; // Default slave do not have read data assign defslv_hrdata = 32'h00000000; // Default slave do not have read data
// -------------------------------
// System ROM Table
// -------------------------------
nanosoc_ahb_cs_rom_table #(//.JEPID (),
//.JEPCONTINUATION (),
//.PARTNUMBER (),
//.REVISION (),
.BASE (BASEADDR_SYSROMTABLE),
// Entry 0 = Cortex-M0+ Processor
.ENTRY0BASEADDR (32'hE00FF000),
.ENTRY0PRESENT (1'b1),
// Entry 1 = CoreSight MTB-M0+
.ENTRY1BASEADDR (32'hF0200000),
.ENTRY1PRESENT (0))
u_system_rom_table
(//Outputs
.HRDATA (sysrom_hrdata[31:0]),
.HREADYOUT (sysrom_hreadyout),
.HRESP (sysrom_hresp),
//Inputs
.HCLK (HCLK),
.HSEL (sysrom_hsel),
.HADDR (HADDR[31:0]),
.HBURST (HBURST[2:0]),
.HMASTLOCK (HMASTLOCK),
.HPROT (HPROT[3:0]),
.HSIZE (HSIZE[2:0]),
.HTRANS (HTRANS[1:0]),
.HWDATA (HWDATA[31:0]),
.HWRITE (HWRITE),
.HREADY (HREADY),
.ECOREVNUM (4'h0));
// ------------------------------- // -------------------------------
// Peripherals // Peripherals
// ------------------------------- // -------------------------------
...@@ -377,10 +335,10 @@ module nanosoc_region_sysio #( ...@@ -377,10 +335,10 @@ module nanosoc_region_sysio #(
// APB subsystem for timers, UARTs // APB subsystem for timers, UARTs
nanosoc_sysio_apb_ss #( nanosoc_sysio_apb_ss #(
.APB_EXT_PORT12_ENABLE (1), .APB_EXT_PORT12_ENABLE (1), // DMAC 1
.APB_EXT_PORT13_ENABLE (1), .APB_EXT_PORT13_ENABLE (0), // Not Used
.APB_EXT_PORT14_ENABLE (1), .APB_EXT_PORT14_ENABLE (1), // USRT
.APB_EXT_PORT15_ENABLE (1), .APB_EXT_PORT15_ENABLE (1), // DMAC 0
.INCLUDE_IRQ_SYNCHRONIZER(0), // require IRQs to be HCLK synchronous .INCLUDE_IRQ_SYNCHRONIZER(0), // require IRQs to be HCLK synchronous
.INCLUDE_APB_TEST_SLAVE (1), // Include example test slave .INCLUDE_APB_TEST_SLAVE (1), // Include example test slave
.INCLUDE_APB_TIMER0 (1), // Include simple timer #0 .INCLUDE_APB_TIMER0 (1), // Include simple timer #0
......
system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+ 2
− 7
View file @ b1f0b4bd
...@@ -45,9 +45,7 @@ module nanosoc_sysio_decode #( ...@@ -45,9 +45,7 @@ module nanosoc_sysio_decode #(
// GPIO1 peripheral base address // GPIO1 peripheral base address
parameter BASEADDR_GPIO1 = 32'h4001_1000, parameter BASEADDR_GPIO1 = 32'h4001_1000,
// GPIO1 peripheral base address // GPIO1 peripheral base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000, parameter BASEADDR_SYSCTRL = 32'h4001_f000
// Location of the System ROM Table.
parameter BASEADDR_SYSROMTABLE = 32'hf000_0000
)( )(
// System Address // System Address
input wire hsel, input wire hsel,
...@@ -58,7 +56,6 @@ module nanosoc_sysio_decode #( ...@@ -58,7 +56,6 @@ module nanosoc_sysio_decode #(
output wire gpio0_hsel, output wire gpio0_hsel,
output wire gpio1_hsel, output wire gpio1_hsel,
output wire sysctrl_hsel, output wire sysctrl_hsel,
output wire sysrom_hsel,
// Default slave // Default slave
output wire defslv_hsel output wire defslv_hsel
...@@ -82,8 +79,6 @@ module nanosoc_sysio_decode #( ...@@ -82,8 +79,6 @@ module nanosoc_sysio_decode #(
BASEADDR_GPIO1[31:12]); // 0x40011000 BASEADDR_GPIO1[31:12]); // 0x40011000
assign sysctrl_hsel = hsel & (haddr[31:12]== assign sysctrl_hsel = hsel & (haddr[31:12]==
BASEADDR_SYSCTRL[31:12]); // 0x4001F000 BASEADDR_SYSCTRL[31:12]); // 0x4001F000
assign sysrom_hsel = hsel & (haddr[31:12]==
BASEADDR_SYSROMTABLE[31:12]); // 0xF0000000
// ---------------------------------------------------------- // ----------------------------------------------------------
// Default slave decode logic // Default slave decode logic
...@@ -91,7 +86,7 @@ module nanosoc_sysio_decode #( ...@@ -91,7 +86,7 @@ module nanosoc_sysio_decode #(
assign defslv_hsel = ~(apbsys_hsel | assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel | gpio0_hsel | gpio1_hsel |
sysctrl_hsel | sysrom_hsel sysctrl_hsel
); );
endmodule endmodule
system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
+ 21
− 21
View file @ b1f0b4bd
...@@ -12,28 +12,28 @@ ...@@ -12,28 +12,28 @@
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module nanosoc_region_systable #( module nanosoc_region_systable #(
parameter SYS_ADDR_W = 32, // System Address Width parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width parameter SYS_DATA_W = 32, // System Data Width
parameter SYSTABLE_BASE = 32'hf000_0000 // Base Address for System ROM Table parameter SYSTABLE_BASE = 32'hf000_0000 // Base Address for System ROM Table
)( )(
input wire HCLK, // Clock input wire HCLK, // Clock
input wire HRESETn, // Reset input wire HRESETn, // Reset
// AHB connection to Initiator // AHB connection to Initiator
input wire HSEL, // AHB region select input wire HSEL, // AHB region select
input wire [SYS_ADDR_W-1:0] HADDR, // AHB address input wire [SYS_ADDR_W-1:0] HADDR, // AHB address
input wire [ 2:0] HBURST, // AHB burst input wire [ 2:0] HBURST, // AHB burst
input wire HMASTLOCK, // AHB lock input wire HMASTLOCK, // AHB lock
input wire [ 3:0] HPROT, // AHB prot input wire [ 3:0] HPROT, // AHB prot
input wire [ 2:0] HSIZE, // AHB size input wire [ 2:0] HSIZE, // AHB size
input wire [ 1:0] HTRANS, // AHB transfer input wire [ 1:0] HTRANS, // AHB transfer
input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data
input wire HWRITE, // AHB write input wire HWRITE, // AHB write
input wire HREADY, // AHB ready input wire HREADY, // AHB ready
output wire [SYS_DATA_W-1:0] HRDATA, // AHB read-data output wire [SYS_DATA_W-1:0] HRDATA, // AHB read-data
output wire HRESP, // AHB response output wire HRESP, // AHB response
output wire HREADYOUT // AHB ready out output wire HREADYOUT // AHB ready out
); );
// ------------------------------- // -------------------------------
// System ROM Table // System ROM Table
......
system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+ 4
− 5
View file @ b1f0b4bd
...@@ -20,6 +20,7 @@ module nanosoc_ss_dma #( ...@@ -20,6 +20,7 @@ module nanosoc_ss_dma #(
// System AHB Clocks and Resets // System AHB Clocks and Resets
input wire SYS_HCLK, input wire SYS_HCLK,
input wire SYS_HRESETn, input wire SYS_HRESETn,
input wire SYS_PCLKEN, // APB clock enable
// DMAC 0 AHB Lite Port // DMAC 0 AHB Lite Port
output wire [SYS_ADDR_W-1:0] DMAC_0_HADDR, // Address bus output wire [SYS_ADDR_W-1:0] DMAC_0_HADDR, // Address bus
...@@ -35,7 +36,6 @@ module nanosoc_ss_dma #( ...@@ -35,7 +36,6 @@ module nanosoc_ss_dma #(
input wire DMAC_0_HRESP, // Transfer response input wire DMAC_0_HRESP, // Transfer response
// DMAC 0 APB Configurtation Port // DMAC 0 APB Configurtation Port
input wire DMAC_0_PCLKEN, // APB clock enable
input wire DMAC_0_PSEL, // APB peripheral select input wire DMAC_0_PSEL, // APB peripheral select
input wire DMAC_0_PEN, // APB transfer enable input wire DMAC_0_PEN, // APB transfer enable
input wire DMAC_0_PWRITE, // APB transfer direction input wire DMAC_0_PWRITE, // APB transfer direction
...@@ -62,7 +62,6 @@ module nanosoc_ss_dma #( ...@@ -62,7 +62,6 @@ module nanosoc_ss_dma #(
input wire DMAC_1_HRESP, // Transfer response input wire DMAC_1_HRESP, // Transfer response
// DMAC 1 APB Configurtation Port // DMAC 1 APB Configurtation Port
input wire DMAC_1_PCLKEN, // APB clock enable
input wire DMAC_1_PSEL, // APB peripheral select input wire DMAC_1_PSEL, // APB peripheral select
input wire DMAC_1_PEN, // APB transfer enable input wire DMAC_1_PEN, // APB transfer enable
input wire DMAC_1_PWRITE, // APB transfer direction input wire DMAC_1_PWRITE, // APB transfer direction
...@@ -86,8 +85,8 @@ module nanosoc_ss_dma #( ...@@ -86,8 +85,8 @@ module nanosoc_ss_dma #(
.CHANNEL_NUM (DMAC_0_CHANNEL_NUM) .CHANNEL_NUM (DMAC_0_CHANNEL_NUM)
) u_dmac_0 ( ) u_dmac_0 (
// AHB Clocks and Resets // AHB Clocks and Resets
.HCLK(DMAC_0_HCLK), .HCLK(SYS_HCLK),
.HRESETn(DMAC_0_HRESETn), .HRESETn(SYS_HRESETn),
// AHB Lite Port // AHB Lite Port
.HADDR(DMAC_0_HADDR), .HADDR(DMAC_0_HADDR),
...@@ -103,7 +102,7 @@ module nanosoc_ss_dma #( ...@@ -103,7 +102,7 @@ module nanosoc_ss_dma #(
.HRESP(DMAC_0_HRESP), .HRESP(DMAC_0_HRESP),
// APB Configuration Port // APB Configuration Port
.PCLKEN(DMAC_0_PCLKEN), .PCLKEN(SYS_PCLKEN),
.PSEL(DMAC_0_PSEL), .PSEL(DMAC_0_PSEL),
.PEN(DMAC_0_PEN), .PEN(DMAC_0_PEN),
.PWRITE(DMAC_0_PWRITE), .PWRITE(DMAC_0_PWRITE),
......
system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v 0 → 100644
+ 350
− 0
View file @ b1f0b4bd
//-----------------------------------------------------------------------------
// NanoSoC System Control and Peripheral Subsystem
// - Contains Clock Control, Pin Mux, System Peripherals and System ROM table
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.masptone@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_ss_systemctrl #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter APB_ADDR_W = 12, // APB Peripheral Address Width
parameter APB_DATA_W = 32, // APB Peripheral Data Width
parameter SYSTABLE_BASE = 32'hf000_0000, // Base Address of System ROM Table
parameter CLKGATE_PRESENT = 0
)(
// Free-running and Crystal Clock Output
output wire SYS_FCLK, // Free-running system clock
output wire SYS_XTALCLK_OUT, // Crystal Clock Output
// System Input Clocks and Resets
input wire SYS_PORESETn, // Power-On-Reset reset (active-low)
input wire SYS_TESTMODE, // Reset bypass in scan test
input wire SYS_HCLK, // AHB clock
input wire SYS_HRESETn, // AHB reset (active-low)
// SYSIO AHB interface
input wire SYSIO_HSEL, // AHB region select
input wire [SYS_ADDR_W-1:0] SYSIO_HADDR, // AHB address
input wire [ 2:0] SYSIO_HBURST, // AHB burst
input wire SYSIO_HMASTLOCK, // AHB lock
input wire [ 3:0] SYSIO_HPROT, // AHB prot
input wire [ 2:0] SYSIO_HSIZE, // AHB size
input wire [ 1:0] SYSIO_HTRANS, // AHB transfer
input wire [SYS_DATA_W-1:0] SYSIO_HWDATA, // AHB write data
input wire SYSIO_HWRITE, // AHB write
input wire SYSIO_HREADY, // AHB ready
output wire [SYS_DATA_W-1:0] SYSIO_HRDATA, // AHB read-data
output wire SYSIO_HRESP, // AHB response
output wire SYSIO_HREADYOUT, // AHB ready out
// System ROM Table AHB interface
input wire SYSTABLE_HSEL, // AHB region select
input wire [SYS_ADDR_W-1:0] SYSTABLE_HADDR, // AHB address
input wire [ 2:0] SYSTABLE_HBURST, // AHB burst
input wire SYSTABLE_HMASTLOCK, // AHB lock
input wire [ 3:0] SYSTABLE_HPROT, // AHB prot
input wire [ 2:0] SYSTABLE_HSIZE, // AHB size
input wire [ 1:0] SYSTABLE_HTRANS, // AHB transfer
input wire [SYS_DATA_W-1:0] SYSTABLE_HWDATA, // AHB write data
input wire SYSTABLE_HWRITE, // AHB write
input wire SYSTABLE_HREADY, // AHB ready
output wire [SYS_DATA_W-1:0] SYSTABLE_HRDATA, // AHB read-data
output wire SYSTABLE_HRESP, // AHB response
output wire SYSTABLE_HREADYOUT, // AHB ready out
// APB clocking control
output wire SYS_PCLK, // Peripheral clock
output wire SYS_PCLKG, // Gated Peripheral bus clock
output wire SYS_PRESETn, // Peripheral system and APB reset
output wire SYS_PCLKEN, // Clock divide control for AHB to APB bridge
// APB external Slave Interfaces
output wire SYSIO_PENABLE,
output wire SYSIO_PWRITE,
output wire [APB_ADDR_W-1:0] SYSIO_PADDR,
output wire [APB_DATA_W-1:0] SYSIO_PWDATA,
output wire USRT_PSEL,
input wire [APB_DATA_W-1:0] USRT_PRDATA,
input wire USRT_PREADY,
input wire USRT_PSLVERR,
output wire DMAC_0_PSEL,
input wire [APB_DATA_W-1:0] DMAC_0_PRDATA,
input wire DMAC_0_PREADY,
input wire DMAC_0_PSLVERR,
output wire DMAC_1_PSEL,
input wire [APB_DATA_W-1:0] DMAC_1_PRDATA,
input wire DMAC_1_PREADY,
input wire DMAC_1_PSLVERR,
// CPU sideband signalling
output wire SYS_NMI, // watchdog_interrupt;
output wire [31:0] SYS_APB_IRQ, // apbsubsys_interrupt;
output wire [15:0] SYS_GPIO0_IRQ, // GPIO 0 IRQs
output wire [15:0] SYS_GPIO1_IRQ, // GPIO 0 IRQs
// CPU power/reset control
output wire SYS_REMAP_CTRL, // REMAP control bit
output wire SYS_WDOGRESETREQ, // Watchdog reset request
output wire CPU_0_LOCKUPRESET, // System Controller cfg - reset if lockup
// System Reset Request Signals
output wire SYS_SYSRESETREQ, // System Request from System Managers
input wire SYS_PRMURESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
// Power Management Control and Status
output wire SYS_PMUENABLE, // System Controller cfg - Enable PMU
input wire SYS_PMUDBGRESETREQ, // Power Management Debug Reset Req
// CPU Status Signals
input wire CPU_0_LOCKUP, // Processor status - Locked up
input wire CPU_0_SLEEPING,
input wire CPU_0_SLEEPDEEP,
// GPIO
input wire [15:0] P0_IN, // GPIO 0 inputs
output wire [15:0] P0_OUT, // GPIO 0 outputs
output wire [15:0] P0_OUTEN, // GPIO 0 output enables
output wire [15:0] P0_ALTFUNC, // GPIO 0 alternate function (pin mux)
input wire [15:0] P1_IN, // GPIO 1 inputs
output wire [15:0] P1_OUT, // GPIO 1 outputs
output wire [15:0] P1_OUTEN, // GPIO 1 output enables
output wire [15:0] P1_ALTFUNC // GPIO 1 alternate function (pin mux)
);
// -------------------------------
// Internal Wiring
// -------------------------------
wire apbactive;
wire uart0_rxd; // Uart 0 receive data
wire uart0_txd; // Uart 0 transmit data
wire uart0_txen; // Uart 0 transmit data enable
wire uart1_rxd; // Uart 1 receive data
wire uart1_txd; // Uart 1 transmit data
wire uart1_txen; // Uart 1 transmit data enable
wire uart2_rxd; // Uart 2 receive data
wire uart2_txd; // Uart 2 transmit data
wire uart2_txen; // Uart 2 transmit data enable
wire timer0_extin; // Timer 0 external input
wire timer1_extin; // Timer 1 external input
// -------------------------------
// NanoSoC Clock Control Instantiation
// -------------------------------
nanosoc_clkctrl #(
.CLKGATE_PRESENT (CLKGATE_PRESENT)
) u_clkctrl(
// inputs
.XTAL1 (SYS_CLK),
.NRST (SYS_SYSRESETn),
.APBACTIVE (apbactive),
.SLEEPING (CPU_0_SLEEPING),
.SLEEPDEEP (CPU_0_SLEEPDEEP),
.LOCKUP (CPU_0_LOCKUP),
.LOCKUPRESET (CPU_0_LOCKUPRESET),
.SYSRESETREQ (SYS_PRMURESETREQ),
.DBGRESETREQ (SYS_PMUDBGRESETREQ),
.CGBYPASS (SYS_TESTMODE),
.RSTBYPASS (SYS_TESTMODE),
// outputs
.XTAL2 (SYS_XTALCLK_OUT),
.FCLK (SYS_FCLK),
.PCLK (SYS_PCLK),
.PCLKG (SYS_PCLKG),
.PCLKEN (SYS_PCLKEN),
.PRESETn (SYS_PRESETn)
);
// -------------------------------
// NanoSoC Pin Mux Instantiation
// -------------------------------
nanosoc_pin_mux u_pin_mux (
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
.uart0_txen (uart0_txen),
.uart1_rxd (uart1_rxd),
.uart1_txd (uart1_txd),
.uart1_txen (uart1_txen),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
.uart2_txen (uart2_txen),
// Timer
.timer0_extin (timer0_extin),
.timer1_extin (timer1_extin),
// IO Ports
.p0_in ( ), // was (p0_in) now from pad inputs),
.p0_out (P0_OUT),
.p0_outen (P0_OUT_EN),
.p0_altfunc (P0_ALTFUNC),
.p1_in ( ), // was(p1_in) now from pad inputs),
.p1_out (P1_OUT),
.p1_outen (P1_OUT_EN),
.p1_altfunc (P1_ALTFUNC),
// Debug
.i_trst_n ( ),
.i_swditms ( ), //i_swditms),
.i_swclktck ( ), //i_swclktck),
.i_tdi ( ),
.i_tdo ( ),
.i_tdoen_n ( ),
.i_swdo ( ),
.i_swdoen ( ),
// IO pads
.p1_out_mux (P1_OUT_MUX),
.p1_out_en_mux (P1_OUT_EN_MUX),
.P0 ( ), //P0),
.P1 ( ), //P1),
.nTRST (1'b1), // Not needed if serial-wire debug is used
.TDI (1'b0), // Not needed if serial-wire debug is used
.SWDIOTMS ( ), //SWDIOTMS),
.SWCLKTCK ( ), //SWCLKTCK),
.TDO ( ) // Not needed if serial-wire debug is used
);
// -------------------------------
// SYSIO Region Instantiation
// -------------------------------
nanosoc_region_sysio #(
.SYS_ADDR_W(SYS_ADDR_W),
.SYS_DATA_W(SYS_DATA_W),
.APB_ADDR_W(APB_ADDR_W),
.APB_DATA_W(APB_DATA_W)
) u_region_sysio (
// Clock and Reset
.FCLK(SYS_FCLK),
.PORESETn(SYS_PORESETn),
.TESTMODE(SYS_TESTMODE),
// AHB interface
.HCLK(SYSIO_SYS_HCLK),
.HRESETn(SYSIO_SYS_HRESETn),
.HSEL(SYSIO_HSEL),
.HADDR(SYSIO_HADDR),
.HBURST(SYSIO_HBURST),
.HMASTLOCK(SYSIO_HMASTLOCK),
.HPROT(SYSIO_HPROT),
.HSIZE(SYSIO_HSIZE),
.HTRANS(SYSIO_HTRANS),
.HWDATA(SYSIO_HWDATA),
.HWRITE(SYSIO_HWRITE),
.HREADY(SYSIO_HREADY),
.HRDATA(SYSIO_HRDATA),
.HRESP(SYSIO_HRESP),
.HREADYOUT(SYSIO_HREADYOUT),
// APB clocking control
.PCLK(SYS_PCLK),
.PCLKG(SYS_PCLKG),
.PRESETn(SYS_PRESETn),
.PCLKEN(SYS_PCLKEN),
// APB external Slave Interface
.exp12_psel(DMAC_1_PSEL),
.exp13_psel(),
.exp14_psel(USRT_PSEL),
.exp15_psel(DMAC_0_PSEL),
.exp_penable(SYSIO_PENABLE),
.exp_pwrite(SYSIO_PWRITE),
.exp_paddr(SYSIO_PADDR),
.exp_pwdata(SYSIO_PWDATA),
.exp12_prdata(DMAC_1_PRDATA),
.exp12_pready(DMAC_1_PREADY),
.exp12_pslverr(DMAC_1_PSLVERR),
.exp13_prdata({APB_ADDR_W{1'b0}}),
.exp13_pready(1'b1),
.exp13_pslverr(1'b1),
.exp14_prdata(USRT_PRDATA),
.exp14_pready(USRT_PREADY),
.exp14_pslverr(USRT_PSLVERR),
.exp15_prdata(DMAC_0_PRDATA),
.exp15_pready(DMAC_0_PREADY),
.exp15_pslverr(DMAC_0_PSLVERR),
// CPU sideband signaling
.SYS_NMI(SYS_NMI),
.SYS_APB_IRQ(SYS_APB_IRQ),
.SYS_GPIO0_IRQ(SYS_GPIO0_IRQ),
.SYS_GPIO1_IRQ(SYS_GPIO1_IRQ),
// CPU power/reset control
.REMAP_CTRL(SYS_REMAP_CTRL),
.APBACTIVE(apbactive),
.SYSRESETREQ(SYS_SYSRESETREQ),
.WDOGRESETREQ(SYS_WDOGRESETREQ),
.LOCKUP(CPU_0_LOCKUP),
.LOCKUPRESET(CPU_0_LOCKUPRESET),
.PMUENABLE(SYS_PMUENABLE),
// IO signaling
.uart0_rxd(uart1_txd), // crossover
.uart0_txd(uart0_txd),
.uart0_txen(uart0_txen),
.uart1_rxd(uart0_txd), // crossover
.uart1_txd(uart1_txd),
.uart1_txen(uart1_txen),
.uart2_rxd(uart2_rxd),
.uart2_txd(uart2_txd),
.uart2_txen(uart2_txen),
.timer0_extin(timer0_extin),
.timer1_extin(timer1_extin),
// GPIO
.p0_in(P0_IN),
.p0_out(P0_OUT),
.p0_outen(P0_OUTEN),
.p0_altfunc(P0_ALTFUNC),
.p1_in(P1_IN),
.p1_out(P1_OUT),
.p1_outen(P1_OUTEN),
.p1_altfunc(P1_ALTFUNC)
);
// --------------------------------------
// System ROM Table Region Instantiation
// --------------------------------------
nanosoc_region_systable #(
.SYS_ADDR_W(SYS_ADDR_W),
.SYS_DATA_W(SYS_DATA_W),
.SYSTABLE_BASE(SYSTABLE_BASE)
) u_region_systable (
// Clock and Reset
.HCLK(SYS_HCLK),
.HRESETn(SYS_HRESETn),
// AHB connection to Initiator
.HSEL(SYSTABLE_HSEL),
.HADDR(SYSTABLE_HADDR),
.HBURST(SYSTABLE_HBURST),
.HMASTLOCK(SYSTABLE_HMASTLOCK),
.HPROT(SYSTABLE_HPROT),
.HSIZE(SYSTABLE_HSIZE),
.HTRANS(SYSTABLE_HTRANS),
.HWDATA(SYSTABLE_HWDATA),
.HWRITE(SYSTABLE_HWRITE),
.HREADY(SYSTABLE_HREADY),
.HRDATA(SYSTABLE_HRDATA),
.HRESP(SYSTABLE_HRESP),
.HREADYOUT(SYSTABLE_HREADYOUT)
);
endmodule
\ No newline at end of file
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