Successful simulation on NanoSoC Refactoring

.gitignore

flist/nanosoc.flist

makefile

system/nanosoc_chip/chip/verilog/nanosoc_chip.v

system/nanosoc_chip/chip/verilog/nanosoc_chip_new.v

...em/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v

...anosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v

...anosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v

...em/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v

system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v

system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v

system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v

...nosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v

...soc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v

system/nanosoc_system/verilog/nanosoc_system.v

system/slcorem0_tech

system/sldma230_tech

system/socdebug_tech

verif/verilog/nanosoc_tb.v