From be8c5137ae9d04a798e6d6bdfa42b522397a1457 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 22 Jun 2023 09:15:38 +0100
Subject: [PATCH] Successful simulation on NanoSoC Refactoring
---
.gitignore | 17 +-
flist/nanosoc.flist | 78 +-
makefile | 4 +-
.../nanosoc_chip/chip/verilog/nanosoc_chip.v | 8 +-
.../chip/verilog/nanosoc_chip_new.v | 835 ------------------
.../dmem_0/verilog/nanosoc_region_dmem_0.v | 4 +-
.../verilog/nanosoc_region_expram_h.v | 4 +-
.../verilog/nanosoc_region_expram_l.v | 4 +-
.../imem_0/verilog/nanosoc_region_imem_0.v | 4 +-
.../cpu/verilog/nanosoc_ss_cpu.v | 32 +-
.../debug/verilog/nanosoc_ss_debug.v | 26 +-
.../dma/verilog/nanosoc_ss_dma.v | 22 +-
.../expansion/verilog/nanosoc_ss_expansion.v | 48 +-
.../verilog/nanosoc_ss_systemctrl.v | 9 +-
.../nanosoc_system/verilog/nanosoc_system.v | 197 +++--
system/slcorem0_tech | 2 +-
system/sldma230_tech | 2 +-
system/socdebug_tech | 2 +-
verif/verilog/nanosoc_tb.v | 50 +-
19 files changed, 300 insertions(+), 1048 deletions(-)
delete mode 100644 system/nanosoc_chip/chip/verilog/nanosoc_chip_new.v
diff --git a/.gitignore b/.gitignore
index 27c13fa..4f177e8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,15 +9,16 @@
/software/*/*.bin
# Compile Test Code Removal
-system/testcodes/*/*.elf
-system/testcodes/*/*.ELF
-system/testcodes/*/*.hex
-system/testcodes/*/*.lst
-system/testcodes/*/*.o
-system/testcodes/*/*.bin
-
+/testcodes/*/*.elf
+/testcodes/*/*.ELF
+/testcodes/*/*.hex
+/testcodes/*/*.lst
+/testcodes/*/*.o
+/testcodes/*/*.bin
# Bootrom removal
system/src/bootrom/
# Simulation Removal (If running at Tech Level)
-sim
\ No newline at end of file
+sim
+
+work
\ No newline at end of file
diff --git a/flist/nanosoc.flist b/flist/nanosoc.flist
index fc7bb4a..220cc3e 100644
--- a/flist/nanosoc.flist
+++ b/flist/nanosoc.flist
@@ -9,26 +9,74 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
+// Abstract : Verilog Command File for NanoSoC IP
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
-// ============= NanoSoC Bus Matrix IP search path =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
+// ============= NanoSoC IP search path =============
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_subsystem.v
+// NanoSoC Subsystems
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file
+
+// Bus Matrix
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
+-y $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
+
+// NanoSoC Regions - Bootrom
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
+
+// NanoSoC Regions - CPU Memories
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+
+// NanoSoC Regions - Expansion Regions
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
+
+// NanoSoC Regions - Sysio Region
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+
+// NanoSoC Regions - SysTable Region
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
+
+// NanoSoC Control
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_control/verilog/nanosoc_clkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_control/verilog/nanosoc_pin_mux.v
+
+// NanoSoC System
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_system/verilog/nanosoc_system.v
+
+// SLCore Files
+$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_integration.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_prmu.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_rstctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_stclkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0.v
+
+// Debug IP
+$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_adp_control.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_ahb.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_ft1248_control.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_usrt_control.v
+
+// DMAC IP
+$(SOCLABS_NANOSOC_TECH_DIR)/system/sldma230_tech/src/verilog/sldmac230.v
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/sldma230_tech/src/defines
+
diff --git a/makefile b/makefile
index f426e6b..427bc67 100644
--- a/makefile
+++ b/makefile
@@ -43,7 +43,7 @@ NANOSOC_SW_DIR ?= $(SOCLABS_NANOSOC_TECH_DIR)/software
NANOSOC_HTML_DIR := $(NANOSOC_SYSTEM_DIR)/html
VERILOG_DIR := $(NANOSOC_SYSTEM_DIR)/verilog
-TESTCODES_DIR := $(NANOSOC_SYSTEM_DIR)/testcodes
+TESTCODES_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/testcodes
# Project System Directory
PROJ_SYS_DIR := $(SOCLABS_PROJECT_DIR)/system
@@ -77,7 +77,7 @@ ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
# Boot Loader image
BOOTLOADER ?= bootloader
BOOTROM_ADDRW ?= 8
-BOOTROM_HEX ?= $(SOCLABS_NANOSOC_TECH_DIR)/system/testcodes/bootloader/$(BOOTLOADER).hex
+BOOTROM_HEX ?= $(SOCLABS_NANOSOC_TECH_DIR)/testcodes/bootloader/$(BOOTLOADER).hex
BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom
diff --git a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 8c4f729..9025f88 100644
--- a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -53,7 +53,6 @@ module nanosoc_chip #(
wire [FT1248_WIDTH-1:0] FT_MIOSIO_E; // MIOSIO tristate enable (active hi)
wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z; // MIOSIO tristate enable (active lo)
wire [FT1248_WIDTH-1:0] FT_MIOSIO_I; // MIOSIO tristate input
- wire [7:0] FT_CLKDIV; // divider prescaler to ensure SCLK <1MHz
// GPIO interface
wire [7:0] GPO8;
@@ -103,6 +102,7 @@ module nanosoc_chip #(
assign CPU_0_SWCLK = swdclk_i;
assign CPU_0_SWDI = swdio_i;
assign swdio_o = CPU_0_SWDO;
+ assign swdio_e = CPU_0_SWDOEN;
assign swdio_z = !CPU_0_SWDOEN;
//--------------------------
@@ -155,6 +155,7 @@ module nanosoc_chip #(
// Free-running and Crystal Clock Output
.SYS_CLK(SYS_CLK),
.SYS_XTALCLK_OUT(SYS_XTALCLK_OUT),
+ .SYS_SYSRESETn(nrst_i),
// Scan Wiring
.SYS_SCANENABLE(SYS_SCANENABLE),
@@ -176,7 +177,6 @@ module nanosoc_chip #(
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
- .FT_CLKDIV(FT_CLKDIV),
// GPIO interface
.GPO8(GPO8),
@@ -190,7 +190,9 @@ module nanosoc_chip #(
.P1_IN(P1_IN),
.P1_OUT(P1_OUT),
.P1_OUTEN(P1_OUTEN),
- .P1_ALTFUNC(P1_ALTFUNC)
+ .P1_ALTFUNC(P1_ALTFUNC),
+ .P1_OUT_MUX(P1_OUT_MUX),
+ .P1_OUT_EN_MUX(P1_OUT_EN_MUX)
);
endmodule
\ No newline at end of file
diff --git a/system/nanosoc_chip/chip/verilog/nanosoc_chip_new.v b/system/nanosoc_chip/chip/verilog/nanosoc_chip_new.v
deleted file mode 100644
index 8e4958d..0000000
--- a/system/nanosoc_chip/chip/verilog/nanosoc_chip_new.v
+++ /dev/null
@@ -1,835 +0,0 @@
-module nanosoc_chip #(
- parameter SYS_ADDR_W = 32,
- parameter SYS_DATA_W = 32,
- parameter RAM_ADDR_W = 14,
- parameter RAM_DATA_W = 32,
- parameter DMA_CHANNEL_NUM = 2,
- parameter CLKGATE_PRESENT = 0
- )(
- `ifdef POWER_PINS
- inout wire VDDIO,
- inout wire VSSIO,
- inout wire VDD,
- inout wire VSS,
- `endif
- input wire xtal_clk_i,
- output wire xtal_clk_o,
- input wire nrst_i,
- input wire [15:0] p0_i, // level-shifted input from pad
- output wire [15:0] p0_o, // output port drive
- output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
- output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
- input wire [15:0] p1_i, // level-shifted input from pad
- output wire [15:0] p1_o, // output port drive
- output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
- output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
- input wire swdio_i,
- output wire swdio_o,
- output wire swdio_e,
- output wire swdio_z,
- input wire swdclk_i
- );
-
- //------------------------------------
- // CMSDK internal wire naming preserved
- //------------------------------------
-
- wire xtal_clk_in;
- wire xtal_clk_out;
- wire pll_clk;
- wire CLK;
-
- assign xtal_clk_in = xtal_clk_i;
- assign xtal_clk_o = xtal_clk_out;
- wire nrst_in = nrst_i;
-
- wire [15:0] p0_in; // level-shifted input from pad
- wire [15:0] p0_out; // output port drive
- wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
- wire [15:0] p0_out_nen; // active low output drive enable (pad tech dependent)
-
- wire [15:0] p1_in; // level-shifted input from pad
- wire [15:0] p1_out; // output port drive
- wire [15:0] p1_out_en; // active high output drive enable (pad tech dependent)
- wire [15:0] p1_out_nen; // active low output drive enable (pad tech dependent)
- wire [15:0] p1_in_mux; // level-shifted input from pad
- wire [15:0] p1_out_mux; // output port drive
- wire [15:0] p1_out_en_mux; // active high output drive enable (pad tech dependent)
- wire [15:0] p1_out_nen_mux; // active low output drive enable (pad tech dependent)
-
- wire swdio_in;
- wire swdio_out;
- wire swdio_out_en;
- wire swdio_out_nen;
- wire swdclk_in;
-
- wire ft_clk_o;
- wire ft_ssn_o;
- wire ft_miso_i;
- wire ft_miosio_o;
- wire ft_miosio_e;
- wire ft_miosio_z;
- wire ft_miosio_i;
-
- // --------------------------------------------------------------------------------
- // Port-0 IO pad driver mapping
- // --------------------------------------------------------------------------------
-
- assign p0_in = p0_i; // level-shifted input from pad
- assign p0_o = p0_out; // output port drive
- assign p0_e = p0_out_en; // active high output drive enable (pad tech dependent)
- assign p0_z = p0_out_nen; // active low output drive enable (pad tech dependent)
-
-
- // --------------------------------------------------------------------------------
- // Port-1 IO pad driver mapping
- // --------------------------------------------------------------------------------
-
- assign ft_miso_i = p1_i[0]; // FT_MISO INPUT pad configuration
- assign p1_in_mux[0] = p1_i[0];
- assign p1_o[0] = 1'b0;
- assign p1_e[0] = 1'b0;
- assign p1_z[0] = 1'b1;
-
- assign p1_in_mux[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
- assign p1_o[1] = ft_clk_o;
- assign p1_e[1] = 1'b1;
- assign p1_z[1] = 1'b0;
-
- assign ft_miosio_i = p1_i[2]; // FT_MIOSIO INOUT pad configuration
- assign p1_in_mux[2] = p1_i[2];
- assign p1_o[2] = ft_miosio_o;
- assign p1_e[2] = ft_miosio_e;
- assign p1_z[2] = ft_miosio_z;
-
- assign p1_in_mux[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
- assign p1_o[3] = ft_ssn_o;
- assign p1_e[3] = 1'b1;
- assign p1_z[3] = 1'b0;
-
- assign p1_in_mux[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
- assign p1_o[15:4] = p1_out_mux[15:4];
- assign p1_e[15:4] = p1_out_en_mux[15:4];
- assign p1_z[15:4] = p1_out_nen_mux[15:4];
-
-
- wire tiehi = 1'b1;
- wire tielo = 1'b0;
-
- //----------------------------------------
- // SoC Clock and Reset Management
- //----------------------------------------
-
- wire PORESETn;// Power on reset
- wire HRESETn; // AHB reset
- wire PRESETn; // APB and peripheral reset
- wire DBGRESETn; // Debug system reset
- wire FCLK; // Free running system clock
- wire HCLK; // System clock from PMU
- wire DCLK;
- wire SCLK;
- wire PCLK; // Peripheral clock
- wire PCLKG; // Gated PCLK for APB
- wire PCLKEN; // Clock divider for AHB to APB bridge
- wire APBACTIVE;
-
- // event signals
- wire TXEV;
- wire RXEV;
- wire nTRST; // JTAG - Test reset (active low)
- wire SWDI; // JTAG/SWD - TMS / SWD data input
- wire SWCLK; // JTAG/SWD - TCK / SWCLK
- wire SWDO; // SWD - SWD data output
- wire SWDOEN; // SWD - SWD data output enable
- wire SYSRESETREQ; // processor system reset request
- wire WDOGRESETREQ; // watchdog system reset request
- wire HRESETREQ; // Combined system reset request
- wire NANOSOC_SYSRESETREQ; // Combined system reset request
- wire clk_ctrl_sys_reset_req;
- wire PMUHRESETREQ;
- wire PMUDBGRESETREQ;
- wire LOCKUP;
- wire LOCKUPRESET;
- wire SLEEPING;
- wire GATEHCLK; // Processor status - safe to gate HCLK
- wire WAKEUP; // Wake up request from WIC
- wire WICENREQ; // WIC enable request from PMU
- wire WICENACK; // WIC enable ack to PMU
- wire PMUENABLE;
- wire CDBGPWRUPREQ; // Debug Power Up request to PMU
- wire CDBGPWRUPACK; // Debug Power Up ACK from PMU
- wire SLEEPHOLDREQn; // Sleep extension request from PMU
- wire SLEEPHOLDACKn; // Sleep extension request to PMU
- wire SYSPWRDOWNACK;
- wire DBGPWRDOWNACK;
- wire SYSPWRDOWN;
- wire DBGPWRDOWN;
- wire SYSISOLATEn;
- wire SYSRETAINn;
- wire DBGISOLATEn;
- wire SLEEPDEEP;
- wire ADPRESETREQ;
- // Scan test dummy signals; not connected until scan insertion
- wire TESTMODE; // Test mode enable signal (override synchronizers etc)
- wire SCANENABLE; // Scan enable signal
- wire SCANINHCLK; // HCLK scan input
- wire SCANOUTHCLK; // Scan Chain wire
-
-// not required for FPGA
- assign TESTMODE = 1'b0;
- assign SCANENABLE = 1'b0;
- assign SCANINHCLK = 1'b0;
- assign SCANOUTHCLK = 1'b0;
-
-// Technology-specific PLL/Frequecy synthesizer would generate
-// CLK, FCLK (Free running system clock) from xtal_clk_in
-
- assign pll_clk = xtal_clk_in; // default to no PLL
- assign CLK = (TESTMODE) ? xtal_clk_in : pll_clk;
- assign HCLK = FCLK;
-
-
-//? assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
-
- // System Reset request can be from processor or watchdog
- // or when lockup happens and the control flag is set.
- assign NANOSOC_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
- ADPRESETREQ |
- (LOCKUP & LOCKUPRESET);
- assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
-
- // Clock controller to generate reset and clock signals
- nanosoc_mcu_clkctrl #(
- .CLKGATE_PRESENT (CLKGATE_PRESENT)
- ) u_nanosoc_mcu_clkctrl (
- // inputs
- .XTAL1 (CLK),
- .NRST (nrst_in),
-
- .APBACTIVE (APBACTIVE),
- .SLEEPING (SLEEPING),
- .SLEEPDEEP (SLEEPDEEP),
- .LOCKUP (LOCKUP),
- .LOCKUPRESET (LOCKUPRESET),
- .SYSRESETREQ (clk_ctrl_sys_reset_req),
- .DBGRESETREQ (PMUDBGRESETREQ),
- .CGBYPASS (TESTMODE),
- .RSTBYPASS (TESTMODE),
-
- // outputs
- .XTAL2 (xtal_clk_out),
- .FCLK (FCLK),
- .PCLK (PCLK),
- .PCLKG (PCLKG),
- .PCLKEN (PCLKEN),
-//?`ifdef CORTEX_M0DESIGNSTART
-//? .PORESETn (PORESETn), // for cm0 designstart
-//? .HRESETn (HRESETn), // for cm0 designstart
-//?`endif
- .PRESETn (PRESETn)
- );
-
- wire gated_hclk;
- wire gated_dclk;
- wire gated_sclk;
-
- cortexm0_rst_ctl u_rst_ctl (
- // Inputs
- .GLOBALRESETn (nrst_in),
- .FCLK (FCLK),
- .HCLK (gated_hclk),
- .DCLK (gated_dclk),
- .SYSRESETREQ (NANOSOC_SYSRESETREQ),
- .PMUHRESETREQ (PMUHRESETREQ),
- .PMUDBGRESETREQ (PMUDBGRESETREQ),
- .RSTBYPASS (TESTMODE),
- .SE (SCANENABLE),
-
- // Outputs
- .PORESETn (PORESETn),
- .HRESETn (HRESETn),
- .DBGRESETn (DBGRESETn),
- .HRESETREQ (HRESETREQ)
- );
-
-
- // Cortex-M0 Power management unit
- cortexm0_pmu u_cortexm0_pmu ( // Inputs
- .FCLK (FCLK),
- .PORESETn (PORESETn),
- .HRESETREQ (NANOSOC_SYSRESETREQ), // from processor / watchdog
- .PMUENABLE (PMUENABLE), // from System Controller
- .WICENACK (WICENACK), // from WIC in integration
-
- .WAKEUP (WAKEUP), // from WIC in integration
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
-
- .SLEEPDEEP (SLEEPDEEP),
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .GATEHCLK (GATEHCLK),
- .SYSPWRDOWNACK (SYSPWRDOWNACK),
- .DBGPWRDOWNACK (DBGPWRDOWNACK),
- .CGBYPASS (TESTMODE),
-
- // Outputs
- .HCLK (gated_hclk),
- .DCLK (gated_dclk),
- .SCLK (gated_sclk),
- .WICENREQ (WICENREQ),
- .CDBGPWRUPACK (CDBGPWRUPACK),
- .SYSISOLATEn (SYSISOLATEn),
- .SYSRETAINn (SYSRETAINn),
- .SYSPWRDOWN (SYSPWRDOWN),
- .DBGISOLATEn (DBGISOLATEn),
- .DBGPWRDOWN (DBGPWRDOWN),
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .PMUDBGRESETREQ (PMUDBGRESETREQ),
- .PMUHRESETREQ (PMUHRESETREQ)
- );
-
- // Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
- assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
- assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
- assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;
-
-
- // In this example system, power control takes place immediately.
- // In a real circuit you might need to add delays in the next two
- // signal assignments for correct operation.
- assign SYSPWRDOWNACK = SYSPWRDOWN;
- assign DBGPWRDOWNACK = DBGPWRDOWN;
-
- wire exp_penable;
- wire exp_pwrite;
- wire [11:0] exp_paddr;
- wire [31:0] exp_pwdata;
- wire exp12_psel;
- wire exp12_pready;
- wire exp12_pslverr;
- wire [31:0] exp12_prdata;
- wire exp13_psel;
- wire exp13_pready;
- wire exp13_pslverr;
- wire [31:0] exp13_prdata;
- wire exp14_psel;
- wire exp14_pready;
- wire exp14_pslverr;
- wire [31:0] exp14_prdata;
- wire exp15_psel;
- wire exp15_pready;
- wire exp15_pslverr;
- wire [31:0] exp15_prdata;
-
-
- // internal peripheral signals
- wire uart0_rxd;
- wire uart0_txd;
- wire uart0_txen;
- wire uart1_rxd;
- wire uart1_txd;
- wire uart1_txen;
- wire uart2_rxd;
- wire uart2_txd;
- wire uart2_txen;
- wire timer0_extin;
- wire timer1_extin;
-
- wire [15:0] p0_altfunc;
-
- wire [15:0] p1_altfunc;
-
- wire exp_irq0;
- wire exp_irq1;
- wire exp_irq2;
- wire exp_irq3;
- wire exp_irqB;
- wire exp_irqC;
- wire exp_irqD;
-
-
-//----------------------------------------
-// ADP ASCII DEBUG PROTOCOL controller
-// AHB MANAGER 0
-//----------------------------------------
-
- // -------------------------------
- // ADP engine stream and control interfaces
- // -------------------------------
-
- wire comio_tx_ready;
- wire [7:0] comio_tx_data8;
- wire comio_tx_valid;
-
- wire comio_rx_ready;
- wire [7:0] comio_rx_data8;
- wire comio_rx_valid;
-
- wire stdio_tx_ready;
- wire [7:0] stdio_tx_data8;
- wire stdio_tx_valid;
-
- wire stdio_rx_ready;
- wire [7:0] stdio_rx_data8;
- wire stdio_rx_valid;
-
- wire [7:0] adp_gpo8;
- wire [7:0] adp_gpi8;
-
- assign adp_gpi8 = adp_gpo8;
- assign ADPRESETREQ = adp_gpo8[0];
-
- // ADP debug controller present
- nanosoc_adp_control_v1_0 u_adp_control (
- // Clock and Reset
- .ahb_hclk (HCLK),
- .ahb_hresetn (HRESETn),
- // DMA Control
- .com_rx_tready (comio_rx_ready),
- .com_rx_tdata (comio_rx_data8),
- .com_rx_tvalid (comio_rx_valid),
- .com_tx_tready (comio_tx_ready),
- .com_tx_tdata (comio_tx_data8),
- .com_tx_tvalid (comio_tx_valid),
- .stdio_rx_tready (stdio_rx_ready),
- .stdio_rx_tdata (stdio_rx_data8),
- .stdio_rx_tvalid (stdio_rx_valid),
- .stdio_tx_tready (stdio_tx_ready),
- .stdio_tx_tdata (stdio_tx_data8),
- .stdio_tx_tvalid (stdio_tx_valid),
- .gpo8 (adp_gpo8),
- .gpi8 (adp_gpi8),
-
- // AHB-Lite Master Interface
- .ahb_hready (HREADY_adp),
- .ahb_hresp (HRESP_adp),
- .ahb_hrdata (HRDATA_adp),
- .ahb_htrans (HTRANS_adp),
- .ahb_hwrite (HWRITE_adp),
- .ahb_haddr (HADDR_adp),
- .ahb_hsize (HSIZE_adp),
- .ahb_hburst (HBURST_adp),
- .ahb_hmastlock (HMASTLOCK_adp),
- .ahb_hprot (HPROT_adp),
- .ahb_hwdata (HWDATA_adp)
- );
- assign HAUSER_adp [1:0] = 2'b00; // Address USER signals
- assign HWUSER_adp [1:0] = 2'b00; // Write-data USER signals
-
- nanosoc_apb_usrt u_apb_usrt_com (
- .PCLK (PCLK), // Peripheral clock
- .PCLKG (PCLKG), // Gated PCLK for bus
- .PRESETn (PRESETn), // Reset
-
- .PSEL (exp14_psel), // APB interface inputs
- .PADDR (exp_paddr[11:2]),
- .PENABLE (exp_penable),
- .PWRITE (exp_pwrite),
- .PWDATA (exp_pwdata),
-
- .PRDATA (exp14_prdata), // APB interface outputs
- .PREADY (exp14_pready),
- .PSLVERR (exp14_pslverr),
-
- .ECOREVNUM (4'h0),// Engineering-change-order revision bits
-
- .TX_VALID_o (stdio_rx_valid),
- .TX_DATA8_o (stdio_rx_data8),
- .TX_READY_i (stdio_rx_ready),
-
- .RX_VALID_i (stdio_tx_valid),
- .RX_DATA8_i (stdio_tx_data8),
- .RX_READY_o (stdio_tx_ready),
-
- .TXINT ( ), // Transmit Interrupt
- .RXINT ( ), // Receive Interrupt
- .TXOVRINT ( ), // Transmit Overrun Interrupt
- .RXOVRINT ( ), // Receive Overrun Interrupt
- .UARTINT ( ) // Combined Interrupt
- );
-
- wire [7:0] ft_clkdiv = 8'd03;
-
- nanosoc_ft1248_stream_io_v1_0 #(
- .FT1248_WIDTH (1),
- .FT1248_CLKON (0)
- ) u_ftdio_com (
- .clk (HCLK),
- .resetn (HRESETn),
- .ft_clkdiv (ft_clkdiv ),
- .ft_clk_o (ft_clk_o ),
- .ft_ssn_o (ft_ssn_o ),
- .ft_miso_i (ft_miso_i ),
- .ft_miosio_o (ft_miosio_o ),
- .ft_miosio_e (ft_miosio_e ),
- .ft_miosio_z (ft_miosio_z ),
- .ft_miosio_i (ft_miosio_i ),
- .rxd_tready (comio_tx_ready),
- .rxd_tdata (comio_tx_data8),
- .rxd_tvalid (comio_tx_valid),
- .rxd_tlast (1'b0),
- .txd_tready (comio_rx_ready),
- .txd_tdata (comio_rx_data8),
- .txd_tvalid (comio_rx_valid),
- .txd_tlast ( )
- );
-
-
-//----------------------------------------
-// DIRECT MEMORY ACCESS controller
-// AHB MANAGER 1
-//----------------------------------------
-
- // DMA interface not used in this example system
- wire [DMA_CHANNEL_NUM-1:0] dma230_req; // tie off signal.
- wire [DMA_CHANNEL_NUM-1:0] dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
-
- assign dma230_req[0] = exp_drq_ip;
- assign dma230_req[1] = exp_drq_op;
-
-
- // DMA done per channel
- wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
- wire dmac_done;
- wire dmac_err;
-
- ///generate if (INCLUDE_DMA != 0) begin : gen_dma
- // DMA controller present
- pl230_udma u_pl230_udma (
- // Clock and Reset
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // DMA Control
- .dma_req (dma230_req),
- .dma_sreq (dma230_req),
- .dma_waitonreq (dma230_tie0),
- .dma_stall (1'b0),
- .dma_active (),
- .dma_done (dma230_done_ch),
- .dma_err (dmac_err),
-
- // AHB-Lite Master Interface
- .hready (HREADY_dma),
- .hresp (HRESP_dma),
- .hrdata (HRDATA_dma),
- .htrans (HTRANS_dma),
- .hwrite (HWRITE_dma),
- .haddr (HADDR_dma),
- .hsize (HSIZE_dma),
- .hburst (HBURST_dma),
- .hmastlock (HMASTLOCK_dma),
- .hprot (HPROT_dma),
- .hwdata (HWDATA_dma),
-
- // APB Slave Interface
- .pclken (PCLKEN),
- .psel (exp15_psel),
- .pen (exp_penable),
- .pwrite (exp_pwrite),
- .paddr (exp_paddr[11:0]),
- .pwdata (exp_pwdata[31:0]),
- .prdata (exp15_prdata)
- );
-
- assign exp15_pready = 1'b1;
- assign exp15_pslverr = 1'b0;
- assign dmac_done = |dma230_done_ch; // OR all the DMA done together
-
-/* end else begin : gen_no_pl230_udma
- // DMA controller not present
- assign HADDR_dma [31:0] = 32'ha2a2a2a2; // Address bus
- assign HTRANS_dma [1:0] = 2'b00; // Transfer type
- assign HWRITE_dma = 1'b0; // Transfer direction
- assign HSIZE_dma [2:0] = 3'b010; // Transfer size
- assign HBURST_dma [2:0] = 3'b001; // Burst type
- assign HPROT_dma [3:0] = 4'b0010; // Protection control
- assign HWDATA_dma [31:0] = 32'hd2d2d2d2; // Write data
- assign HMASTLOCK_dma = 1'b0; // Locked Sequence
- assign HAUSER_dma [1:0] = 2'b00; // Address USER signals
- assign HWUSER_dma [1:0] = 2'b00; // Write-data USER signals
-
- assign dmac_done = 1'b0;
- assign dmac_err = 1'b0;
- assign exp15_pready = 1'b1;
- assign exp15_pslverr = 1'b0;
- assign exp15_prdata = 32'h00000000;
- assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
-
- end endgenerate
-*/
-
-
-
-//----------------------------------------
-// CORTEX-M0 CPU controller
-// AHB MANAGER 3
-//----------------------------------------
-
- wire SYS_NMI; // Watchdog nin-maskable interrupt
- wire [31:0] SYS_APB_IRQ; // APB subsystem IRQs
- wire [15:0] SYS_GPIO0_IRQ; // GPIO-0 IRQs
- wire [15:0] SYS_GPIO1_IRQ; // GPIO-1 IRQs
-
- wire gpio0_combintr;
- wire gpio1_combintr;
- assign gpio0_combintr = |SYS_GPIO0_IRQ[15:0];
- assign gpio1_combintr = |SYS_GPIO1_IRQ[15:0];
-
- wire intnmi_cm0;
- wire [31:0] intisr_cm0;
-
-// match interrupts to CMSDK for validation code reuse
-
- assign intnmi_cm0 = SYS_NMI;
- //assign intisr_cm0[ 5: 0] = SYS_APB_IRQ[ 5: 0];
- assign intisr_cm0[ 0] = exp_irq0;
- assign intisr_cm0[ 1] = exp_irq1;
- assign intisr_cm0[ 2] = exp_irq2;
- assign intisr_cm0[ 3] = exp_irq3;
- assign intisr_cm0[ 5: 4] = SYS_APB_IRQ[ 5: 4];
- assign intisr_cm0[ 6] = SYS_APB_IRQ[ 6] | gpio0_combintr;
- assign intisr_cm0[ 7] = SYS_APB_IRQ[ 7] | gpio1_combintr;
- assign intisr_cm0[14: 8] = SYS_APB_IRQ[14: 8];
- assign intisr_cm0[15] = SYS_APB_IRQ[15] | dmac_done | dmac_err;
- assign intisr_cm0[31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
-
- assign HAUSER_cpu [1:0] = 2'b00; // Address USER signals
- assign HWUSER_cpu [1:0] = 2'b00; // Write-data USER signals
-
-
- // Cortex-M0 integration level
- nanosoc_cpu u_nanosoc_cpu (
- .HCLK (gated_hclk), //HCLK),
- .FCLK (FCLK),
- .DCLK (DCLK),
- .SCLK (SCLK),
- .HRESETn (HRESETn),
- .PORESETn (PORESETn),
- .DBGRESETn (DBGRESETn),
- .RSTBYPASS (TESTMODE),
- .DFTSE (SCANENABLE),
- // AHB port
- .HADDR (HADDR_cpu),
- .HTRANS (HTRANS_cpu),
- .HWRITE (HWRITE_cpu),
- .HSIZE (HSIZE_cpu),
- .HBURST (HBURST_cpu),
- .HPROT (HPROT_cpu),
- .HWDATA (HWDATA_cpu),
- .HMASTLOCK (HMASTLOCK_cpu),
- .HREADY (HREADY_cpu),
-// .HAUSER (HAUSER_cpu),
-// .HWUSER (HWUSER_cpu),
- .HRDATA (HRDATA_cpu),
- .HRESP (HRESP_cpu),
-// .HRUSER (HRUSER_cpu),
- // sideband signals
- .NMI (intnmi_cm0), // Non-maskable interrupt input
- .IRQ (intisr_cm0[31:0]), // Interrupt request inputs
- .TXEV (TXEV), // Event output (SEV executed)
- .RXEV (RXEV), // Event input
- // MISCELLANEOUS ---------------------
- .SLEEPING (SLEEPING),
- .SLEEPDEEP (SLEEPDEEP),
- .WAKEUP (WAKEUP ), // Wake up request from WIC
- .WICENREQ (WICENREQ ), // WIC enable request from PMU
- .WICENACK (WICENACK ), // WIC enable ack to PMU
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .CDBGPWRUPACK (CDBGPWRUPACK),
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
- .LOCKUP (LOCKUP), // Core is locked-up
- .GATEHCLK (GATEHCLK),
- .SYSRESETREQ (SYSRESETREQ), // System reset request
- .WDOGRESETREQ (WDOGRESETREQ), // Watchdog HW reset request
- .ADPRESETREQ (ADPRESETREQ), // ADP debugger reset request
-
- // Debug - JTAG or Serial wire
- // inputs
- .SWDI (SWDI),
- .SWCLK (SWCLK),
- // outputs
- .SWDO (SWDO),
- .SWDOEN (SWDOEN)
- );
-
- assign RXEV = dmac_done; // Generate event when a DMA operation completed.
-
-
-//------------------------------------
-// internal wires
-
- assign p0_out_nen = ~p0_out_en; //active low pad drive option
- assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
-
- localparam BASEADDR_GPIO0 = 32'h4001_0000;
- localparam BASEADDR_GPIO1 = 32'h4001_1000;
- localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
-
- nanosoc_sysio u_nanosoc_sysio (
- .FCLK (FCLK ), // free-running clock
- .PORESETn (PORESETn ), // Power-On-Reset (active-low)
- .TESTMODE (TESTMODE ), // Test-mode override for testability
- .HCLK (HCLK ), // AHB interconnect clock
- .HRESETn (HRESETn ), // AHB interconnect reset (active-low)
- // Common AHB signals
- .HSEL (HSEL_sysio ),
- .HADDR (HADDR_sysio ),
- .HBURST (HBURST_sysio ),
- .HMASTLOCK (HMASTLOCK_sysio),
- .HPROT (HPROT_sysio ),
- .HSIZE (HSIZE_sysio ),
- .HTRANS (HTRANS_sysio ),
- .HWDATA (HWDATA_sysio ),
- .HWRITE (HWRITE_sysio ),
- .HREADY (HREADYMUX_sysio),
- .HRDATA (HRDATA_sysio ),
- .HRESP (HRESP_sysio ),
- .HREADYOUT (HREADYOUT_sysio),
- // APB clocking
- .PCLK (PCLK ),
- .PCLKG (PCLKG ),
- .PRESETn (PRESETn ),
- .PCLKEN (PCLKEN ),
- // APB expansion select outputs
- .exp12_psel (exp12_psel ),
- .exp13_psel (exp13_psel ),
- .exp14_psel (exp14_psel ),
- .exp15_psel (exp15_psel ),
- .exp_pwdata (exp_pwdata ),
- .exp_paddr (exp_paddr ),
- .exp_pwrite (exp_pwrite ),
- .exp_penable (exp_penable ),
- // APB expansion interface inputs
- .exp12_prdata (exp12_prdata ),
- .exp12_pready (exp12_pready ),
- .exp12_pslverr (exp12_pslverr),
- .exp13_prdata (exp13_prdata ),
- .exp13_pready (exp13_pready ),
- .exp13_pslverr (exp13_pslverr),
- .exp14_prdata (exp14_prdata ),
- .exp14_pready (exp14_pready ),
- .exp14_pslverr (exp14_pslverr),
- .exp15_prdata (exp15_prdata ),
- .exp15_pready (exp15_pready ),
- .exp15_pslverr (exp15_pslverr),
- // CPU sideband signalling
- .SYS_NMI (SYS_NMI ),
- .SYS_APB_IRQ (SYS_APB_IRQ ),
- // CPU specific power/reset control
- .REMAP_CTRL (ROM_MAP ),
- .APBACTIVE (APBACTIVE ),
- .SYSRESETREQ (SYSRESETREQ ),
- .WDOGRESETREQ (WDOGRESETREQ ),
- .LOCKUP (LOCKUP ),
- .LOCKUPRESET (LOCKUPRESET ),
- .PMUENABLE (PMUENABLE ),
- // chip IO
- .SYS_GPIO0_IRQ (SYS_GPIO0_IRQ ),
- .SYS_GPIO1_IRQ (SYS_GPIO1_IRQ ),
- // IO signalling
- .uart0_rxd (uart1_txd), //(uart0_rxd ), // crossover
- .uart0_txd (uart0_txd ),
- .uart0_txen (uart0_txen ),
- .uart1_rxd (uart0_txd), //uart1_rxd ), // crossover
- .uart1_txd (uart1_txd ),
- .uart1_txen (uart1_txen ),
- .uart2_rxd (uart2_rxd ),
- .uart2_txd (uart2_txd ),
- .uart2_txen (uart2_txen ),
- .timer0_extin (timer0_extin ),
- .timer1_extin (timer1_extin ),
- // GPIO port signalling
- .p0_in (p0_in ),
- .p0_out (p0_out ),
- .p0_outen (p0_out_en ),
- .p0_altfunc (p0_altfunc ),
-
- .p1_in (p1_in ),
- .p1_out (p1_out ),
- .p1_outen (p1_out_en ),
- .p1_altfunc (p1_altfunc )
- );
-
- assign REMAP[3] = 1'b0;
- assign REMAP[2] = 1'b0;
- assign REMAP[1] = 1'b0;
- assign REMAP[0] =!ROM_MAP;
-
- assign exp12_pready = 1'b1;
- assign exp13_pready = 1'b1;
- assign exp12_pslverr = 1'b0;
- assign exp13_pslverr = 1'b0;
- assign exp12_prdata = 32'h0;
- assign exp13_prdata = 32'h0;
-
-
- // Serial wire debug is used. nTRST, TDI and TDO are not needed
-
-
-//----------------------------------------
-// I/O port pin muxing and tristate
-//----------------------------------------
-
- assign SWCLK = swdclk_i;
- assign SWDI = swdio_i;
- assign swdio_o = SWDO;
- assign swdio_e = SWDOEN;
- assign swdio_z = !SWDOEN;
-
- nanosoc_mcu_pin_mux u_pin_mux (
- // UART
- .uart0_rxd (uart0_rxd),
- .uart0_txd (uart0_txd),
- .uart0_txen (uart0_txen),
- .uart1_rxd (uart1_rxd),
- .uart1_txd (uart1_txd),
- .uart1_txen (uart1_txen),
- .uart2_rxd (uart2_rxd),
- .uart2_txd (uart2_txd),
- .uart2_txen (uart2_txen),
-
- // Timer
- .timer0_extin (timer0_extin),
- .timer1_extin (timer1_extin),
-
-
- // IO Ports
- .p0_in ( ), // was (p0_in) now from pad inputs),
- .p0_out (p0_out),
- .p0_outen (p0_out_en),
- .p0_altfunc (p0_altfunc),
-
- .p1_in ( ), // was(p1_in) now from pad inputs),
- .p1_out (p1_out),
- .p1_outen (p1_out_en),
- .p1_altfunc (p1_altfunc),
-
- // Debug
- .i_trst_n ( ),
- .i_swditms ( ), //i_swditms),
- .i_swclktck ( ), //i_swclktck),
- .i_tdi ( ),
- .i_tdo ( ),
- .i_tdoen_n ( ),
- .i_swdo ( ),
- .i_swdoen ( ),
-
- // IO pads
- .p1_out_mux (p1_out_mux),
- .p1_out_en_mux (p1_out_en_mux),
- .P0 ( ), //P0),
- .P1 ( ), //P1),
-
- .nTRST (nTRST), // Not needed if serial-wire debug is used
- .TDI (1'b0), // Not needed if serial-wire debug is used
- .SWDIOTMS ( ), //SWDIOTMS),
- .SWCLKTCK ( ), //SWCLKTCK),
- .TDO ( ) // Not needed if serial-wire debug is used
-
- );
-
-endmodule
-
-
-
diff --git a/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v b/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
index 56dfdfc..a2b921e 100644
--- a/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
+++ b/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
@@ -36,6 +36,8 @@ module nanosoc_region_dmem_0 #(
// SRAM Instantiation
sl_ahb_sram #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (DMEM_RAM_ADDR_W)
) u_dmem_0 (
// AHB Inputs
@@ -47,7 +49,7 @@ module nanosoc_region_dmem_0 #(
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
- .HREADY (HREADYMUX),
+ .HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
diff --git a/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v b/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
index c93b82f..78b3f18 100644
--- a/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
+++ b/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
@@ -37,6 +37,8 @@ module nanosoc_region_expram_h #(
// AHB to SRAM bridge
sl_ahb_sram #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W)
) u_expram_h (
// AHB Inputs
@@ -48,7 +50,7 @@ module nanosoc_region_expram_h #(
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
- .HREADY (HREADYMUX),
+ .HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
diff --git a/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v b/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
index 5e43f89..b3db369 100644
--- a/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
+++ b/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
@@ -37,6 +37,8 @@ module nanosoc_region_expram_l #(
// SRAM Instantiation
sl_ahb_sram #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W)
) u_expram_l (
// AHB Inputs
@@ -48,7 +50,7 @@ module nanosoc_region_expram_l #(
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
- .HREADY (HREADYMUX),
+ .HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
diff --git a/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v b/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
index 38f887e..fd17263 100644
--- a/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+++ b/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
@@ -38,6 +38,8 @@ module nanosoc_region_imem_0 #(
// SRAM Instantiation
sl_ahb_sram #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (IMEM_RAM_ADDR_W),
.FILENAME (IMEM_RAM_FPGA_IMG)
) u_imem_0 (
@@ -50,7 +52,7 @@ module nanosoc_region_imem_0 #(
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
- .HREADY (HREADYMUX),
+ .HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
diff --git a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
index e41f96a..b4e4702 100644
--- a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+++ b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
@@ -76,6 +76,7 @@ module nanosoc_ss_cpu #(
input wire CPU_0_HRESP, // Transfer response
// Bootrom 0 AHB Lite port
+ input wire BOOTROM_0_HSEL, // Select
input wire [31:0] BOOTROM_0_HADDR, // Address bus
input wire [1:0] BOOTROM_0_HTRANS, // Transfer type
input wire BOOTROM_0_HWRITE, // Transfer direction
@@ -87,8 +88,10 @@ module nanosoc_ss_cpu #(
output wire [31:0] BOOTROM_0_HRDATA, // Read data bus
output wire BOOTROM_0_HREADY, // HREADY feedback
output wire BOOTROM_0_HRESP, // Transfer response
+ output wire BOOTROM_0_HREADYOUT, // AHB ready out
// IMEM 0 AHB Lite port
+ input wire IMEM_0_HSEL, // Select
input wire [31:0] IMEM_0_HADDR, // Address bus
input wire [1:0] IMEM_0_HTRANS, // Transfer type
input wire IMEM_0_HWRITE, // Transfer direction
@@ -100,8 +103,10 @@ module nanosoc_ss_cpu #(
output wire [31:0] IMEM_0_HRDATA, // Read data bus
output wire IMEM_0_HREADY, // HREADY feedback
output wire IMEM_0_HRESP, // Transfer response
+ output wire IMEM_0_HREADYOUT, // AHB ready out
// DMEM 0 AHB Lite port
+ input wire DMEM_0_HSEL, // Select
input wire [31:0] DMEM_0_HADDR, // Address bus
input wire [1:0] DMEM_0_HTRANS, // Transfer type
input wire DMEM_0_HWRITE, // Transfer direction
@@ -113,6 +118,7 @@ module nanosoc_ss_cpu #(
output wire [31:0] DMEM_0_HRDATA, // Read data bus
output wire DMEM_0_HREADY, // HREADY feedback
output wire DMEM_0_HRESP, // Transfer response
+ output wire DMEM_0_HREADYOUT, // AHB ready out
// CPU Sideband signalling
input wire CPU_0_NMI, // Non-Maskable Interrupt request
@@ -135,19 +141,19 @@ module nanosoc_ss_cpu #(
// CPU Core 0 Instantiation
// -------------------------------
slcorem0 #(
- .ACG (CLKGATE_PRESENT), // Architectural clock gating
- .BE (BE), // Big-endian
- .BKPT (BKPT), // Number of breakpoint comparators
- .DBG (DBG), // Debug configuration
- .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
- .NUMIRQ (NUMIRQ), // Number of Interrupts
- .RAR (RESET_ALL_REGS), // Reset All Registers
- .SMUL (SMUL), // Multiplier configuration
- .SYST (SYST), // SysTick
- .WIC (WIC), // Wake-up interrupt controller support
- .WICLINES (WICLINES), // Supported WIC lines
- .WPT (WPT), // Number of DWT comparators
- .ROMTABLE_BASE (ROMTABLE_BASE)
+ .CLKGATE_PRESENT (CLKGATE_PRESENT), // Architectural clock gating
+ .BE (BE), // Big-endian
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .INCLUDE_JTAG (INCLUDE_JTAG), // Debug port interface: JTAGnSW
+ .NUMIRQ (NUMIRQ), // Number of Interrupts
+ .RESET_ALL_REGS (RESET_ALL_REGS), // Reset All Registers
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT), // Number of DWT comparators
+ .ROMTABLE_BASE (ROMTABLE_BASE)
) u_cpu_0 (
// System Input Clocks and Resets
.SYS_FCLK(SYS_FCLK),
diff --git a/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v b/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
index 3257983..3ac14db 100644
--- a/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
+++ b/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
@@ -17,7 +17,8 @@ module nanosoc_ss_debug #(
// SoCDebug Parameters
parameter PROMPT_CHAR = "]",
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
- parameter integer FT1248_CLKON = 1 // FTDI clock always on - else quiet when no access
+ parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
+ parameter [7:0] FT1248_CLKDIV = 8'd03 // Clock Division Ratio
)(
// System Clocks and Resets
input wire SYS_HCLK,
@@ -57,7 +58,6 @@ module nanosoc_ss_debug #(
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
- input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
// GPIO interface
output wire [7:0] GPO8,
@@ -67,11 +67,12 @@ module nanosoc_ss_debug #(
socdebug_ahb #(
.PROMPT_CHAR(PROMPT_CHAR),
.FT1248_WIDTH(FT1248_WIDTH),
- .FT1248_CLKON(FT1248_CLKON)
- ) u_socdebbug (
+ .FT1248_CLKON(FT1248_CLKON),
+ .FT1248_CLKDIV(FT1248_CLKDIV)
+ ) u_socdebug (
// AHB-lite Master Interface - ADP
- .HCLK(DEBUG_SYS_HCLK),
- .HRESETn(DEBUG_SYS_HRESETn),
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
.HADDR32_o(DEBUG_HADDR),
.HBURST3_o(DEBUG_HBURST),
.HMASTLOCK_o(DEBUG_HMASTLOCK),
@@ -80,14 +81,14 @@ module nanosoc_ss_debug #(
.HTRANS2_o(DEBUG_HTRANS),
.HWDATA32_o(DEBUG_HWDATA),
.HWRITE_o(DEBUG_HWRITE),
- .HRDATA32_i(DEBUG_HRDATA32),
+ .HRDATA32_i(DEBUG_HRDATA),
.HREADY_i(DEBUG_HREADY),
.HRESP_i(DEBUG_HRESP),
// APB Slave Interface - USRT
- .PCLK(DEBUG_PCLK),
- .PCLKG(DEBUG_PCLKG),
- .PRESETn(DEBUG_PRESETn),
+ .PCLK(SYS_PCLK),
+ .PCLKG(SYS_PCLKG),
+ .PRESETn(SYS_PRESETn),
.PSEL_i(DEBUG_PSEL),
.PADDR_i(DEBUG_PADDR[11:2]),
.PENABLE_i(DEBUG_PENABLE),
@@ -105,11 +106,10 @@ module nanosoc_ss_debug #(
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
- .FT_CLKDIV(FT_CLKDIV),
// GPIO interface
- .GPO8_o(GPO8_o),
- .GPI8_i(GPI8_i)
+ .GPO8_o(GPO8),
+ .GPI8_i(GPI8)
);
endmodule
\ No newline at end of file
diff --git a/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v b/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
index 5c835ce..e2af9bf 100644
--- a/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+++ b/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
@@ -81,7 +81,7 @@ module nanosoc_ss_dma #(
sldmac230 #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W),
- .CFG_ADDR_W (CFG_ADDR_W),
+ .CFG_ADDR_W (DMAC_0_CFG_ADDR_W),
.CHANNEL_NUM (DMAC_0_CHANNEL_NUM)
) u_dmac_0 (
// AHB Clocks and Resets
@@ -120,20 +120,20 @@ module nanosoc_ss_dma #(
// DMA Controller 1 Instantiation - Not implemented
// -------------------------------
// AHB Tie-off signals
- assign DMAC_1_HADDR = 32'b0;
- assign DMAC_1_HTRANS = 2'b0;
- assign DMAC_1_HWRITE = 1'b0;
- assign DMAC_1_HSIZE = 3'b0;
- assign DMAC_1_HBURST = 3'b0;
- assign DMAC_1_HPROT = 4'0;
- assign DMAC_1_HWDATA = 32'b0;
+ assign DMAC_1_HADDR = 32'b0;
+ assign DMAC_1_HTRANS = 2'b0;
+ assign DMAC_1_HWRITE = 1'b0;
+ assign DMAC_1_HSIZE = 3'b0;
+ assign DMAC_1_HBURST = 3'b0;
+ assign DMAC_1_HPROT = 4'b0;
+ assign DMAC_1_HWDATA = 32'b0;
assign DMAC_1_HMASTLOCK = 1'b0;
// APB Tie-off signals
- assign DMAC_1_PRDATA = 32'b0;
+ assign DMAC_1_PRDATA = 32'b0;
// DMA Status Tie-off signals
- assign DMAC_1_DMA_DONE = 0;
- assign DMAC_1_DMA_ERR = 0;
+ assign DMAC_1_DMA_DONE = 0;
+ assign DMAC_1_DMA_ERR = 0;
endmodule
\ No newline at end of file
diff --git a/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v b/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
index 3f3cf17..cc200e3 100644
--- a/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
+++ b/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
@@ -41,32 +41,32 @@ module nanosoc_ss_expansion #(
output wire [31:0] EXP_HRDATA,
// SRAM Low Region AHB Port
- input wire EXPSRAM_L_HSEL,
- input wire [SYS_ADDR_W-1:0] EXPSRAM_L_HADDR,
- input wire [1:0] EXPSRAM_L_HTRANS,
- input wire [2:0] EXPSRAM_L_HSIZE,
- input wire [3:0] EXPSRAM_L_HPROT,
- input wire EXPSRAM_L_HWRITE,
- input wire EXPSRAM_L_HREADY,
- input wire [31:0] EXPSRAM_L_HWDATA,
+ input wire EXPRAM_L_HSEL,
+ input wire [SYS_ADDR_W-1:0] EXPRAM_L_HADDR,
+ input wire [1:0] EXPRAM_L_HTRANS,
+ input wire [2:0] EXPRAM_L_HSIZE,
+ input wire [3:0] EXPRAM_L_HPROT,
+ input wire EXPRAM_L_HWRITE,
+ input wire EXPRAM_L_HREADY,
+ input wire [31:0] EXPRAM_L_HWDATA,
- output wire EXPSRAM_L_HREADYOUT,
- output wire EXPSRAM_L_HRESP,
- output wire [31:0] EXPSRAM_L_HRDATA,
+ output wire EXPRAM_L_HREADYOUT,
+ output wire EXPRAM_L_HRESP,
+ output wire [31:0] EXPRAM_L_HRDATA,
// SRAM High Region AHB Port
- input wire EXPSRAM_H_HSEL,
- input wire [SYS_ADDR_W-1:0] EXPSRAM_H_HADDR,
- input wire [1:0] EXPSRAM_H_HTRANS,
- input wire [2:0] EXPSRAM_H_HSIZE,
- input wire [3:0] EXPSRAM_H_HPROT,
- input wire EXPSRAM_H_HWRITE,
- input wire EXPSRAM_H_HREADY,
- input wire [31:0] EXPSRAM_H_HWDATA,
+ input wire EXPRAM_H_HSEL,
+ input wire [SYS_ADDR_W-1:0] EXPRAM_H_HADDR,
+ input wire [1:0] EXPRAM_H_HTRANS,
+ input wire [2:0] EXPRAM_H_HSIZE,
+ input wire [3:0] EXPRAM_H_HPROT,
+ input wire EXPRAM_H_HWRITE,
+ input wire EXPRAM_H_HREADY,
+ input wire [31:0] EXPRAM_H_HWDATA,
- output wire EXPSRAM_H_HREADYOUT,
- output wire EXPSRAM_H_HRESP,
- output wire [31:0] EXPSRAM_H_HRDATA,
+ output wire EXPRAM_H_HREADYOUT,
+ output wire EXPRAM_H_HRESP,
+ output wire [31:0] EXPRAM_H_HRDATA,
// Interrupt and DMAC Connections
output wire [3:0] EXP_IRQ,
@@ -82,8 +82,8 @@ module nanosoc_ss_expansion #(
.SYS_DATA_W(SYS_DATA_W)
) u_region_exp (
// Clock and Reset
- .HCLK(HCLK),
- .HRESETn(HRESETn),
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
// AHB Subordinate Port
.HSEL(EXP_HSEL),
diff --git a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 5b8b683..24e823b 100644
--- a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -26,6 +26,7 @@ module nanosoc_ss_systemctrl #(
output wire SYS_XTALCLK_OUT, // Crystal Clock Output
// System Input Clocks and Resets
+ input wire SYS_SYSRESETn, // System Reset
input wire SYS_PORESETn, // Power-On-Reset reset (active-low)
input wire SYS_TESTMODE, // Reset bypass in scan test
input wire SYS_HCLK, // AHB clock
@@ -194,12 +195,12 @@ module nanosoc_ss_systemctrl #(
// IO Ports
.p0_in ( ), // was (p0_in) now from pad inputs),
.p0_out (P0_OUT),
- .p0_outen (P0_OUT_EN),
+ .p0_outen (P0_OUTEN),
.p0_altfunc (P0_ALTFUNC),
.p1_in ( ), // was(p1_in) now from pad inputs),
.p1_out (P1_OUT),
- .p1_outen (P1_OUT_EN),
+ .p1_outen (P1_OUTEN),
.p1_altfunc (P1_ALTFUNC),
// Debug
@@ -240,8 +241,8 @@ module nanosoc_ss_systemctrl #(
.TESTMODE(SYS_TESTMODE),
// AHB interface
- .HCLK(SYSIO_SYS_HCLK),
- .HRESETn(SYSIO_SYS_HRESETn),
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
.HSEL(SYSIO_HSEL),
.HADDR(SYSIO_HADDR),
.HBURST(SYSIO_HBURST),
diff --git a/system/nanosoc_system/verilog/nanosoc_system.v b/system/nanosoc_system/verilog/nanosoc_system.v
index d083b9f..24b2146 100644
--- a/system/nanosoc_system/verilog/nanosoc_system.v
+++ b/system/nanosoc_system/verilog/nanosoc_system.v
@@ -58,14 +58,16 @@ module nanosoc_system #(
// SoCDebug Parameters
parameter PROMPT_CHAR = "]",
- parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
- parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
+ parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
+ parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
+ parameter [7:0] FT1248_CLKDIV = 8'd03, // Clock Division Ratio
// Address of System ROM Table
parameter SYSTABLE_BASE = 32'hF000_0000 // Base Address of System ROM Table
) (
// Free-running and Crystal Clock Output
input wire SYS_CLK, // System Input Clock
+ input wire SYS_SYSRESETn, // System Reset
output wire SYS_XTALCLK_OUT, // Crystal Clock Output
// Scan Wiring
@@ -88,7 +90,6 @@ module nanosoc_system #(
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
- input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
// GPIO interface
output wire [7:0] GPO8,
@@ -103,7 +104,7 @@ module nanosoc_system #(
output wire [15:0] P1_OUT, // GPIO 1 outputs
output wire [15:0] P1_OUTEN, // GPIO 1 output enables
output wire [15:0] P1_ALTFUNC, // GPIO 1 alternate function (pin mux)
- output wire [15:0] P1_OUT_MUX, // GPIO 1 aOutput Port Drive
+ output wire [15:0] P1_OUT_MUX, // GPIO 1 Output Port Drive
output wire [15:0] P1_OUT_EN_MUX // Active High output drive enable (pad tech dependent)
);
//--------------------------
@@ -117,7 +118,6 @@ module nanosoc_system #(
//--------------------------
// System Input Clocks and Resets
wire SYS_FCLK; // Free running clock
- wire SYS_SYSRESETn; // System Reset
// System Reset Request Signals
wire SYS_SYSRESETREQ; // System Request from System Managers
@@ -137,14 +137,12 @@ module nanosoc_system #(
// Power Management Signals
wire SYS_PMUENABLE; // Power Management Enable
wire SYS_PMUDBGRESETREQ; // Power Management Debug Reset Req
-
- // Reset Request Wiring
- //--------------------------
-
- assign SYS_SYSRESETREQ = CPU_0_SYSRESETREQ
- | DEBUG_RESETREQ
- | SYS_WDOGRESETREQ
- | (SYS_LOCKUPRESET & CPU_0_LOCKUP);
+
+ // Sysio APB driving signals - To all APB Components
+ wire SYSIO_PENABLE;
+ wire SYSIO_PWRITE;
+ wire [APB_ADDR_W-1:0] SYSIO_PADDR;
+ wire [APB_DATA_W-1:0] SYSIO_PWDATA;
//--------------------------
// CPU Subsystem
@@ -167,6 +165,7 @@ module nanosoc_system #(
wire CPU_0_HRESP; // Transfer response
// Bootrom 0 Region Wiring - To Interconnect Subsystem
+ wire BOOTROM_0_HSEL; // Select
wire [31:0] BOOTROM_0_HADDR; // Address bus
wire [1:0] BOOTROM_0_HTRANS; // Transfer type
wire BOOTROM_0_HWRITE; // Transfer direction
@@ -180,6 +179,7 @@ module nanosoc_system #(
wire BOOTROM_0_HRESP; // Transfer response
// Instruction Memory 0 Region Wiring - To Interconnect Subsystem
+ wire IMEM_0_HSEL; // Select
wire [31:0] IMEM_0_HADDR; // Address bus
wire [1:0] IMEM_0_HTRANS; // Transfer type
wire IMEM_0_HWRITE; // Transfer direction
@@ -193,6 +193,7 @@ module nanosoc_system #(
wire IMEM_0_HRESP; // Transfer response
// Data Memory 0 Region Wiring - To Interconnect Subsystem
+ wire DMEM_0_HSEL; // Select
wire [31:0] DMEM_0_HADDR; // Address bus
wire [1:0] DMEM_0_HTRANS; // Transfer type
wire DMEM_0_HWRITE; // Transfer direction
@@ -216,23 +217,6 @@ module nanosoc_system #(
wire CPU_0_SLEEPING; // Processor status - sleeping
wire CPU_0_SLEEPDEEP; // Processor status - deep sleep
- // Interrupt Wiring
- //--------------------------
-
- assign CPU_0_IRQ [3:0] = EXP_IRQ [3:0];
- assign CPU_0_IRQ [ 5: 4] = SYS_APB_IRQ[ 5: 4];
- assign CPU_0_IRQ [ 6] = SYS_APB_IRQ[ 6] | |SYS_GPIO0_ANY_IRQ;
- assign CPU_0_IRQ [ 7] = SYS_APB_IRQ[ 7] | |SYS_GPIO1_ANY_IRQ;
- assign CPU_0_IRQ [14: 8] = SYS_APB_IRQ[14: 8];
- assign CPU_0_IRQ [15] = SYS_APB_IRQ[15] | DMAC_ANY_DONE | DMAC_ANY_ERROR;
- assign CPU_0_IRQ [31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
-
-
- // Sideband Wiring
- //--------------------------
-
- assign CPU_0_RXEV = DMAC_ANY_DONE;
-
// Instantiate Subsystem
//--------------------------
@@ -290,6 +274,7 @@ module nanosoc_system #(
.CPU_0_HRESP(CPU_0_HRESP),
// Bootrom 0 AHB Lite port
+ .BOOTROM_0_HSEL(BOOTROM_0_HSEL),
.BOOTROM_0_HADDR(BOOTROM_0_HADDR),
.BOOTROM_0_HTRANS(BOOTROM_0_HTRANS),
.BOOTROM_0_HWRITE(BOOTROM_0_HWRITE),
@@ -301,8 +286,10 @@ module nanosoc_system #(
.BOOTROM_0_HRDATA(BOOTROM_0_HRDATA),
.BOOTROM_0_HREADY(BOOTROM_0_HREADY),
.BOOTROM_0_HRESP(BOOTROM_0_HRESP),
+ .BOOTROM_0_HREADYOUT(BOOTROM_0_HREADYOUT),
// IMEM 0 AHB Lite port
+ .IMEM_0_HSEL(IMEM_0_HSEL),
.IMEM_0_HADDR(IMEM_0_HADDR),
.IMEM_0_HTRANS(IMEM_0_HTRANS),
.IMEM_0_HWRITE(IMEM_0_HWRITE),
@@ -314,8 +301,10 @@ module nanosoc_system #(
.IMEM_0_HRDATA(IMEM_0_HRDATA),
.IMEM_0_HREADY(IMEM_0_HREADY),
.IMEM_0_HRESP(IMEM_0_HRESP),
+ .IMEM_0_HREADYOUT(IMEM_0_HREADYOUT),
// DMEM 0 AHB Lite port
+ .DMEM_0_HSEL(DMEM_0_HSEL),
.DMEM_0_HADDR(DMEM_0_HADDR),
.DMEM_0_HTRANS(DMEM_0_HTRANS),
.DMEM_0_HWRITE(DMEM_0_HWRITE),
@@ -327,6 +316,7 @@ module nanosoc_system #(
.DMEM_0_HRDATA(DMEM_0_HRDATA),
.DMEM_0_HREADY(DMEM_0_HREADY),
.DMEM_0_HRESP(DMEM_0_HRESP),
+ .DMEM_0_HREADYOUT(DMEM_0_HREADYOUT),
// CPU Sideband signalling
.CPU_0_NMI(CPU_0_NMI),
@@ -414,9 +404,6 @@ module nanosoc_system #(
wire DMAC_0_ANY_DONE;
wire DMAC_1_ANY_DONE;
- assign EXP_DLAST [1:0] = 2'b00;
- assign DMAC_0_DMA_REQ = EXP_DRQ;
-
assign DMAC_0_ANY_DONE = |DMAC_0_DMA_DONE;
assign DMAC_1_ANY_DONE = |DMAC_1_DMA_DONE;
@@ -536,6 +523,11 @@ module nanosoc_system #(
assign DEBUG_RESETREQ = GPO8[0];
+ // Sideband Wiring
+ //--------------------------
+
+ assign CPU_0_RXEV = DMAC_ANY_DONE;
+
// Instantiate Subsystem
//--------------------------
nanosoc_ss_debug #(
@@ -546,7 +538,8 @@ module nanosoc_system #(
// SoCDebug Parameters
.PROMPT_CHAR(PROMPT_CHAR),
.FT1248_WIDTH(FT1248_WIDTH),
- .FT1248_CLKON(FT1248_CLKON)
+ .FT1248_CLKON(FT1248_CLKON),
+ .FT1248_CLKDIV(FT1248_CLKDIV)
) u_debug_ss (
// System Clocks and Resets
.SYS_HCLK(SYS_HCLK),
@@ -586,7 +579,6 @@ module nanosoc_system #(
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
- .FT_CLKDIV(FT_CLKDIV),
// GPIO interface
.GPO8(GPO8),
@@ -609,38 +601,43 @@ module nanosoc_system #(
wire EXP_HWRITE;
wire EXP_HREADY;
wire [31:0] EXP_HWDATA;
+ wire [2:0] EXP_HBURST;
wire EXP_HREADYOUT;
wire EXP_HRESP;
wire [31:0] EXP_HRDATA;
// SRAM Low Region AHB Port - To Interconnect Subsystem
- wire EXPSRAM_L_HSEL;
- wire [SYS_ADDR_W-1:0] EXPSRAM_L_HADDR;
- wire [1:0] EXPSRAM_L_HTRANS;
- wire [2:0] EXPSRAM_L_HSIZE;
- wire [3:0] EXPSRAM_L_HPROT;
- wire EXPSRAM_L_HWRITE;
- wire EXPSRAM_L_HREADY;
- wire [31:0] EXPSRAM_L_HWDATA;
+ wire EXPRAM_L_HSEL;
+ wire [SYS_ADDR_W-1:0] EXPRAM_L_HADDR;
+ wire [1:0] EXPRAM_L_HTRANS;
+ wire [2:0] EXPRAM_L_HSIZE;
+ wire [3:0] EXPRAM_L_HPROT;
+ wire EXPRAM_L_HWRITE;
+ wire EXPRAM_L_HREADY;
+ wire [31:0] EXPRAM_L_HWDATA;
+ wire [2:0] EXPRAM_L_HBURST;
- wire EXPSRAM_L_HREADYOUT;
- wire EXPSRAM_L_HRESP;
- wire [31:0] EXPSRAM_L_HRDATA;
+ wire EXPRAM_L_HREADYOUT;
+ wire EXPRAM_L_HRESP;
+ wire [31:0] EXPRAM_L_HRDATA;
+
// SRAM High Region AHB Port - To Interconnect Subsystem
- wire EXPSRAM_H_HSEL;
- wire [SYS_ADDR_W-1:0] EXPSRAM_H_HADDR;
- wire [1:0] EXPSRAM_H_HTRANS;
- wire [2:0] EXPSRAM_H_HSIZE;
- wire [3:0] EXPSRAM_H_HPROT;
- wire EXPSRAM_H_HWRITE;
- wire EXPSRAM_H_HREADY;
- wire [31:0] EXPSRAM_H_HWDATA;
+ wire EXPRAM_H_HSEL;
+ wire [SYS_ADDR_W-1:0] EXPRAM_H_HADDR;
+ wire [1:0] EXPRAM_H_HTRANS;
+ wire [2:0] EXPRAM_H_HSIZE;
+ wire [3:0] EXPRAM_H_HPROT;
+ wire EXPRAM_H_HWRITE;
+ wire EXPRAM_H_HREADY;
+ wire [31:0] EXPRAM_H_HWDATA;
+ wire [2:0] EXPRAM_H_HBURST;
- wire EXPSRAM_H_HREADYOUT;
- wire EXPSRAM_H_HRESP;
- wire [31:0] EXPSRAM_H_HRDATA;
+ wire EXPRAM_H_HREADYOUT;
+ wire EXPRAM_H_HRESP;
+ wire [31:0] EXPRAM_H_HRDATA;
+
// Interrupt Connections - TO CPU Subsystem
wire [3:0] EXP_IRQ;
@@ -649,6 +646,11 @@ module nanosoc_system #(
wire [1:0] EXP_DRQ;
wire [1:0] EXP_DLAST;
+ // Expansion DRQ Wiring
+ //--------------------------
+ assign EXP_DLAST [1:0] = 2'b00;
+ assign DMAC_0_DMA_REQ = EXP_DRQ;
+
// Instantiate Subsystem
//--------------------------
nanosoc_ss_expansion #(
@@ -682,30 +684,30 @@ module nanosoc_system #(
.EXP_HRDATA(EXP_HRDATA),
// SRAM Low Region AHB Port
- .EXPSRAM_L_HSEL(EXPSRAM_L_HSEL),
- .EXPSRAM_L_HADDR(EXPSRAM_L_HADDR),
- .EXPSRAM_L_HTRANS(EXPSRAM_L_HTRANS),
- .EXPSRAM_L_HSIZE(EXPSRAM_L_HSIZE),
- .EXPSRAM_L_HPROT(EXPSRAM_L_HPROT),
- .EXPSRAM_L_HWRITE(EXPSRAM_L_HWRITE),
- .EXPSRAM_L_HREADY(EXPSRAM_L_HREADY),
- .EXPSRAM_L_HWDATA(EXPSRAM_L_HWDATA),
- .EXPSRAM_L_HREADYOUT(EXPSRAM_L_HREADYOUT),
- .EXPSRAM_L_HRESP(EXPSRAM_L_HRESP),
- .EXPSRAM_L_HRDATA(EXPSRAM_L_HRDATA),
+ .EXPRAM_L_HSEL(EXPRAM_L_HSEL),
+ .EXPRAM_L_HADDR(EXPRAM_L_HADDR),
+ .EXPRAM_L_HTRANS(EXPRAM_L_HTRANS),
+ .EXPRAM_L_HSIZE(EXPRAM_L_HSIZE),
+ .EXPRAM_L_HPROT(EXPRAM_L_HPROT),
+ .EXPRAM_L_HWRITE(EXPRAM_L_HWRITE),
+ .EXPRAM_L_HREADY(EXPRAM_L_HREADY),
+ .EXPRAM_L_HWDATA(EXPRAM_L_HWDATA),
+ .EXPRAM_L_HREADYOUT(EXPRAM_L_HREADYOUT),
+ .EXPRAM_L_HRESP(EXPRAM_L_HRESP),
+ .EXPRAM_L_HRDATA(EXPRAM_L_HRDATA),
// SRAM High Region AHB Port
- .EXPSRAM_H_HSEL(EXPSRAM_H_HSEL),
- .EXPSRAM_H_HADDR(EXPSRAM_H_HADDR),
- .EXPSRAM_H_HTRANS(EXPSRAM_H_HTRANS),
- .EXPSRAM_H_HSIZE(EXPSRAM_H_HSIZE),
- .EXPSRAM_H_HPROT(EXPSRAM_H_HPROT),
- .EXPSRAM_H_HWRITE(EXPSRAM_H_HWRITE),
- .EXPSRAM_H_HREADY(EXPSRAM_H_HREADY),
- .EXPSRAM_H_HWDATA(EXPSRAM_H_HWDATA),
- .EXPSRAM_H_HREADYOUT(EXPSRAM_H_HREADYOUT),
- .EXPSRAM_H_HRESP(EXPSRAM_H_HRESP),
- .EXPSRAM_H_HRDATA(EXPSRAM_H_HRDATA),
+ .EXPRAM_H_HSEL(EXPRAM_H_HSEL),
+ .EXPRAM_H_HADDR(EXPRAM_H_HADDR),
+ .EXPRAM_H_HTRANS(EXPRAM_H_HTRANS),
+ .EXPRAM_H_HSIZE(EXPRAM_H_HSIZE),
+ .EXPRAM_H_HPROT(EXPRAM_H_HPROT),
+ .EXPRAM_H_HWRITE(EXPRAM_H_HWRITE),
+ .EXPRAM_H_HREADY(EXPRAM_H_HREADY),
+ .EXPRAM_H_HWDATA(EXPRAM_H_HWDATA),
+ .EXPRAM_H_HREADYOUT(EXPRAM_H_HREADYOUT),
+ .EXPRAM_H_HRESP(EXPRAM_H_HRESP),
+ .EXPRAM_H_HRDATA(EXPRAM_H_HRDATA),
// Interrupt and DMAC Connections
.EXP_IRQ(EXP_IRQ),
@@ -749,12 +751,6 @@ module nanosoc_system #(
wire [SYS_DATA_W-1:0] SYSTABLE_HRDATA; // AHB read-data
wire SYSTABLE_HRESP; // AHB response
wire SYSTABLE_HREADYOUT; // AHB ready out
-
- // Sysio APB driving signals - To all APB Components
- wire SYSIO_PENABLE;
- wire SYSIO_PWRITE;
- wire [APB_ADDR_W-1:0] SYSIO_PADDR;
- wire [APB_DATA_W-1:0] SYSIO_PWDATA;
// CPU sideband signalling - TO CPU Subsystem
wire SYS_NMI; // watchdog_interrupt;
@@ -782,6 +778,15 @@ module nanosoc_system #(
//--------------------------
assign SYS_REMAP_CTRL [3:0] = { 3'b000, !SYSIO_REMAP_CTRL};
+
+ // Reset Request Wiring
+ //--------------------------
+
+ assign SYS_SYSRESETREQ = CPU_0_SYSRESETREQ
+ | DEBUG_RESETREQ
+ | SYS_WDOGRESETREQ
+ | (SYS_LOCKUPRESET & CPU_0_LOCKUP);
+
// Instantiate Subsystem
//--------------------------
@@ -800,6 +805,7 @@ module nanosoc_system #(
.SYS_XTALCLK_OUT(SYS_XTALCLK_OUT), // Crystal Clock Output
// System Input Clocks and Resets
+ .SYS_SYSRESETn(SYS_SYSRESETn),
.SYS_PORESETn(SYS_PORESETn), // Power-On-Reset reset (active-low)
.SYS_TESTMODE(SYS_TESTMODE), // Reset bypass in scan test
.SYS_HCLK(SYS_HCLK), // AHB clock
@@ -848,7 +854,8 @@ module nanosoc_system #(
.SYSIO_PWDATA(SYSIO_PWDATA),
.USRT_PSEL(DEBUG_PSEL),
- .USRT_PRDATA(DEBUG_PREADY),
+ .USRT_PRDATA(DEBUG_PRDATA),
+ .USRT_PREADY(DEBUG_PREADY),
.USRT_PSLVERR(DEBUG_PSLVERR),
.DMAC_0_PSEL(DMAC_0_PSEL),
@@ -893,9 +900,23 @@ module nanosoc_system #(
.P1_IN(P1_IN),
.P1_OUT(P1_OUT),
.P1_OUTEN(P1_OUTEN),
- .P1_ALTFUNC(P1_ALTFUNC)
+ .P1_ALTFUNC(P1_ALTFUNC),
+ .P1_OUT_MUX(P1_OUT_MUX),
+ .P1_OUT_EN_MUX(P1_OUT_EN_MUX)
);
-
+
+ //--------------------------
+ // Interrupt Wiring
+ //--------------------------
+
+ assign CPU_0_IRQ [3:0] = EXP_IRQ [3:0];
+ assign CPU_0_IRQ [ 5: 4] = SYS_APB_IRQ[ 5: 4];
+ assign CPU_0_IRQ [ 6] = SYS_APB_IRQ[ 6] | (|SYS_GPIO0_ANY_IRQ);
+ assign CPU_0_IRQ [ 7] = SYS_APB_IRQ[ 7] | (|SYS_GPIO1_ANY_IRQ);
+ assign CPU_0_IRQ [14: 8] = SYS_APB_IRQ[14: 8];
+ assign CPU_0_IRQ [15] = SYS_APB_IRQ[15] | DMAC_ANY_DONE | DMAC_ANY_ERROR;
+ assign CPU_0_IRQ [31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
+
//--------------------------
// Interconnect Subsystem
//--------------------------
diff --git a/system/slcorem0_tech b/system/slcorem0_tech
index 3fbedbf..bc84f48 160000
--- a/system/slcorem0_tech
+++ b/system/slcorem0_tech
@@ -1 +1 @@
-Subproject commit 3fbedbfb068d360194d1d4b879e5a1eb28930d85
+Subproject commit bc84f48569a2833a67df85c609bc30b081568785
diff --git a/system/sldma230_tech b/system/sldma230_tech
index 858deb1..0b63e43 160000
--- a/system/sldma230_tech
+++ b/system/sldma230_tech
@@ -1 +1 @@
-Subproject commit 858deb1bd8a17fafabf015d702c5891236d024fb
+Subproject commit 0b63e4325cbc6d0ee1e5eff5620e38e14092c79d
diff --git a/system/socdebug_tech b/system/socdebug_tech
index 6a6da3c..ec5a608 160000
--- a/system/socdebug_tech
+++ b/system/socdebug_tech
@@ -1 +1 @@
-Subproject commit 6a6da3cfd4851abf6623991de6389f54593a9854
+Subproject commit ec5a60835a6ed8b44c084f701411914eeda75a4e
diff --git a/verif/verilog/nanosoc_tb.v b/verif/verilog/nanosoc_tb.v
index 8a7bc4f..80022c0 100644
--- a/verif/verilog/nanosoc_tb.v
+++ b/verif/verilog/nanosoc_tb.v
@@ -389,7 +389,7 @@ nanosoc_ft1248x1_track
`ifdef CORTEX_M0
`ifdef USE_TARMAC
-`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_cpu.u_cortex_m0_integration.u_cortexm0
+`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_cpu_ss.u_cpu_0.u_slcorem0_integration.u_cortexm0
CORTEXM0
#(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4),
@@ -523,7 +523,7 @@ nanosoc_ft1248x1_track
// - log the RTL Inuts/outputs/internal-state of this traccking DMAC
// --------------------------------------------------------------------------------
-`define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_pl230_udma
+`define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_dma_ss.u_dmac_0.u_pl230_udma
pl230_udma u_track_pl230_udma (
// Clock and Reset
@@ -597,29 +597,29 @@ nanosoc_ft1248x1_track
// Tracking Accelerator logging support
// --------------------------------------------------------------------------------
- `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper
-
- nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.TIMESTAMP(1))
- u_nanosoc_acc_log_to_file (
- .HCLK (`ACC_PATH.HCLK ),
- .HRESETn (`ACC_PATH.HRESETn ),
- .HSEL_i (`ACC_PATH.HSEL_i ),
- .HADDR_i (`ACC_PATH.HADDR_i ),
- .HTRANS_i (`ACC_PATH.HTRANS_i ),
- .HWRITE_i (`ACC_PATH.HWRITE_i ),
- .HSIZE_i (`ACC_PATH.HSIZE_i ),
- .HPROT_i (`ACC_PATH.HPROT_i ),
- .HWDATA_i (`ACC_PATH.HWDATA_i ),
- .HREADY_i (`ACC_PATH.HREADY_i ),
- .HRDATA_o (`ACC_PATH.HRDATA_o ),
- .HREADYOUT_o (`ACC_PATH.HREADYOUT_o ),
- .HRESP_o (`ACC_PATH.HRESP_o ),
- .exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ),
- .exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i),
- .exp_drq_op_o (`ACC_PATH.exp_drq_op_o ),
- .exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i),
- .exp_irq_o (`ACC_PATH.exp_irq_o )
- );
+// `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper
+
+// nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.TIMESTAMP(1))
+// u_nanosoc_acc_log_to_file (
+// .HCLK (`ACC_PATH.HCLK ),
+// .HRESETn (`ACC_PATH.HRESETn ),
+// .HSEL_i (`ACC_PATH.HSEL_i ),
+// .HADDR_i (`ACC_PATH.HADDR_i ),
+// .HTRANS_i (`ACC_PATH.HTRANS_i ),
+// .HWRITE_i (`ACC_PATH.HWRITE_i ),
+// .HSIZE_i (`ACC_PATH.HSIZE_i ),
+// .HPROT_i (`ACC_PATH.HPROT_i ),
+// .HWDATA_i (`ACC_PATH.HWDATA_i ),
+// .HREADY_i (`ACC_PATH.HREADY_i ),
+// .HRDATA_o (`ACC_PATH.HRDATA_o ),
+// .HREADYOUT_o (`ACC_PATH.HREADYOUT_o ),
+// .HRESP_o (`ACC_PATH.HRESP_o ),
+// .exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ),
+// .exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i),
+// .exp_drq_op_o (`ACC_PATH.exp_drq_op_o ),
+// .exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i),
+// .exp_irq_o (`ACC_PATH.exp_irq_o )
+// );
// --------------------------------------------------------------------------------
--
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