Wired Chip Level and made changes

flist/nanosoc.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Chip Related IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    NanoSoC Bus Matrix IP search path    =============
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_subsystem.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file

system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v

@@ -120,7 +120,9 @@ module nanosoc_ss_systemctrl #(
     input  wire            [15:0] P1_IN,            // GPIO 1 inputs
     output wire            [15:0] P1_OUT,           // GPIO 1 outputs
     output wire            [15:0] P1_OUTEN,         // GPIO 1 output enables
-    output wire            [15:0] P1_ALTFUNC        // GPIO 1 alternate function (pin mux)
+    output wire            [15:0] P1_ALTFUNC,       // GPIO 1 alternate function (pin mux)
+    output wire            [15:0] P1_OUT_MUX,       // GPIO 1 aOutput Port Drive
+    output wire            [15:0] P1_OUT_EN_MUX     // Active High output drive enable (pad tech dependent)
 );
     // -------------------------------
     // Internal Wiring

system/nanosoc_system/verilog/nanosoc_system.v

@@ -92,7 +92,19 @@ module nanosoc_system #(
     
     // GPIO interface
     output wire               [7:0] GPO8,
-    input  wire               [7:0] GPI8
+    input  wire               [7:0] GPI8,
+    
+    // GPIO
+    input  wire               [15:0] P0_IN,            // GPIO 0 inputs
+    output wire               [15:0] P0_OUT,           // GPIO 0 outputs
+    output wire               [15:0] P0_OUTEN,         // GPIO 0 output enables
+    output wire               [15:0] P0_ALTFUNC,       // GPIO 0 alternate function (pin mux)
+    input  wire               [15:0] P1_IN,            // GPIO 1 inputs
+    output wire               [15:0] P1_OUT,           // GPIO 1 outputs
+    output wire               [15:0] P1_OUTEN,         // GPIO 1 output enables
+    output wire               [15:0] P1_ALTFUNC,       // GPIO 1 alternate function (pin mux)
+    output wire               [15:0] P1_OUT_MUX,       // GPIO 1 aOutput Port Drive
+    output wire               [15:0] P1_OUT_EN_MUX     // Active High output drive enable (pad tech dependent)
 );
     //--------------------------
     // Local Parameters
@@ -757,16 +769,6 @@ module nanosoc_system #(
     // Lockup Signals - To System
     wire                   SYS_WDOGRESETREQ;   // Watchdog reset request
     wire                   SYS_LOCKUPRESET;    // System Controller cfg - Reset if lockup
-      
-    // GPIO - To Chip Level
-    wire            [15:0] P0_IN;            // GPIO 0 inputs
-    wire            [15:0] P0_OUT;           // GPIO 0 outputs
-    wire            [15:0] P0_OUTEN;         // GPIO 0 enables
-    wire            [15:0] P0_ALTFUNC;       // GPIO 0 alternate function (pin mux)
-    wire            [15:0] P1_IN;            // GPIO 1 inputs
-    wire            [15:0] P1_OUT;           // GPIO 1 outputs
-    wire            [15:0] P1_OUTEN;         // GPIO 1 enables
-    wire            [15:0] P1_ALTFUNC;       // GPIO 1 alternate function (pin mux)
     
     // Interrupt Wiring
     //--------------------------