From 6e8c794f6011058304f459f5c1e88c7d0804fa23 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Tue, 20 Jun 2023 14:46:20 +0100
Subject: [PATCH] Wired Chip Level and made changes
---
flist/nanosoc.flist | 34 +
.../nanosoc_chip/chip/verilog/nanosoc_chip.v | 1760 ++---------------
.../verilog/nanosoc_ss_systemctrl.v | 4 +-
.../nanosoc_system/verilog/nanosoc_system.v | 24 +-
4 files changed, 225 insertions(+), 1597 deletions(-)
create mode 100644 flist/nanosoc.flist
diff --git a/flist/nanosoc.flist b/flist/nanosoc.flist
new file mode 100644
index 0000000..fc7bb4a
--- /dev/null
+++ b/flist/nanosoc.flist
@@ -0,0 +1,34 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Chip Related IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Bus Matrix IP search path =============
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_subsystem.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file
diff --git a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 77721ca..8c4f729 100644
--- a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -1,1606 +1,196 @@
-//-----------------------------------------------------------------------------
-// customised top-level Cortex-M0 'nanosoc' controller
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
-//-----------------------------------------------------------------------------
-//
-
-//param ADDR_WIDTH_RAM = 9; // 512B
-//param ADDR_WIDTH_RAM = 10; // 1024B
-//param ADDR_WIDTH_RAM = 11; // 2KB
-//param ADDR_WIDTH_RAM = 12; // 4KB
-//param ADDR_WIDTH_RAM = 13; // 8KB
-//param ADDR_WIDTH_RAM = 14; // 16KB
-//param ADDR_WIDTH_RAM = 15; // 32KB
-//param ADDR_WIDTH_RAM = 16; // 64KB
-
module nanosoc_chip #(
- parameter SYS_ADDR_W = 32,
- parameter SYS_DATA_W = 32,
- parameter RAM_ADDR_W = 14,
- parameter RAM_DATA_W = 32
- )(
- `ifdef POWER_PINS
- inout wire VDDIO,
- inout wire VSSIO,
- inout wire VDD,
- inout wire VSS,
- `endif
- input wire xtal_clk_i,
- output wire xtal_clk_o,
- input wire nrst_i,
- input wire [15:0] p0_i, // level-shifted input from pad
- output wire [15:0] p0_o, // output port drive
- output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
- output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
- input wire [15:0] p1_i, // level-shifted input from pad
- output wire [15:0] p1_o, // output port drive
- output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
- output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
- input wire swdio_i,
- output wire swdio_o,
- output wire swdio_e,
- output wire swdio_z,
- input wire swdclk_i
- );
-
- localparam CLKGATE_PRESENT = 0;
- localparam DMA_CHANNEL_NUM = 2;
- localparam INCLUDE_DMA = 1;
- localparam CORTEX_M0 = 1;
-
-//------------------------------------
-// CMSDK internal wire naming preserved
-//------------------------------------
+ parameter integer FT1248_WIDTH = 1 // FTDI Interface 1,2,4 width supported
+)(
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+`endif
+ input wire xtal_clk_i,
+ output wire xtal_clk_o,
+ input wire nrst_i,
+ input wire [15:0] p0_i, // level-shifted input from pad
+ output wire [15:0] p0_o, // output port drive
+ output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
+ input wire [15:0] p1_i, // level-shifted input from pad
+ output wire [15:0] p1_o, // output port drive
+ output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
+ input wire swdio_i,
+ output wire swdio_o,
+ output wire swdio_e,
+ output wire swdio_z,
+ input wire swdclk_i
+);
- wire xtal_clk_in = xtal_clk_i;
- wire xtal_clk_out;
- wire pll_clk;
- wire CLK;
+ //--------------------------
+ // System Wiring
+ //--------------------------
+ // Free-running and Crystal Clock Output
+ wire SYS_CLK; // System Input Clock
+ wire PLL_CLK; // Phase-Locked Loop Clock
+ wire SYS_XTALCLK_OUT; // Crystal Clock Output
- assign xtal_clk_o = xtal_clk_out;
- wire SYSRESETn = nrst_i;
- wire [15:0] p0_in; // level-shifted input from pad
- wire [15:0] p0_out; // output port drive
- wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
- wire [15:0] p0_out_nen; // active low output drive enable (pad tech dependent)
-
- wire [15:0] p1_in; // level-shifted input from pad
- wire [15:0] p1_out; // output port drive
- wire [15:0] p1_out_en; // active high output drive enable (pad tech dependent)
- wire [15:0] p1_out_nen; // active low output drive enable (pad tech dependent)
- wire [15:0] p1_in_mux; // level-shifted input from pad
- wire [15:0] p1_out_mux; // output port drive
- wire [15:0] p1_out_en_mux; // active high output drive enable (pad tech dependent)
- wire [15:0] p1_out_nen_mux; // active low output drive enable (pad tech dependent)
-
- wire swdio_in;
- wire swdio_out;
- wire swdio_out_en;
- wire swdio_out_nen;
- wire swdclk_in;
-
- wire ft_clk_o;
- wire ft_ssn_o;
- wire ft_miso_i;
- wire ft_miosio_o;
- wire ft_miosio_e;
- wire ft_miosio_z;
- wire ft_miosio_i;
-
- // --------------------------------------------------------------------------------
- // Port-0 IO pad driver mapping
- // --------------------------------------------------------------------------------
-
- assign p0_in = p0_i; // level-shifted input from pad
- assign p0_o = p0_out; // output port drive
- assign p0_e = p0_out_en; // active high output drive enable (pad tech dependent)
- assign p0_z = p0_out_nen; // active low output drive enable (pad tech dependent)
-
-
- // --------------------------------------------------------------------------------
- // Port-1 IO pad driver mapping
- // --------------------------------------------------------------------------------
-
-// modify p1_mux [3:0] for ft1248 interface
-// assign p1_in_mux[3:0] = p1_i[3:0]; // IO MUX controlled bidirectionals
-// assign p1_o[3:0] = p1_out_mux[3:0];
-// assign p1_e[3:0] = p1_out_en_mux[3:0];
-// assign p1_z[3:0] = p1_out_nen_mux[3:0];
-
- assign ft_miso_i = p1_i[0]; // FT_MISO INPUT pad configuration
- assign p1_in_mux[0] = p1_i[0];
- assign p1_o[0] = 1'b0;
- assign p1_e[0] = 1'b0;
- assign p1_z[0] = 1'b1;
+ // Scan Wiring
+ wire SYS_SCANENABLE; // Scan Mode Enable
+ wire SYS_TESTMODE; // Test Mode Enable (Override Synchronisers)
+ wire INC_SCANINHCLK; // HCLK scan wire
+ wire INC_SCANOUTHCLK; // Scan Chain Output
- assign p1_in_mux[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
- assign p1_o[1] = ft_clk_o;
- assign p1_e[1] = 1'b1;
- assign p1_z[1] = 1'b0;
-
- assign ft_miosio_i = p1_i[2]; // FT_MIOSIO INOUT pad configuration
- assign p1_in_mux[2] = p1_i[2];
- assign p1_o[2] = ft_miosio_o;
- assign p1_e[2] = ft_miosio_e;
- assign p1_z[2] = ft_miosio_z;
-
- assign p1_in_mux[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
- assign p1_o[3] = ft_ssn_o;
- assign p1_e[3] = 1'b1;
- assign p1_z[3] = 1'b0;
-
- assign p1_in_mux[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
- assign p1_o[15:4] = p1_out_mux[15:4];
- assign p1_e[15:4] = p1_out_en_mux[15:4];
- assign p1_z[15:4] = p1_out_nen_mux[15:4];
-
-
-//TIE_HI uTIEHI (.tiehi(tiehi));
- wire tiehi = 1'b1;
-//TIE_LO uTIELO (.tielo(tielo));
- wire tielo = 1'b0;
-
-//----------------------------------------
-// SoC Clock and Reset Management
-//----------------------------------------
- wire PORESETn;// Power on reset
- wire HRESETn; // AHB reset
- wire PRESETn; // APB and peripheral reset
- wire DBGRESETn; // Debug system reset
- wire FCLK; // Free running system clock
- wire HCLK; // System clock from PMU
- wire DCLK;
- wire SCLK;
- wire PCLK; // Peripheral clock
- wire PCLKG; // Gated PCLK for APB
- wire PCLKEN; // Clock divider for AHB to APB bridge
- wire APBACTIVE;
+ // Serial-Wire Debug
+ wire CPU_0_SWDI; // SWD data input
+ wire CPU_0_SWCLK; // SWD clock
+ wire CPU_0_SWDO; // SWD data output
+ wire CPU_0_SWDOEN; // SWD data enable
- // event signals
- wire TXEV;
- wire RXEV;
- wire nTRST; // JTAG - Test reset (active low)
- wire SWDI; // JTAG/SWD - TMS / SWD data input
- wire SWCLK; // JTAG/SWD - TCK / SWCLK
- wire SWDO; // SWD - SWD data output
- wire SWDOEN; // SWD - SWD data output enable
- wire SYSRESETREQ; // processor system reset request
- wire WDOGRESETREQ; // watchdog system reset request
- wire HRESETREQ; // Combined system reset request
- wire NANOSOC_SYSRESETREQ; // Combined system reset request
- wire CCTRLRESETREQ;
- wire PMUHRESETREQ;
- wire PMUDBGRESETREQ;
- wire LOCKUP;
- wire LOCKUPRESET;
- wire SLEEPING;
- wire GATEHCLK; // Processor status - safe to gate HCLK
- wire WAKEUP; // Wake up request from WIC
- wire WICENREQ; // WIC enable request from PMU
- wire WICENACK; // WIC enable ack to PMU
- wire PMUENABLE;
- wire CDBGPWRUPREQ; // Debug Power Up request to PMU
- wire CDBGPWRUPACK; // Debug Power Up ACK from PMU
- wire SLEEPHOLDREQn; // Sleep extension request from PMU
- wire SLEEPHOLDACKn; // Sleep extension request to PMU
- wire SYSPWRDOWNACK;
- wire DBGPWRDOWNACK;
- wire SYSPWRDOWN;
- wire DBGPWRDOWN;
- wire SYSISOLATEn;
- wire SYSRETAINn;
- wire DBGISOLATEn;
- wire SLEEPDEEP;
- wire ADPRESETREQ;
- // Scan test dummy signals; not connected until scan insertion
- wire TESTMODE; // Test mode enable signal (override synchronizers etc)
- wire SCANENABLE; // Scan enable signal
- wire SCANINHCLK; // HCLK scan input
- wire SCANOUTHCLK; // Scan Chain wire
-
-// not required for FPGA
- assign TESTMODE = 1'b0;
- assign SCANENABLE = 1'b0;
- assign SCANINHCLK = 1'b0;
- assign SCANOUTHCLK = 1'b0;
-
-// Technology-specific PLL/Frequecy synthesizer would generate
-// CLK, FCLK (Free running system clock)
-// from
-// xtal_clk_in
-
- assign pll_clk = xtal_clk_in; // default to no PLL
-
- assign CLK = (TESTMODE) ? xtal_clk_in : pll_clk;
+ // FT1248 Interace - FT1248
+ wire FT_CLK_O; // SCLK
+ wire FT_SSN_O; // SS_N
+ wire FT_MISO_I; // MISO
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_O; // MIOSIO tristate when enabled
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_E; // MIOSIO tristate enable (active hi)
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z; // MIOSIO tristate enable (active lo)
+ wire [FT1248_WIDTH-1:0] FT_MIOSIO_I; // MIOSIO tristate input
+ wire [7:0] FT_CLKDIV; // divider prescaler to ensure SCLK <1MHz
-
-//? assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
- assign HCLK = FCLK;
+ // GPIO interface
+ wire [7:0] GPO8;
+ wire [7:0] GPI8;
- // System Reset request can be from processor or watchdog
- // or when lockup happens and the control flag is set.
- assign NANOSOC_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
- ADPRESETREQ |
- (LOCKUP & LOCKUPRESET);
- assign CCTRLRESETREQ = PMUHRESETREQ | HRESETREQ;
-
- // Clock controller to generate reset and clock signals
- nanosoc_mcu_clkctrl
- #(.CLKGATE_PRESENT(CLKGATE_PRESENT))
- u_nanosoc_mcu_clkctrl(
- // inputs
- .XTAL1 (CLK),
- .NRST (SYSRESETn),
-
- .APBACTIVE (APBACTIVE),
- .SLEEPING (SLEEPING),
- .SLEEPDEEP (SLEEPDEEP),
- .LOCKUP (LOCKUP),
- .LOCKUPRESET (LOCKUPRESET),
- .SYSRESETREQ (CCTRLRESETREQ),
- .DBGRESETREQ (PMUDBGRESETREQ),
- .CGBYPASS (TESTMODE),
- .RSTBYPASS (TESTMODE),
-
- // outputs
- .XTAL2 (xtal_clk_out),
-
- .FCLK (FCLK),
-
- .PCLK (PCLK),
- .PCLKG (PCLKG),
- .PCLKEN (PCLKEN),
-//?`ifdef CORTEX_M0DESIGNSTART
-//? .PORESETn (PORESETn), // for cm0 designstart
-//? .HRESETn (HRESETn), // for cm0 designstart
-//?`endif
- .PRESETn (PRESETn)
- );
-
- wire HCLKG;
- wire DCLKG;
- wire SCLKG;
-
- cortexm0_rst_ctl u_rst_ctl
- (// Inputs
- .GLOBALRESETn (SYSRESETn),
- .FCLK (FCLK),
- .HCLK (HCLKG),
- .DCLK (DCLKG),
- .SYSRESETREQ (NANOSOC_SYSRESETREQ),
- .PMUHRESETREQ (PMUHRESETREQ),
- .PMUDBGRESETREQ (PMUDBGRESETREQ),
- .RSTBYPASS (TESTMODE),
- .SE (SCANENABLE),
-
- // Outputs
- .PORESETn (PORESETn),
- .HRESETn (HRESETn),
- .DBGRESETn (DBGRESETn),
- .HRESETREQ (HRESETREQ));
-
-
- // Cortex-M0 Power management unit
- cortexm0_pmu u_cortexm0_pmu
- ( // Inputs
- .FCLK (FCLK),
- .PORESETn (PORESETn),
- .HRESETREQ (NANOSOC_SYSRESETREQ), // from processor / watchdog
- .PMUENABLE (PMUENABLE), // from System Controller
- .WICENACK (WICENACK), // from WIC in integration
-
- .WAKEUP (WAKEUP), // from WIC in integration
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
-
- .SLEEPDEEP (SLEEPDEEP),
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .GATEHCLK (GATEHCLK),
- .SYSPWRDOWNACK (SYSPWRDOWNACK),
- .DBGPWRDOWNACK (DBGPWRDOWNACK),
- .CGBYPASS (TESTMODE),
-
- // Outputs
- .HCLK (HCLKG),
- .DCLK (DCLKG),
- .SCLK (SCLKG),
- .WICENREQ (WICENREQ),
- .CDBGPWRUPACK (CDBGPWRUPACK),
- .SYSISOLATEn (SYSISOLATEn),
- .SYSRETAINn (SYSRETAINn),
- .SYSPWRDOWN (SYSPWRDOWN),
- .DBGISOLATEn (DBGISOLATEn),
- .DBGPWRDOWN (DBGPWRDOWN),
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .PMUDBGRESETREQ (PMUDBGRESETREQ),
- .PMUHRESETREQ (PMUHRESETREQ)
- );
-
- // Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
- assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : HCLKG;
- assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : DCLKG;
- assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : SCLKG;
-
-
- // In this example system, power control takes place immediately.
- // In a real circuit you might need to add delays in the next two
- // signal assignments for correct operation.
- assign SYSPWRDOWNACK = SYSPWRDOWN;
- assign DBGPWRDOWNACK = DBGPWRDOWN;
-
- wire exp_penable;
- wire exp_pwrite;
- wire [11:0] exp_paddr;
- wire [31:0] exp_pwdata;
- wire exp12_psel;
- wire exp12_pready;
- wire exp12_pslverr;
- wire [31:0] exp12_prdata;
- wire exp13_psel;
- wire exp13_pready;
- wire exp13_pslverr;
- wire [31:0] exp13_prdata;
- wire exp14_psel;
- wire exp14_pready;
- wire exp14_pslverr;
- wire [31:0] exp14_prdata;
- wire exp15_psel;
- wire exp15_pready;
- wire exp15_pslverr;
- wire [31:0] exp15_prdata;
-
-
- // internal peripheral signals
- wire uart0_rxd;
- wire uart0_txd;
- wire uart0_txen;
- wire uart1_rxd;
- wire uart1_txd;
- wire uart1_txen;
- wire uart2_rxd;
- wire uart2_txd;
- wire uart2_txen;
- wire timer0_extin;
- wire timer1_extin;
-
- wire [15:0] p0_altfunc;
-
- wire [15:0] p1_altfunc;
-
- wire exp_irq0;
- wire exp_irq1;
- wire exp_irq2;
- wire exp_irq3;
- wire exp_irqB;
- wire exp_irqC;
- wire exp_irqD;
+ // GPIO
+ wire [15:0] P0_IN; // GPIO 0 inputs
+ wire [15:0] P0_OUT; // GPIO 0 outputs
+ wire [15:0] P0_OUTEN; // GPIO 0 output enables
+ wire [15:0] P0_ALTFUNC; // GPIO 0 alternate function (pin mux)
-// -----------------------------------------------------------------------------
-// AHB Interconnect declarations
-// Upper-case AMBA naming convention maintained
-// -----------------------------------------------------------------------------
-
- // System Address Remap control
- wire [3:0] REMAP; // System Address REMAP control, bit-0 set on POR
- wire ROM_MAP;
-
- // Manager port SI0 (inputs from master 0)
- wire [SYS_ADDR_W-1:0] HADDR_adp; // Address bus
- wire [1:0] HTRANS_adp; // Transfer type
- wire HWRITE_adp; // Transfer direction
- wire [2:0] HSIZE_adp; // Transfer size
- wire [2:0] HBURST_adp; // Burst type
- wire [3:0] HPROT_adp; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_adp; // Write data
- wire HMASTLOCK_adp; // Locked Sequence
- wire [1:0] HAUSER_adp; // Address USER signals
- wire [1:0] HWUSER_adp; // Write-data USER signals
- // Manager port SI0 (outputs to master 0)
- wire [SYS_DATA_W-1:0] HRDATA_adp; // Read data bus
- wire HREADY_adp; // HREADY feedback
- wire HRESP_adp; // Transfer response
- wire [1:0] HRUSER_adp; // Read-data USER signals
-
- // Manager port SI1 (inputs from master 1)
- wire [SYS_ADDR_W-1:0] HADDR_dma; // Address bus
- wire [1:0] HTRANS_dma; // Transfer type
- wire HWRITE_dma; // Transfer direction
- wire [2:0] HSIZE_dma; // Transfer size
- wire [2:0] HBURST_dma; // Burst type
- wire [3:0] HPROT_dma; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_dma; // Write data
- wire HMASTLOCK_dma; // Locked Sequence
- wire [1:0] HAUSER_dma; // Address USER signals
- wire [1:0] HWUSER_dma; // Write-data USER signals
- // Manager port SI1 (outputs to master 1)
- wire [SYS_DATA_W-1:0] HRDATA_dma; // Read data bus
- wire HREADY_dma; // HREADY feedback
- wire HRESP_dma; // Transfer response
- wire [1:0] HRUSER_dma; // Read-data USER signals
-
- // Manager port SI2 (inputs from master 2)
- wire [SYS_ADDR_W-1:0] HADDR_dma2; // Address bus
- wire [1:0] HTRANS_dma2; // Transfer type
- wire HWRITE_dma2; // Transfer direction
- wire [2:0] HSIZE_dma2; // Transfer size
- wire [2:0] HBURST_dma2; // Burst type
- wire [3:0] HPROT_dma2; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_dma2; // Write data
- wire HMASTLOCK_dma2; // Locked Sequence
- wire [1:0] HAUSER_dma2; // Address USER signals
- wire [1:0] HWUSER_dma2; // Write-data USER signals
- // Manager port SI2 (outputs to master 2)
- wire [SYS_DATA_W-1:0] HRDATA_dma2; // Read data bus
- wire HREADY_dma2; // HREADY feedback
- wire HRESP_dma2; // Transfer response
- wire [1:0] HRUSER_dma2; // Read-data USER signals
-
- // Manager port SI3 (inputs from master 3)
- wire [SYS_ADDR_W-1:0] HADDR_cpu; // Address bus
- wire [1:0] HTRANS_cpu; // Transfer type
- wire HWRITE_cpu; // Transfer direction
- wire [2:0] HSIZE_cpu; // Transfer size
- wire [2:0] HBURST_cpu; // Burst type
- wire [3:0] HPROT_cpu; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_cpu; // Write data
- wire HMASTLOCK_cpu; // Locked Sequence
- wire [1:0] HAUSER_cpu; // Address USER signals
- wire [1:0] HWUSER_cpu; // Write-data USER signals
- // Manager port SI3 (outputs to master 3)
- wire [SYS_DATA_W-1:0] HRDATA_cpu; // Read data bus
- wire HREADY_cpu; // HREADY feedback
- wire HRESP_cpu; // Transfer response
- wire [1:0] HRUSER_cpu; // Read-data USER signals
-
- // Subordinate port MI0 (outputs to slave 0)
- wire HSEL_bootrom; // Slave Select
- wire [SYS_ADDR_W-1:0] HADDR_bootrom; // Address bus
- wire [1:0] HTRANS_bootrom; // Transfer type
- wire HWRITE_bootrom; // Transfer direction
- wire [2:0] HSIZE_bootrom; // Transfer size
- wire [2:0] HBURST_bootrom; // Burst type
- wire [3:0] HPROT_bootrom; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_bootrom; // Write data
- wire HMASTLOCK_bootrom; // Locked Sequence
- wire HREADYMUX_bootrom; // Transfer done
- wire [1:0] HAUSER_bootrom; // Address USER signals
- wire [1:0] HWUSER_bootrom; // Write-data USER signals
- // Subordinate port MI0 (inputs from slave 0)
- wire [SYS_DATA_W-1:0] HRDATA_bootrom; // Read data bus
- wire HREADYOUT_bootrom; // HREADY feedback
- wire HRESP_bootrom; // Transfer response
- wire [1:0] HRUSER_bootrom; // Read-data USER signals
-
- // Subordinate port MI1 (outputs to slave 1)
- wire HSEL_imem; // Slave Select
- wire [SYS_ADDR_W-1:0] HADDR_imem; // Address bus
- wire [1:0] HTRANS_imem; // Transfer type
- wire HWRITE_imem; // Transfer direction
- wire [2:0] HSIZE_imem; // Transfer size
- wire [2:0] HBURST_imem; // Burst type
- wire [3:0] HPROT_imem; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_imem; // Write data
- wire HMASTLOCK_imem; // Locked Sequence
- wire HREADYMUX_imem; // Transfer done
- wire [1:0] HAUSER_imem; // Address USER signals
- wire [1:0] HWUSER_imem; // Write-data USER signals
- // Subordinate port MI1 (inputs from slave 1)
- wire [SYS_DATA_W-1:0] HRDATA_imem; // Read data bus
- wire HREADYOUT_imem; // HREADY feedback
- wire HRESP_imem; // Transfer response
- wire [1:0] HRUSER_imem; // Read-data USER signals
-
- // Subordinate port MI2 (outputs to slave 2)
- wire HSEL_dmem; // Slave Select
- wire [SYS_ADDR_W-1:0] HADDR_dmem; // Address bus
- wire [1:0] HTRANS_dmem; // Transfer type
- wire HWRITE_dmem; // Transfer direction
- wire [2:0] HSIZE_dmem; // Transfer size
- wire [2:0] HBURST_dmem; // Burst type
- wire [3:0] HPROT_dmem; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_dmem; // Write data
- wire HMASTLOCK_dmem; // Locked Sequence
- wire HREADYMUX_dmem; // Transfer done
- wire [1:0] HAUSER_dmem; // Address USER signals
- wire [1:0] HWUSER_dmem; // Write-data USER signals
- // Subordinate port MI2 (inputs from slave 2)
- wire [SYS_DATA_W-1:0] HRDATA_dmem; // Read data bus
- wire HREADYOUT_dmem; // HREADY feedback
- wire HRESP_dmem; // Transfer response
- wire [1:0] HRUSER_dmem; // Read-data USER signals
-
- // Subordinate port MI3 (outputs to slave 3)
- wire HSEL_sysio; // Slave Select
- wire [SYS_ADDR_W-1:0] HADDR_sysio; // Address bus
- wire [1:0] HTRANS_sysio; // Transfer type
- wire HWRITE_sysio; // Transfer direction
- wire [2:0] HSIZE_sysio; // Transfer size
- wire [2:0] HBURST_sysio; // Burst type
- wire [3:0] HPROT_sysio; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_sysio; // Write data
- wire HMASTLOCK_sysio; // Locked Sequence
- wire HREADYMUX_sysio; // Transfer done
- wire [1:0] HAUSER_sysio; // Address USER signals
- wire [1:0] HWUSER_sysio; // Write-data USER signals
- // Subordinate port MI3 (inputs from slave 3)
- wire [SYS_DATA_W-1:0] HRDATA_sysio; // Read data bus
- wire HREADYOUT_sysio; // HREADY feedback
- wire HRESP_sysio; // Transfer response
- wire [1:0] HRUSER_sysio; // Read-data USER signals
-
- // Subordinate port MI4 (outputs to slave 4)
- wire HSEL_expram_l; // Slave Select
- wire [SYS_ADDR_W-1:0] HADDR_expram_l; // Address bus
- wire [1:0] HTRANS_expram_l; // Transfer type
- wire HWRITE_expram_l; // Transfer direction
- wire [2:0] HSIZE_expram_l; // Transfer size
- wire [2:0] HBURST_expram_l; // Burst type
- wire [3:0] HPROT_expram_l; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_expram_l; // Write data
- wire HMASTLOCK_expram_l; // Locked Sequence
- wire HREADYMUX_expram_l; // Transfer done
- wire [1:0] HAUSER_expram_l; // Address USER signals
- wire [1:0] HWUSER_expram_l; // Write-data USER signals
- // Subordinate port MI4 (inputs from slave 4)
- wire [SYS_DATA_W-1:0] HRDATA_expram_l; // Read data bus
- wire HREADYOUT_expram_l; // HREADY feedback
- wire HRESP_expram_l; // Transfer response
- wire [1:0] HRUSER_expram_l; // Read-data USER signals
-
- // Subordinate port MI5 (outputs to slave 5)
- wire HSEL_expram_h; // Slave Select
- wire [SYS_ADDR_W-1:0] HADDR_expram_h; // Address bus
- wire [1:0] HTRANS_expram_h; // Transfer type
- wire HWRITE_expram_h; // Transfer direction
- wire [2:0] HSIZE_expram_h; // Transfer size
- wire [2:0] HBURST_expram_h; // Burst type
- wire [3:0] HPROT_expram_h; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_expram_h; // Write data
- wire HMASTLOCK_expram_h; // Locked Sequence
- wire HREADYMUX_expram_h; // Transfer done
- wire [1:0] HAUSER_expram_h; // Address USER signals
- wire [1:0] HWUSER_expram_h; // Write-data USER signals
- // Subordinate port MI5 (inputs from slave 5)
- wire [SYS_DATA_W-1:0] HRDATA_expram_h; // Read data bus
- wire HREADYOUT_expram_h; // HREADY feedback
- wire HRESP_expram_h; // Transfer response
- wire [1:0] HRUSER_expram_h; // Read-data USER signals
-
- // Subordinate port MI6 (outputs to slave 6)
- wire HSEL_exp; // Slave Select
- wire [SYS_ADDR_W-1:0] HADDR_exp; // Address bus
- wire [1:0] HTRANS_exp; // Transfer type
- wire HWRITE_exp; // Transfer direction
- wire [2:0] HSIZE_exp; // Transfer size
- wire [2:0] HBURST_exp; // Burst type
- wire [3:0] HPROT_exp; // Protection control
- wire [SYS_DATA_W-1:0] HWDATA_exp; // Write data
- wire HMASTLOCK_exp; // Locked Sequence
- wire HREADYMUX_exp; // Transfer done
- wire [1:0] HAUSER_exp; // Address USER signals
- wire [1:0] HWUSER_exp; // Write-data USER signals
- // Subordinate port MI5 (inputs from slave 6)
- wire [SYS_DATA_W-1:0] HRDATA_exp; // Read data bus
- wire HREADYOUT_exp; // HREADY feedback
- wire HRESP_exp; // Transfer response
- wire [1:0] HRUSER_exp; // Read-data USER signals
-
-
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-// Interconnect matrix
-// 4 AHB-lite managers, 7 AHB-lite layer interfaces
-//------------------------------------------------------------------------------
-
-// BusMatrix instance
- nanosoc_ahb32_4x7_busmatrix_lite u_nanosoc_ahb32_4x7_busmatrix_lite (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .REMAP (REMAP),
-
- // Input port SI0 signals
- .HADDR_adp (HADDR_adp),
- .HTRANS_adp (HTRANS_adp),
- .HWRITE_adp (HWRITE_adp),
- .HSIZE_adp (HSIZE_adp),
- .HBURST_adp (HBURST_adp),
- .HPROT_adp (HPROT_adp),
- .HWDATA_adp (HWDATA_adp),
- .HMASTLOCK_adp (HMASTLOCK_adp),
- .HREADY_adp (HREADY_adp),
- .HAUSER_adp (HAUSER_adp),
- .HWUSER_adp (HWUSER_adp),
- .HRDATA_adp (HRDATA_adp),
- .HRESP_adp (HRESP_adp),
- .HRUSER_adp (HRUSER_adp),
-
- // Input port SI1 signals
- .HADDR_dma (HADDR_dma),
- .HTRANS_dma (HTRANS_dma),
- .HWRITE_dma (HWRITE_dma),
- .HSIZE_dma (HSIZE_dma),
- .HBURST_dma (HBURST_dma),
- .HPROT_dma (HPROT_dma),
- .HWDATA_dma (HWDATA_dma),
- .HMASTLOCK_dma (HMASTLOCK_dma),
- .HREADY_dma (HREADY_dma),
- .HAUSER_dma (HAUSER_dma),
- .HWUSER_dma (HWUSER_dma),
- .HRDATA_dma (HRDATA_dma),
- .HRESP_dma (HRESP_dma),
- .HRUSER_dma (HRUSER_dma),
-
- // Input port SI2 signals
- .HADDR_dma2 (HADDR_dma2),
- .HTRANS_dma2 (HTRANS_dma2),
- .HWRITE_dma2 (HWRITE_dma2),
- .HSIZE_dma2 (HSIZE_dma2),
- .HBURST_dma2 (HBURST_dma2),
- .HPROT_dma2 (HPROT_dma2),
- .HWDATA_dma2 (HWDATA_dma2),
- .HMASTLOCK_dma2 (HMASTLOCK_dma2),
- .HREADY_dma2 (HREADY_dma2),
- .HAUSER_dma2 (HAUSER_dma2),
- .HWUSER_dma2 (HWUSER_dma2),
- .HRDATA_dma2 (HRDATA_dma2),
- .HRESP_dma2 (HRESP_dma2),
- .HRUSER_dma2 (HRUSER_dma2),
-
- // Input port SI3 signals
- .HADDR_cpu (HADDR_cpu),
- .HTRANS_cpu (HTRANS_cpu),
- .HWRITE_cpu (HWRITE_cpu),
- .HSIZE_cpu (HSIZE_cpu),
- .HBURST_cpu (HBURST_cpu),
- .HPROT_cpu (HPROT_cpu),
- .HWDATA_cpu (HWDATA_cpu),
- .HMASTLOCK_cpu (HMASTLOCK_cpu),
- .HREADY_cpu (HREADY_cpu),
- .HAUSER_cpu (HAUSER_cpu),
- .HWUSER_cpu (HWUSER_cpu),
- .HRDATA_cpu (HRDATA_cpu),
- .HRESP_cpu (HRESP_cpu),
- .HRUSER_cpu (HRUSER_cpu),
-
- // Output port MI0 signals
- .HSEL_bootrom (HSEL_bootrom),
- .HADDR_bootrom (HADDR_bootrom),
- .HTRANS_bootrom (HTRANS_bootrom),
- .HWRITE_bootrom (HWRITE_bootrom),
- .HSIZE_bootrom (HSIZE_bootrom),
- .HBURST_bootrom (HBURST_bootrom),
- .HPROT_bootrom (HPROT_bootrom),
- .HWDATA_bootrom (HWDATA_bootrom),
- .HMASTLOCK_bootrom (HMASTLOCK_bootrom),
- .HREADYMUX_bootrom (HREADYMUX_bootrom),
- .HAUSER_bootrom (HAUSER_bootrom),
- .HWUSER_bootrom (HWUSER_bootrom),
- .HRDATA_bootrom (HRDATA_bootrom),
- .HREADYOUT_bootrom (HREADYOUT_bootrom),
- .HRESP_bootrom (HRESP_bootrom),
- .HRUSER_bootrom (HRUSER_bootrom),
-
- // Output port MI1 signals
- .HSEL_imem (HSEL_imem),
- .HADDR_imem (HADDR_imem),
- .HTRANS_imem (HTRANS_imem),
- .HWRITE_imem (HWRITE_imem),
- .HSIZE_imem (HSIZE_imem),
- .HBURST_imem (HBURST_imem),
- .HPROT_imem (HPROT_imem),
- .HWDATA_imem (HWDATA_imem),
- .HMASTLOCK_imem (HMASTLOCK_imem),
- .HREADYMUX_imem (HREADYMUX_imem),
- .HAUSER_imem (HAUSER_imem),
- .HWUSER_imem (HWUSER_imem),
- .HRDATA_imem (HRDATA_imem),
- .HREADYOUT_imem (HREADYOUT_imem),
- .HRESP_imem (HRESP_imem),
- .HRUSER_imem (HRUSER_imem),
-
- // Output port MI2 signals
- .HSEL_dmem (HSEL_dmem),
- .HADDR_dmem (HADDR_dmem),
- .HTRANS_dmem (HTRANS_dmem),
- .HWRITE_dmem (HWRITE_dmem),
- .HSIZE_dmem (HSIZE_dmem),
- .HBURST_dmem (HBURST_dmem),
- .HPROT_dmem (HPROT_dmem),
- .HWDATA_dmem (HWDATA_dmem),
- .HMASTLOCK_dmem (HMASTLOCK_dmem),
- .HREADYMUX_dmem (HREADYMUX_dmem),
- .HAUSER_dmem (HAUSER_dmem),
- .HWUSER_dmem (HWUSER_dmem),
- .HRDATA_dmem (HRDATA_dmem),
- .HREADYOUT_dmem (HREADYOUT_dmem),
- .HRESP_dmem (HRESP_dmem),
- .HRUSER_dmem (HRUSER_dmem),
-
- // Output port MI3 signals
- .HSEL_sysio (HSEL_sysio),
- .HADDR_sysio (HADDR_sysio),
- .HTRANS_sysio (HTRANS_sysio),
- .HWRITE_sysio (HWRITE_sysio),
- .HSIZE_sysio (HSIZE_sysio),
- .HBURST_sysio (HBURST_sysio),
- .HPROT_sysio (HPROT_sysio),
- .HWDATA_sysio (HWDATA_sysio),
- .HMASTLOCK_sysio (HMASTLOCK_sysio),
- .HREADYMUX_sysio (HREADYMUX_sysio),
- .HAUSER_sysio (HAUSER_sysio),
- .HWUSER_sysio (HWUSER_sysio),
- .HRDATA_sysio (HRDATA_sysio),
- .HREADYOUT_sysio (HREADYOUT_sysio),
- .HRESP_sysio (HRESP_sysio),
- .HRUSER_sysio (HRUSER_sysio),
-
- // Output port MI4 signals
- .HSEL_expram_l (HSEL_expram_l),
- .HADDR_expram_l (HADDR_expram_l),
- .HTRANS_expram_l (HTRANS_expram_l),
- .HWRITE_expram_l (HWRITE_expram_l),
- .HSIZE_expram_l (HSIZE_expram_l),
- .HBURST_expram_l (HBURST_expram_l),
- .HPROT_expram_l (HPROT_expram_l),
- .HWDATA_expram_l (HWDATA_expram_l),
- .HMASTLOCK_expram_l (HMASTLOCK_expram_l),
- .HREADYMUX_expram_l (HREADYMUX_expram_l),
- .HAUSER_expram_l (HAUSER_expram_l),
- .HWUSER_expram_l (HWUSER_expram_l),
- .HRDATA_expram_l (HRDATA_expram_l),
- .HREADYOUT_expram_l (HREADYOUT_expram_l),
- .HRESP_expram_l (HRESP_expram_l),
- .HRUSER_expram_l (HRUSER_expram_l),
-
- // Output port MI5 signals
- .HSEL_expram_h (HSEL_expram_h),
- .HADDR_expram_h (HADDR_expram_h),
- .HTRANS_expram_h (HTRANS_expram_h),
- .HWRITE_expram_h (HWRITE_expram_h),
- .HSIZE_expram_h (HSIZE_expram_h),
- .HBURST_expram_h (HBURST_expram_h),
- .HPROT_expram_h (HPROT_expram_h),
- .HWDATA_expram_h (HWDATA_expram_h),
- .HMASTLOCK_expram_h (HMASTLOCK_expram_h),
- .HREADYMUX_expram_h (HREADYMUX_expram_h),
- .HAUSER_expram_h (HAUSER_expram_h),
- .HWUSER_expram_h (HWUSER_expram_h),
- .HRDATA_expram_h (HRDATA_expram_h),
- .HREADYOUT_expram_h (HREADYOUT_expram_h),
- .HRESP_expram_h (HRESP_expram_h),
- .HRUSER_expram_h (HRUSER_expram_h),
-
- // Output port MI6 signals
- .HSEL_exp (HSEL_exp),
- .HADDR_exp (HADDR_exp),
- .HTRANS_exp (HTRANS_exp),
- .HWRITE_exp (HWRITE_exp),
- .HSIZE_exp (HSIZE_exp),
- .HBURST_exp (HBURST_exp),
- .HPROT_exp (HPROT_exp),
- .HWDATA_exp (HWDATA_exp),
- .HMASTLOCK_exp (HMASTLOCK_exp),
- .HREADYMUX_exp (HREADYMUX_exp),
- .HAUSER_exp (HAUSER_exp),
- .HWUSER_exp (HWUSER_exp),
- .HRDATA_exp (HRDATA_exp),
- .HREADYOUT_exp (HREADYOUT_exp),
- .HRESP_exp (HRESP_exp),
- .HRUSER_exp (HRUSER_exp),
-
- // Scan test dummy signals; not connected until scan insertion
- .SCANENABLE (SCANENABLE),
- .SCANINHCLK (SCANINHCLK),
- .SCANOUTHCLK (SCANOUTHCLK)
- );
-
-//----------------------------------------
-// Bootrom Region (region_bootrom)
-//----------------------------------------
+ wire [15:0] P1_IN; // GPIO 1 inputs
+ wire [15:0] P1_IN_MUX; // level-shifted input from pad
+ wire [15:0] P1_OUT; // GPIO 1 outputs
+ wire [15:0] P1_OUTEN; // GPIO 1 output enables
+ wire [15:0] P1_OUT_MUX; // GPIO 1 aOutput Port Drive
+ wire [15:0] P1_OUT_EN_MUX; // Active High output drive enable (pad tech dependent)
+ wire [15:0] P1_ALTFUNC; // GPIO 1 alternate function (pin mux)
- localparam BOOTROM_ADDR_W = 10;
+ //--------------------------
+ // FPGA-Specific Wiring - Should be own Module
+ //--------------------------
- nanosoc_region_bootrom #(
- .SYS_ADDR_W (SYS_ADDR_W),
- .SYS_DATA_W (SYS_DATA_W),
- .BOOTROM_ADDR_W (BOOTROM_ADDR_W)
- ) u_nanosoc_region_bootrom (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_bootrom),
- .HADDR (HADDR_bootrom),
- .HTRANS (HTRANS_bootrom),
- .HSIZE (HSIZE_bootrom),
- .HPROT (HPROT_bootrom),
- .HWRITE (HWRITE_bootrom),
- .HREADY (HREADYMUX_bootrom),
- .HWDATA (HWDATA_bootrom),
- .HREADYOUT (HREADYOUTS_bootrom),
- .HRESP (HRESPS_bootrom),
- .HRDATA (HRDATA_bootrom)
- );
+ // Technology-specific PLL/Frequecy synthesizer would generate
+ // CLK, FCLK (Free running system clock)
+ // from
+ // xtal_clk_i
-//----------------------------------------
-// Instruction Memory Region (region_imem)
-//----------------------------------------
-
- localparam IMEM_RAM_ADDR_W = RAM_ADDR_W;
- localparam IMEM_RAM_DATA_W = RAM_DATA_W;
- localparam IMEM_RAM_FPGA_IMG = "image.hex";
-
- nanosoc_region_imem #(
- .SYS_ADDR_W (SYS_ADDR_W),
- .SYS_DATA_W (SYS_DATA_W),
- .IMEM_RAM_ADDR_W (IMEM_RAM_ADDR_W),
- .IMEM_RAM_DATA_W (IMEM_RAM_DATA_W),
- .IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG)
- ) u_nanosoc_region_imem (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_imem),
- .HADDR (HADDR_imem),
- .HTRANS (HTRANS_imem),
- .HSIZE (HSIZE_imem),
- .HPROT (HPROT_imem),
- .HWRITE (HWRITE_imem),
- .HREADY (HREADYMUX_imem),
- .HWDATA (HWDATA_imem),
- .HREADYOUT (HREADYOUTS_imem),
- .HRESP (HRESPS_imem),
- .HRDATA (HRDATA_imem)
- );
+ assign PLL_CLK = xtal_clk_i; // Default to no PLL
-//----------------------------------------
-// Data Memory Region (region_dmem)
-//----------------------------------------
-
- localparam DMEM_RAM_ADDR_W = RAM_ADDR_W;
- localparam DMEM_RAM_DATA_W = RAM_DATA_W;
-
- nanosoc_region_dmem #(
- .SYS_ADDR_W (SYS_ADDR_W),
- .SYS_DATA_W (SYS_DATA_W),
- .DMEM_RAM_ADDR_W (DMEM_RAM_ADDR_W),
- .DMEM_RAM_DATA_W (DMEM_RAM_DATA_W)
- ) u_nanosoc_region_dmem (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_dmem),
- .HADDR (HADDR_dmem),
- .HTRANS (HTRANS_dmem),
- .HSIZE (HSIZE_dmem),
- .HPROT (HPROT_dmem),
- .HWRITE (HWRITE_dmem),
- .HREADY (HREADYMUX_dmem),
- .HWDATA (HWDATA_dmem),
- .HREADYOUT (HREADYOUTS_dmem),
- .HRESP (HRESPS_dmem),
- .HRDATA (HRDATA_dmem)
- );
-
-//----------------------------------------
-// System Peripheral Region (region_sysio)
-//----------------------------------------
-
-//---------------------------------------------
-// Expansion SRAM Low Region (region_expram_l)
-//---------------------------------------------
-
-//----------------------------------------------
-// Expansion SRAM High Region (region_expram_h)
-//----------------------------------------------
-
-// ************************************************
-// ************************************************
-//
-// ADD YOUR EXPERIMENTAL AHB-MAPPED WRAPPER HERE
-//
-//
-// ************************************************
-
- wire exp_drq_ip;
- wire exp_drq_op;
- wire [3:0] exp_irq;
- wire exp_merged_irq;
- assign exp_irq0 = exp_irq[0];
- assign exp_irq1 = exp_irq[1];
- assign exp_irq2 = exp_irq[2];
- assign exp_irq3 = exp_irq[3];
-
-//----------------------------------------
-// Expansion Region "exp" instance
-//----------------------------------------
-
-`ifdef NANOSOC_EXPANSION_REGION
-
-nanosoc_exp_wrapper #(
- .AHBADDRWIDTH(29),
- .INPACKETWIDTH(16),
- .CFGSIZEWIDTH(32),
- .CFGSCHEMEWIDTH(1),
- .OUTPACKETWIDTH(16),
- .CFGNUMIRQ(4)
-) u_nanosoc_exp_wrapper (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- // AHB port: 32 bit data bus interface
- .HSEL_i (HSEL_exp),
- .HADDR_i (HADDR_exp[28:0]),
- .HTRANS_i (HTRANS_exp),
- .HSIZE_i (HSIZE_exp),
- .HPROT_i (HPROT_exp),
- .HWRITE_i (HWRITE_exp),
- .HREADY_i (HREADYMUX_exp),
- .HWDATA_i (HWDATA_exp),
- .HREADYOUT_o (HREADYOUT_exp),
- .HRESP_o (HRESP_exp),
- .HRDATA_o (HRDATA_exp),
- .exp_drq_ip_o (exp_drq_ip),
- .exp_dlast_ip_i(1'b0),
- .exp_drq_op_o (exp_drq_op),
- .exp_dlast_op_i(1'b0),
- .exp_irq_o (exp_irq)
-);
-
-`else
-
- // Default slave - if no expansion region
- cmsdk_ahb_default_slave u_ahb_exp (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_exp),
- .HTRANS (HTRANS_exp),
- .HREADY (HREADYMUX_exp),
- .HREADYOUT (HREADYOUT_exp),
- .HRESP (HRESP_exp)
-);
- assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data
-
-`endif
-
- assign HRUSER_exp = 2'b00;
+ assign SYS_SCANENABLE = 1'b0;
+ assign SYS_TESTMODE = 1'b0;
+ assign INC_SCANINHCLK = 1'b0;
+ assign INC_SCANOUTHCLK = 1'b0;
-//----------------------------------------
-// Expansion/DMA "ram8,ram9" RAM instances
-//----------------------------------------
-
-localparam AWRAM8 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
- wire [AWRAM8-3:0] addr_expram_l;
- wire [31:0] wdata_expram_l;
- wire [31:0] rdata_expram_l;
- wire [3:0] wen_expram_l;
- wire cs_expram_l;
-
- // AHB to SRAM bridge
- cmsdk_ahb_to_sram #(.AW(AWRAM8)) u_ahb_to_sram8
- (
- // AHB Inputs
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_expram_l), // AHB inputs
- .HADDR (HADDR_expram_l[AWRAM8-1:0]),
- .HTRANS (HTRANS_expram_l),
- .HSIZE (HSIZE_expram_l),
- .HWRITE (HWRITE_expram_l),
- .HWDATA (HWDATA_expram_l),
- .HREADY (HREADYMUX_expram_l),
-
- // AHB Outputs
- .HREADYOUT (HREADYOUT_expram_l), // Outputs
- .HRDATA (HRDATA_expram_l),
- .HRESP (HRESP_expram_l),
-
- // SRAM input
- .SRAMRDATA (rdata_expram_l),
- // SRAM Outputs
- .SRAMADDR (addr_expram_l),
- .SRAMWDATA (wdata_expram_l),
- .SRAMWEN (wen_expram_l),
- .SRAMCS (cs_expram_l)
- );
-
- // SRAM model
- cmsdk_fpga_sram #(.AW(AWRAM8)) u_fpga_expram_l
- (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr_expram_l),
- .WDATA (wdata_expram_l),
- .WREN (wen_expram_l),
- .CS (cs_expram_l),
- // SRAM Output
- .RDATA (rdata_expram_l)
- );
-
-// instandiate expansion RAM instance to appear at 0x90000000
-
- localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
- wire [AWRAM9-3:0] addr_expram_h;
- wire [31:0] wdata_expram_h;
- wire [31:0] rdata_expram_h;
- wire [3:0] wen_expram_h;
- wire cs_expram_h;
-
- // AHB to SRAM bridge
- cmsdk_ahb_to_sram #(.AW(AWRAM9)) u_ahb_to_sram9
- (
- // AHB Inputs
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_expram_h), // AHB inputs
- .HADDR (HADDR_expram_h[AWRAM9-1:0]),
- .HTRANS (HTRANS_expram_h),
- .HSIZE (HSIZE_expram_h),
- .HWRITE (HWRITE_expram_h),
- .HWDATA (HWDATA_expram_h),
- .HREADY (HREADYMUX_expram_h),
-
- // AHB Outputs
- .HREADYOUT (HREADYOUT_expram_h), // Outputs
- .HRDATA (HRDATA_expram_h),
- .HRESP (HRESP_expram_h),
-
- // SRAM input
- .SRAMRDATA (rdata_expram_h),
- // SRAM Outputs
- .SRAMADDR (addr_expram_h),
- .SRAMWDATA (wdata_expram_h),
- .SRAMWEN (wen_expram_h),
- .SRAMCS (cs_expram_h)
- );
-
- // SRAM model
- cmsdk_fpga_sram #(.AW(AWRAM9)) u_fpga_expram_h
- (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr_expram_h),
- .WDATA (wdata_expram_h),
- .WREN (wen_expram_h),
- .CS (cs_expram_h),
- // SRAM Output
- .RDATA (rdata_expram_h)
- );
-
-// assign [31:0] HRDATA_expram_l = 32'hdead8888; // Read data bus
-// assign HREADYOUT_expram_l = 1'b1; // HREADY feedback
-// assign HRESP_expram_l = 1'b0; // Transfer response
-// assign [1:0] HRUSER_expram_l = 00; // Read-data USER signals
-//
-// assign [31:0] HRDATA_expram_h = 32'hdead9999; // Read data bus
-// assign HREADYOUT_expram_h = 1'b1; // HREADY feedback
-// assign HRESP_expram_h = 1'b0; // Transfer response
-// assign [1:0] HRUSER_expram_h = 00; // Read-data USER signals
-
-
-//----------------------------------------
-// ADP ASCII DEBUG PROTOCOL controller
-// AHB MANAGER 0
-//----------------------------------------
-
- // -------------------------------
- // ADP engine stream and control interfaces
- // -------------------------------
-
- wire comio_tx_ready;
- wire [7:0] comio_tx_data8;
- wire comio_tx_valid;
-
- wire comio_rx_ready;
- wire [7:0] comio_rx_data8;
- wire comio_rx_valid;
+ //--------------------------
+ // Clock Wiring
+ //--------------------------
- wire stdio_tx_ready;
- wire [7:0] stdio_tx_data8;
- wire stdio_tx_valid;
-
- wire stdio_rx_ready;
- wire [7:0] stdio_rx_data8;
- wire stdio_rx_valid;
-
- wire [7:0] adp_gpo8;
- wire [7:0] adp_gpi8;
-
- assign adp_gpi8 = adp_gpo8;
- assign ADPRESETREQ = adp_gpo8[0];
-
- // ADP debug controller present
- nanosoc_adp_control_v1_0 u_adp_control (
- // Clock and Reset
- .ahb_hclk (HCLK),
- .ahb_hresetn (HRESETn),
- // DMA Control
- .com_rx_tready (comio_rx_ready),
- .com_rx_tdata (comio_rx_data8),
- .com_rx_tvalid (comio_rx_valid),
- .com_tx_tready (comio_tx_ready),
- .com_tx_tdata (comio_tx_data8),
- .com_tx_tvalid (comio_tx_valid),
- .stdio_rx_tready (stdio_rx_ready),
- .stdio_rx_tdata (stdio_rx_data8),
- .stdio_rx_tvalid (stdio_rx_valid),
- .stdio_tx_tready (stdio_tx_ready),
- .stdio_tx_tdata (stdio_tx_data8),
- .stdio_tx_tvalid (stdio_tx_valid),
- .gpo8 (adp_gpo8),
- .gpi8 (adp_gpi8),
- // AHB-Lite Master Interface
- .ahb_hready (HREADY_adp),
- .ahb_hresp (HRESP_adp),
- .ahb_hrdata (HRDATA_adp),
- .ahb_htrans (HTRANS_adp),
- .ahb_hwrite (HWRITE_adp),
- .ahb_haddr (HADDR_adp),
- .ahb_hsize (HSIZE_adp),
- .ahb_hburst (HBURST_adp),
- .ahb_hmastlock (HMASTLOCK_adp),
- .ahb_hprot (HPROT_adp),
- .ahb_hwdata (HWDATA_adp)
- );
- assign HAUSER_adp [1:0] = 2'b00; // Address USER signals
- assign HWUSER_adp [1:0] = 2'b00; // Write-data USER signals
-
- nanosoc_apb_usrt u_apb_usrt_com (
- .PCLK (PCLK), // Peripheral clock
- .PCLKG (PCLKG), // Gated PCLK for bus
- .PRESETn (PRESETn), // Reset
-
- .PSEL (exp14_psel), // APB interface inputs
- .PADDR (exp_paddr[11:2]),
- .PENABLE (exp_penable),
- .PWRITE (exp_pwrite),
- .PWDATA (exp_pwdata),
-
- .PRDATA (exp14_prdata), // APB interface outputs
- .PREADY (exp14_pready),
- .PSLVERR (exp14_pslverr),
-
- .ECOREVNUM (4'h0),// Engineering-change-order revision bits
-
- .TX_VALID_o (stdio_rx_valid),
- .TX_DATA8_o (stdio_rx_data8),
- .TX_READY_i (stdio_rx_ready),
-
- .RX_VALID_i (stdio_tx_valid),
- .RX_DATA8_i (stdio_tx_data8),
- .RX_READY_o (stdio_tx_ready),
-
- .TXINT ( ), // Transmit Interrupt
- .RXINT ( ), // Receive Interrupt
- .TXOVRINT ( ), // Transmit Overrun Interrupt
- .RXOVRINT ( ), // Receive Overrun Interrupt
- .UARTINT ( ) // Combined Interrupt
- );
+ assign SYS_CLK = (SYS_TESTMODE) ? xtal_clk_i : PLL_CLK;
+ assign xtal_clk_o = SYS_XTALCLK_OUT;
- wire [7:0] ft_clkdiv = 8'd03;
-
- nanosoc_ft1248_stream_io_v1_0 #(
- .FT1248_WIDTH (1),
- .FT1248_CLKON (0)
- ) u_ftdio_com (
- .clk (HCLK),
- .resetn (HRESETn),
- .ft_clkdiv (ft_clkdiv ),
- .ft_clk_o (ft_clk_o ),
- .ft_ssn_o (ft_ssn_o ),
- .ft_miso_i (ft_miso_i ),
- .ft_miosio_o (ft_miosio_o ),
- .ft_miosio_e (ft_miosio_e ),
- .ft_miosio_z (ft_miosio_z ),
- .ft_miosio_i (ft_miosio_i ),
- .rxd_tready (comio_tx_ready),
- .rxd_tdata (comio_tx_data8),
- .rxd_tvalid (comio_tx_valid),
- .rxd_tlast (1'b0),
- .txd_tready (comio_rx_ready),
- .txd_tdata (comio_rx_data8),
- .txd_tvalid (comio_rx_valid),
- .txd_tlast ( )
- );
-
-
-//----------------------------------------
-// DIRECT MEMORY ACCESS controller
-// AHB MANAGER 1
-//----------------------------------------
-
- // DMA interface not used in this example system
- wire [DMA_CHANNEL_NUM-1:0] dma230_req; // tie off signal.
- wire [DMA_CHANNEL_NUM-1:0] dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
-
- assign dma230_req[0] = exp_drq_ip;
- assign dma230_req[1] = exp_drq_op;
-
-
- // DMA done per channel
- wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
- wire dmac_done;
- wire dmac_err;
+ //--------------------------
+ // SWD Wiring
+ //--------------------------
- ///generate if (INCLUDE_DMA != 0) begin : gen_dma
- // DMA controller present
- pl230_udma u_pl230_udma (
- // Clock and Reset
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // DMA Control
- .dma_req (dma230_req),
- .dma_sreq (dma230_req),
- .dma_waitonreq (dma230_tie0),
- .dma_stall (1'b0),
- .dma_active (),
- .dma_done (dma230_done_ch),
- .dma_err (dmac_err),
-
- // AHB-Lite Master Interface
- .hready (HREADY_dma),
- .hresp (HRESP_dma),
- .hrdata (HRDATA_dma),
- .htrans (HTRANS_dma),
- .hwrite (HWRITE_dma),
- .haddr (HADDR_dma),
- .hsize (HSIZE_dma),
- .hburst (HBURST_dma),
- .hmastlock (HMASTLOCK_dma),
- .hprot (HPROT_dma),
- .hwdata (HWDATA_dma),
-
- // APB Slave Interface
- .pclken (PCLKEN),
- .psel (exp15_psel),
- .pen (exp_penable),
- .pwrite (exp_pwrite),
- .paddr (exp_paddr[11:0]),
- .pwdata (exp_pwdata[31:0]),
- .prdata (exp15_prdata)
- );
-
- assign exp15_pready = 1'b1;
- assign exp15_pslverr = 1'b0;
- assign dmac_done = |dma230_done_ch; // OR all the DMA done together
-
-/* end else begin : gen_no_pl230_udma
- // DMA controller not present
- assign HADDR_dma [31:0] = 32'ha2a2a2a2; // Address bus
- assign HTRANS_dma [1:0] = 2'b00; // Transfer type
- assign HWRITE_dma = 1'b0; // Transfer direction
- assign HSIZE_dma [2:0] = 3'b010; // Transfer size
- assign HBURST_dma [2:0] = 3'b001; // Burst type
- assign HPROT_dma [3:0] = 4'b0010; // Protection control
- assign HWDATA_dma [31:0] = 32'hd2d2d2d2; // Write data
- assign HMASTLOCK_dma = 1'b0; // Locked Sequence
- assign HAUSER_dma [1:0] = 2'b00; // Address USER signals
- assign HWUSER_dma [1:0] = 2'b00; // Write-data USER signals
-
- assign dmac_done = 1'b0;
- assign dmac_err = 1'b0;
- assign exp15_pready = 1'b1;
- assign exp15_pslverr = 1'b0;
- assign exp15_prdata = 32'h00000000;
- assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
-
- end endgenerate
-*/
-
-//----------------------------------------
-// DIRECT MEMORY ACCESS controller 2
-// AHB MANAGER 2
-//----------------------------------------
-
- // Manager port SI2 (inputs from master 2)
- assign HADDR_dma2 [31:0] = 32'ha2a2a2a2; // Address bus
- assign HTRANS_dma2 [1:0] = 2'b00; // Transfer type
- assign HWRITE_dma2 = 1'b0; // Transfer direction
- assign HSIZE_dma2 [2:0] = 3'b010; // Transfer size
- assign HBURST_dma2 [2:0] = 3'b000; // Burst type
- assign HPROT_dma2 [3:0] = 4'b0010; // Protection control
- assign HWDATA_dma2 [31:0] = 32'hd2d2d2d2; // Write data
- assign HMASTLOCK_dma2 = 1'b0; // Locked Sequence
- assign HAUSER_dma2 [1:0] = 2'b00; // Address USER signals
- assign HWUSER_dma2 [1:0] = 2'b00; // Write-data USER signals
-
-//----------------------------------------
-// CORTEX-M0 CPU controller
-// AHB MANAGER 3
-//----------------------------------------
-
- wire SYS_NMI; // Watchdog nin-maskable interrupt
- wire [31:0] SYS_APB_IRQ; // APB subsystem IRQs
- wire [15:0] SYS_GPIO0_IRQ; // GPIO-0 IRQs
- wire [15:0] SYS_GPIO1_IRQ; // GPIO-1 IRQs
-
- wire gpio0_combintr;
- wire gpio1_combintr;
- assign gpio0_combintr = |SYS_GPIO0_IRQ[15:0];
- assign gpio1_combintr = |SYS_GPIO1_IRQ[15:0];
-
- wire intnmi_cm0;
- wire [31:0] intisr_cm0;
-
-// match interrupts to CMSDK for validation code reuse
-
- assign intnmi_cm0 = SYS_NMI;
- //assign intisr_cm0[ 5: 0] = SYS_APB_IRQ[ 5: 0];
- assign intisr_cm0[ 0] = exp_irq0;
- assign intisr_cm0[ 1] = exp_irq1;
- assign intisr_cm0[ 2] = exp_irq2;
- assign intisr_cm0[ 3] = exp_irq3;
- assign intisr_cm0[ 5: 4] = SYS_APB_IRQ[ 5: 4];
- assign intisr_cm0[ 6] = SYS_APB_IRQ[ 6] | gpio0_combintr;
- assign intisr_cm0[ 7] = SYS_APB_IRQ[ 7] | gpio1_combintr;
- assign intisr_cm0[14: 8] = SYS_APB_IRQ[14: 8];
- assign intisr_cm0[15] = SYS_APB_IRQ[15] | dmac_done | dmac_err;
- assign intisr_cm0[31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
-
- assign HAUSER_cpu [1:0] = 2'b00; // Address USER signals
- assign HWUSER_cpu [1:0] = 2'b00; // Write-data USER signals
-
-
- // Cortex-M0 integration level
- nanosoc_cpu u_nanosoc_cpu (
- .HCLK (HCLKG), //HCLK),
- .FCLK (FCLK),
- .DCLK (DCLK),
- .SCLK (SCLK),
- .HRESETn (HRESETn),
- .PORESETn (PORESETn),
- .DBGRESETn (DBGRESETn),
- .RSTBYPASS (TESTMODE),
- .DFTSE (SCANENABLE),
- // AHB port
- .HADDR (HADDR_cpu),
- .HTRANS (HTRANS_cpu),
- .HWRITE (HWRITE_cpu),
- .HSIZE (HSIZE_cpu),
- .HBURST (HBURST_cpu),
- .HPROT (HPROT_cpu),
- .HWDATA (HWDATA_cpu),
- .HMASTLOCK (HMASTLOCK_cpu),
- .HREADY (HREADY_cpu),
-// .HAUSER (HAUSER_cpu),
-// .HWUSER (HWUSER_cpu),
- .HRDATA (HRDATA_cpu),
- .HRESP (HRESP_cpu),
-// .HRUSER (HRUSER_cpu),
- // sideband signals
- .NMI (intnmi_cm0), // Non-maskable interrupt input
- .IRQ (intisr_cm0[31:0]), // Interrupt request inputs
- .TXEV (TXEV), // Event output (SEV executed)
- .RXEV (RXEV), // Event input
- // MISCELLANEOUS ---------------------
- .SLEEPING (SLEEPING),
- .SLEEPDEEP (SLEEPDEEP),
- .WAKEUP (WAKEUP ), // Wake up request from WIC
- .WICENREQ (WICENREQ ), // WIC enable request from PMU
- .WICENACK (WICENACK ), // WIC enable ack to PMU
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .CDBGPWRUPACK (CDBGPWRUPACK),
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
- .LOCKUP (LOCKUP), // Core is locked-up
- .GATEHCLK (GATEHCLK),
- .SYSRESETREQ (SYSRESETREQ), // System reset request
- .WDOGRESETREQ (WDOGRESETREQ), // Watchdog HW reset request
- .ADPRESETREQ (ADPRESETREQ), // ADP debugger reset request
-
- // Debug - JTAG or Serial wire
- // inputs
- .SWDI (SWDI),
- .SWCLK (SWCLK),
- // outputs
- .SWDO (SWDO),
- .SWDOEN (SWDOEN)
- );
-
- assign RXEV = dmac_done; // Generate event when a DMA operation completed.
-
-
-//------------------------------------
-// internal wires
-
- assign p0_out_nen = ~p0_out_en; //active low pad drive option
- assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
-
- localparam BASEADDR_GPIO0 = 32'h4001_0000;
- localparam BASEADDR_GPIO1 = 32'h4001_1000;
- localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
-
- nanosoc_sysio u_nanosoc_sysio (
- .FCLK (FCLK ), // free-running clock
- .PORESETn (PORESETn ), // Power-On-Reset (active-low)
- .TESTMODE (TESTMODE ), // Test-mode override for testability
- .HCLK (HCLK ), // AHB interconnect clock
- .HRESETn (HRESETn ), // AHB interconnect reset (active-low)
- // Common AHB signals
- .HSEL (HSEL_sysio ),
- .HADDR (HADDR_sysio ),
- .HBURST (HBURST_sysio ),
- .HMASTLOCK (HMASTLOCK_sysio),
- .HPROT (HPROT_sysio ),
- .HSIZE (HSIZE_sysio ),
- .HTRANS (HTRANS_sysio ),
- .HWDATA (HWDATA_sysio ),
- .HWRITE (HWRITE_sysio ),
- .HREADY (HREADYMUX_sysio),
- .HRDATA (HRDATA_sysio ),
- .HRESP (HRESP_sysio ),
- .HREADYOUT (HREADYOUT_sysio),
- // APB clocking
- .PCLK (PCLK ),
- .PCLKG (PCLKG ),
- .PRESETn (PRESETn ),
- .PCLKEN (PCLKEN ),
- // APB expansion select outputs
- .exp12_psel (exp12_psel ),
- .exp13_psel (exp13_psel ),
- .exp14_psel (exp14_psel ),
- .exp15_psel (exp15_psel ),
- .exp_pwdata (exp_pwdata ),
- .exp_paddr (exp_paddr ),
- .exp_pwrite (exp_pwrite ),
- .exp_penable (exp_penable ),
- // APB expansion interface inputs
- .exp12_prdata (exp12_prdata ),
- .exp12_pready (exp12_pready ),
- .exp12_pslverr (exp12_pslverr),
- .exp13_prdata (exp13_prdata ),
- .exp13_pready (exp13_pready ),
- .exp13_pslverr (exp13_pslverr),
- .exp14_prdata (exp14_prdata ),
- .exp14_pready (exp14_pready ),
- .exp14_pslverr (exp14_pslverr),
- .exp15_prdata (exp15_prdata ),
- .exp15_pready (exp15_pready ),
- .exp15_pslverr (exp15_pslverr),
- // CPU sideband signalling
- .SYS_NMI (SYS_NMI ),
- .SYS_APB_IRQ (SYS_APB_IRQ ),
- // CPU specific power/reset control
- .REMAP_CTRL (ROM_MAP ),
- .APBACTIVE (APBACTIVE ),
- .SYSRESETREQ (SYSRESETREQ ),
- .WDOGRESETREQ (WDOGRESETREQ ),
- .LOCKUP (LOCKUP ),
- .LOCKUPRESET (LOCKUPRESET ),
- .PMUENABLE (PMUENABLE ),
- // chip IO
- .SYS_GPIO0_IRQ (SYS_GPIO0_IRQ ),
- .SYS_GPIO1_IRQ (SYS_GPIO1_IRQ ),
- // IO signalling
- .uart0_rxd (uart1_txd), //(uart0_rxd ), // crossover
- .uart0_txd (uart0_txd ),
- .uart0_txen (uart0_txen ),
- .uart1_rxd (uart0_txd), //uart1_rxd ), // crossover
- .uart1_txd (uart1_txd ),
- .uart1_txen (uart1_txen ),
- .uart2_rxd (uart2_rxd ),
- .uart2_txd (uart2_txd ),
- .uart2_txen (uart2_txen ),
- .timer0_extin (timer0_extin ),
- .timer1_extin (timer1_extin ),
- // GPIO port signalling
- .p0_in (p0_in ),
- .p0_out (p0_out ),
- .p0_outen (p0_out_en ),
- .p0_altfunc (p0_altfunc ),
-
- .p1_in (p1_in ),
- .p1_out (p1_out ),
- .p1_outen (p1_out_en ),
- .p1_altfunc (p1_altfunc )
- );
-
- assign REMAP[3] = 1'b0;
- assign REMAP[2] = 1'b0;
- assign REMAP[1] = 1'b0;
- assign REMAP[0] =!ROM_MAP;
-
- assign exp12_pready = 1'b1;
- assign exp13_pready = 1'b1;
- assign exp12_pslverr = 1'b0;
- assign exp13_pslverr = 1'b0;
- assign exp12_prdata = 32'h0;
- assign exp13_prdata = 32'h0;
-
-
- // Serial wire debug is used. nTRST, TDI and TDO are not needed
-
-
-//----------------------------------------
-// I/O port pin muxing and tristate
-//----------------------------------------
-
- assign SWCLK = swdclk_i;
- assign SWDI = swdio_i;
- assign swdio_o = SWDO;
- assign swdio_e = SWDOEN;
- assign swdio_z = !SWDOEN;
-
- nanosoc_mcu_pin_mux u_pin_mux (
- // UART
- .uart0_rxd (uart0_rxd),
- .uart0_txd (uart0_txd),
- .uart0_txen (uart0_txen),
- .uart1_rxd (uart1_rxd),
- .uart1_txd (uart1_txd),
- .uart1_txen (uart1_txen),
- .uart2_rxd (uart2_rxd),
- .uart2_txd (uart2_txd),
- .uart2_txen (uart2_txen),
-
- // Timer
- .timer0_extin (timer0_extin),
- .timer1_extin (timer1_extin),
-
-
- // IO Ports
- .p0_in ( ), // was (p0_in) now from pad inputs),
- .p0_out (p0_out),
- .p0_outen (p0_out_en),
- .p0_altfunc (p0_altfunc),
-
- .p1_in ( ), // was(p1_in) now from pad inputs),
- .p1_out (p1_out),
- .p1_outen (p1_out_en),
- .p1_altfunc (p1_altfunc),
-
- // Debug
- .i_trst_n ( ),
- .i_swditms ( ), //i_swditms),
- .i_swclktck ( ), //i_swclktck),
- .i_tdi ( ),
- .i_tdo ( ),
- .i_tdoen_n ( ),
- .i_swdo ( ),
- .i_swdoen ( ),
+ assign CPU_0_SWCLK = swdclk_i;
+ assign CPU_0_SWDI = swdio_i;
+ assign swdio_o = CPU_0_SWDO;
+ assign swdio_z = !CPU_0_SWDOEN;
+
+ //--------------------------
+ // FT1248 Wiring
+ //--------------------------
+
+ assign P0_IN = p0_i;
+ assign p0_o = P0_OUT;
+ assign p0_e = P0_OUTEN;
+ assign p0_z = ~P0_OUTEN;
+
+ assign FT_MISO_I = p1_i[0]; // FT_MISO INPUT pad configuration
+ assign P1_IN_MUX[0] = p1_i[0];
+ assign p1_o[0] = 1'b0;
+ assign p1_e[0] = 1'b0;
+ assign p1_z[0] = 1'b1;
+
+ assign P1_IN_MUX[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
+ assign p1_o[1] = FT_CLK_O;
+ assign p1_e[1] = 1'b1;
+ assign p1_z[1] = 1'b0;
- // IO pads
- .p1_out_mux (p1_out_mux),
- .p1_out_en_mux (p1_out_en_mux),
- .P0 ( ), //P0),
- .P1 ( ), //P1),
+ assign FT_MIOSIO_I = p1_i[2]; // FT_MIOSIO INOUT pad configuration
+ assign P1_IN_MUX[2] = p1_i[2];
+ assign p1_o[2] = FT_MIOSIO_O;
+ assign p1_e[2] = FT_MIOSIO_E;
+ assign p1_z[2] = FT_MIOSIO_Z;
- .nTRST (nTRST), // Not needed if serial-wire debug is used
- .TDI (1'b0), // Not needed if serial-wire debug is used
- .SWDIOTMS ( ), //SWDIOTMS),
- .SWCLKTCK ( ), //SWCLKTCK),
- .TDO ( ) // Not needed if serial-wire debug is used
+ assign P1_IN_MUX[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
+ assign p1_o[3] = FT_SSN_O;
+ assign p1_e[3] = 1'b1;
+ assign p1_z[3] = 1'b0;
+ assign P1_IN_MUX[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
+ assign p1_o[15:4] = P1_OUT_MUX[15:4];
+ assign p1_e[15:4] = P1_OUT_EN_MUX[15:4];
+ assign p1_z[15:4] = ~P1_OUT_EN_MUX[15:4];
+
+ //--------------------------
+ // GPIO Interface Assignment
+ //--------------------------
+
+ assign GPI8 = GPO8;
+
+ //--------------------------
+ // System Instantiation
+ //--------------------------
+
+ nanosoc_system u_system (
+ // Free-running and Crystal Clock Output
+ .SYS_CLK(SYS_CLK),
+ .SYS_XTALCLK_OUT(SYS_XTALCLK_OUT),
+
+ // Scan Wiring
+ .SYS_SCANENABLE(SYS_SCANENABLE),
+ .SYS_TESTMODE(SYS_TESTMODE),
+ .INC_SCANINHCLK(INC_SCANINHCLK),
+ .INC_SCANOUTHCLK(INC_SCANOUTHCLK),
+
+ // Serial-Wire Debug
+ .CPU_0_SWDI(CPU_0_SWDI),
+ .CPU_0_SWCLK(CPU_0_SWCLK),
+ .CPU_0_SWDO(CPU_0_SWDO),
+ .CPU_0_SWDOEN(CPU_0_SWDOEN),
+
+ // FT1248 Interace - FT1248
+ .FT_CLK_O(FT_CLK_O),
+ .FT_SSN_O(FT_SSN_O),
+ .FT_MISO_I(FT_MISO_I),
+ .FT_MIOSIO_O(FT_MIOSIO_O),
+ .FT_MIOSIO_E(FT_MIOSIO_E),
+ .FT_MIOSIO_Z(FT_MIOSIO_Z),
+ .FT_MIOSIO_I(FT_MIOSIO_I),
+ .FT_CLKDIV(FT_CLKDIV),
+
+ // GPIO interface
+ .GPO8(GPO8),
+ .GPI8(GPI8),
+
+ // GPIO
+ .P0_IN(P0_IN),
+ .P0_OUT(P0_OUT),
+ .P0_OUTEN(P0_OUTEN),
+ .P0_ALTFUNC(P0_ALTFUNC),
+ .P1_IN(P1_IN),
+ .P1_OUT(P1_OUT),
+ .P1_OUTEN(P1_OUTEN),
+ .P1_ALTFUNC(P1_ALTFUNC)
);
-endmodule
-
-
-
+endmodule
\ No newline at end of file
diff --git a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 2386fc1..5b8b683 100644
--- a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -120,7 +120,9 @@ module nanosoc_ss_systemctrl #(
input wire [15:0] P1_IN, // GPIO 1 inputs
output wire [15:0] P1_OUT, // GPIO 1 outputs
output wire [15:0] P1_OUTEN, // GPIO 1 output enables
- output wire [15:0] P1_ALTFUNC // GPIO 1 alternate function (pin mux)
+ output wire [15:0] P1_ALTFUNC, // GPIO 1 alternate function (pin mux)
+ output wire [15:0] P1_OUT_MUX, // GPIO 1 aOutput Port Drive
+ output wire [15:0] P1_OUT_EN_MUX // Active High output drive enable (pad tech dependent)
);
// -------------------------------
// Internal Wiring
diff --git a/system/nanosoc_system/verilog/nanosoc_system.v b/system/nanosoc_system/verilog/nanosoc_system.v
index 977e359..d083b9f 100644
--- a/system/nanosoc_system/verilog/nanosoc_system.v
+++ b/system/nanosoc_system/verilog/nanosoc_system.v
@@ -92,7 +92,19 @@ module nanosoc_system #(
// GPIO interface
output wire [7:0] GPO8,
- input wire [7:0] GPI8
+ input wire [7:0] GPI8,
+
+ // GPIO
+ input wire [15:0] P0_IN, // GPIO 0 inputs
+ output wire [15:0] P0_OUT, // GPIO 0 outputs
+ output wire [15:0] P0_OUTEN, // GPIO 0 output enables
+ output wire [15:0] P0_ALTFUNC, // GPIO 0 alternate function (pin mux)
+ input wire [15:0] P1_IN, // GPIO 1 inputs
+ output wire [15:0] P1_OUT, // GPIO 1 outputs
+ output wire [15:0] P1_OUTEN, // GPIO 1 output enables
+ output wire [15:0] P1_ALTFUNC, // GPIO 1 alternate function (pin mux)
+ output wire [15:0] P1_OUT_MUX, // GPIO 1 aOutput Port Drive
+ output wire [15:0] P1_OUT_EN_MUX // Active High output drive enable (pad tech dependent)
);
//--------------------------
// Local Parameters
@@ -757,16 +769,6 @@ module nanosoc_system #(
// Lockup Signals - To System
wire SYS_WDOGRESETREQ; // Watchdog reset request
wire SYS_LOCKUPRESET; // System Controller cfg - Reset if lockup
-
- // GPIO - To Chip Level
- wire [15:0] P0_IN; // GPIO 0 inputs
- wire [15:0] P0_OUT; // GPIO 0 outputs
- wire [15:0] P0_OUTEN; // GPIO 0 enables
- wire [15:0] P0_ALTFUNC; // GPIO 0 alternate function (pin mux)
- wire [15:0] P1_IN; // GPIO 1 inputs
- wire [15:0] P1_OUT; // GPIO 1 outputs
- wire [15:0] P1_OUTEN; // GPIO 1 enables
- wire [15:0] P1_ALTFUNC; // GPIO 1 alternate function (pin mux)
// Interrupt Wiring
//--------------------------
--
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