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Commit a5dfe47e authored by dam1n19's avatar dam1n19
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Reworked DMA subsystem to use Defines

parent c28a7ab9
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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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flist/nanosoc.flist
+ 0
− 3
View file @ a5dfe47e
......@@ -31,6 +31,3 @@
// DMAC IP
-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
// DMA Subystem
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
flist/nanosoc_ip.flist
+ 1
− 0
View file @ a5dfe47e
......@@ -32,6 +32,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
// Bus Matrix
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix_ip.flist
......
fpga/makefile
+ 4
− 1
View file @ a5dfe47e
......@@ -76,6 +76,8 @@ endif
# Defines to pass to filelist compile
NANOSOC_DEFINES += $(ACCELERATOR_SUBSYSTEM)
NANOSOC_DEFINES += DMAC_0_PL230
# Compile Testcodes and Bootrom
code:
......@@ -83,7 +85,8 @@ code:
@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) bootrom
defs_nanosoc:
@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) defs_gen DEFINES_DIR=$(DEFINES_DIR) NANOSOC_DEFINES=$(NANOSOC_DEFINES) DEFINES_FILE=$(DEFINES_FILE)
@mkdir -p $(DEFINES_DIR)
@$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
# Generate TCL filelist from flists
flist_nanosoc: defs_nanosoc
......
makefile
+ 1
− 0
View file @ a5dfe47e
......@@ -95,6 +95,7 @@ ifeq ($(ACCELERATOR),yes)
NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
endif
NANOSOC_DEFINES += DMAC_0_PL230
NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
# Is the Arm QuickStart being used?
......
nanosoc/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v deleted 100644 → 0
+ 0
− 119
View file @ c28a7ab9
//-----------------------------------------------------------------------------
// NanoSoC DMA Subsystem - Contains DMA Controllers
// - Version with no DMA Controllers connected
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_ss_dma #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter DMAC_0_CFG_ADDR_W = 12, // DMAC 0 Configuration Port Address Width
parameter DMAC_1_CFG_ADDR_W = 12, // DMAC 1 Configuration Port Address Width
parameter DMAC_0_CHANNEL_NUM = 2, // DMAC 0 Number of DMA Channels
parameter DMAC_1_CHANNEL_NUM = 2 // DMAC 1 Number of DMA Channels
)(
// System AHB Clocks and Resets
input wire SYS_HCLK,
input wire SYS_HRESETn,
input wire SYS_PCLKEN, // APB clock enable
// DMAC 0 AHB Lite Port
output wire [SYS_ADDR_W-1:0] DMAC_0_HADDR, // Address bus
output wire [1:0] DMAC_0_HTRANS, // Transfer type
output wire DMAC_0_HWRITE, // Transfer direction
output wire [2:0] DMAC_0_HSIZE, // Transfer size
output wire [2:0] DMAC_0_HBURST, // Burst type
output wire [3:0] DMAC_0_HPROT, // Protection control
output wire [SYS_DATA_W-1:0] DMAC_0_HWDATA, // Write data
output wire DMAC_0_HMASTLOCK, // Locked Sequence
input wire [SYS_DATA_W-1:0] DMAC_0_HRDATA, // Read data bus
input wire DMAC_0_HREADY, // HREADY feedback
input wire DMAC_0_HRESP, // Transfer response
// DMAC 0 APB Configurtation Port
input wire DMAC_0_PSEL, // APB peripheral select
input wire DMAC_0_PEN, // APB transfer enable
input wire DMAC_0_PWRITE, // APB transfer direction
input wire [DMAC_0_CFG_ADDR_W-1:0] DMAC_0_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_0_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_0_PRDATA, // APB read data
// DMAC 0 DMA Request and Status Port
input wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_REQ, // DMA transfer request
output wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_DONE, // DMA transfer done
output wire DMAC_0_DMA_ERR, // DMA slave response not OK
// DMAC 1 AHB Lite Port
output wire [SYS_ADDR_W-1:0] DMAC_1_HADDR, // Address bus
output wire [1:0] DMAC_1_HTRANS, // Transfer type
output wire DMAC_1_HWRITE, // Transfer direction
output wire [2:0] DMAC_1_HSIZE, // Transfer size
output wire [2:0] DMAC_1_HBURST, // Burst type
output wire [3:0] DMAC_1_HPROT, // Protection control
output wire [SYS_DATA_W-1:0] DMAC_1_HWDATA, // Write data
output wire DMAC_1_HMASTLOCK, // Locked Sequence
input wire [SYS_DATA_W-1:0] DMAC_1_HRDATA, // Read data bus
input wire DMAC_1_HREADY, // HREADY feedback
input wire DMAC_1_HRESP, // Transfer response
// DMAC 1 APB Configurtation Port
input wire DMAC_1_PSEL, // APB peripheral select
input wire DMAC_1_PEN, // APB transfer enable
input wire DMAC_1_PWRITE, // APB transfer direction
input wire [DMAC_1_CFG_ADDR_W-1:0] DMAC_1_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_1_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_1_PRDATA, // APB read data
// DMAC 1 DMA Request and Status Port
input wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ, // DMA transfer request
output wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_DONE, // DMA transfer done
output wire DMAC_1_DMA_ERR // DMA slave response not OK
);
// -------------------------------
// DMA Controller 0 Instantiation - Not implemented
// -------------------------------
// AHB Tie-off signals
assign DMAC_0_HADDR = 32'd0;
assign DMAC_0_HTRANS = 2'd0;
assign DMAC_0_HWRITE = 1'd0;
assign DMAC_0_HSIZE = 3'd0;
assign DMAC_0_HBURST = 3'd0;
assign DMAC_0_HPROT = 4'd0;
assign DMAC_0_HWDATA = 32'd0;
assign DMAC_0_HMASTLOCK = 1'd0;
// APB Tie-off signals
assign DMAC_0_PRDATA = 32'd0;
// DMA Status Tie-off signals
assign DMAC_0_DMA_DONE = {DMAC_0_CHANNEL_NUM{1'b0}};
assign DMAC_0_DMA_ERR = 1'b0;
// -------------------------------
// DMA Controller 1 Instantiation - Not implemented
// -------------------------------
// AHB Tie-off signals
assign DMAC_1_HADDR = 32'd0;
assign DMAC_1_HTRANS = 2'd0;
assign DMAC_1_HWRITE = 1'd0;
assign DMAC_1_HSIZE = 3'd0;
assign DMAC_1_HBURST = 3'd0;
assign DMAC_1_HPROT = 4'd0;
assign DMAC_1_HWDATA = 32'd0;
assign DMAC_1_HMASTLOCK = 1'd0;
// APB Tie-off signals
assign DMAC_1_PRDATA = 32'd0;
// DMA Status Tie-off signals
assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}};
assign DMAC_1_DMA_ERR = 1'b0;
endmodule
\ No newline at end of file
nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v → nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+ 70
− 5
View file @ a5dfe47e
......@@ -80,6 +80,7 @@ module nanosoc_ss_dma #(
output wire DMAC_1_DMA_ERR // DMA slave response not OK
);
`ifdef DMAC_0_PL230
// -------------------------------
// DMA Controller 0 Instantiation
// -------------------------------
......@@ -125,10 +126,77 @@ module nanosoc_ss_dma #(
//--------------------------
assign DMAC_0_PREADY = 1'b1;
assign DMAC_0_PSLVERR = 1'b0;
`else
// -------------------------------
// DMA Controller 0 Instantiation - Not implemented
// -------------------------------
// AHB Tie-off signals
assign DMAC_0_HADDR = 32'd0;
assign DMAC_0_HTRANS = 2'd0;
assign DMAC_0_HWRITE = 1'd0;
assign DMAC_0_HSIZE = 3'd0;
assign DMAC_0_HBURST = 3'd0;
assign DMAC_0_HPROT = 4'd0;
assign DMAC_0_HWDATA = 32'd0;
assign DMAC_0_HMASTLOCK = 1'd0;
// APB Tie-off signals
assign DMAC_0_PRDATA = 32'd0;
// DMA Status Tie-off signals
assign DMAC_0_DMA_DONE = {DMAC_0_CHANNEL_NUM{1'b0}};
assign DMAC_0_DMA_ERR = 1'b0;
`endif
`ifdef DMAC_1_PL230
// -------------------------------
// DMA Controller 1 Instantiation - Not implemented
// DMA Controller 0 Instantiation
// -------------------------------
sldma230 #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W),
.CFG_ADDR_W (DMAC_1_CFG_ADDR_W),
.CHANNEL_NUM (DMAC_1_CHANNEL_NUM)
) u_dmac_0 (
// AHB Clocks and Resets
.HCLK(SYS_HCLK),
.HRESETn(SYS_HRESETn),
// AHB Lite Port
.HADDR(DMAC_1_HADDR),
.HTRANS(DMAC_1_HTRANS),
.HWRITE(DMAC_1_HWRITE),
.HSIZE(DMAC_1_HSIZE),
.HBURST(DMAC_1_HBURST),
.HPROT(DMAC_1_HPROT),
.HWDATA(DMAC_1_HWDATA),
.HMASTLOCK(DMAC_1_HMASTLOCK),
.HRDATA(DMAC_1_HRDATA),
.HREADY(DMAC_1_HREADY),
.HRESP(DMAC_1_HRESP),
// APB Configuration Port
.PCLKEN(SYS_PCLKEN),
.PSEL(DMAC_1_PSEL),
.PEN(DMAC_1_PEN),
.PWRITE(DMAC_1_PWRITE),
.PADDR(DMAC_1_PADDR),
.PWDATA(DMAC_1_PWDATA),
.PRDATA(DMAC_1_PRDATA),
// DMA Request and Status Port
.DMA_REQ(DMAC_1_DMA_REQ),
.DMA_DONE(DMAC_1_DMA_DONE),
.DMA_ERR(DMAC_1_DMA_ERR)
);
// APB Assignments
//--------------------------
assign DMAC_1_PREADY = 1'b1;
assign DMAC_1_PSLVERR = 1'b0;
`else
// -------------------------------
// DMA Controller 0 Instantiation - Not implemented
// -------------------------------
// AHB Tie-off signals
assign DMAC_1_HADDR = 32'd0;
......@@ -142,13 +210,10 @@ module nanosoc_ss_dma #(
// APB Tie-off signals
assign DMAC_1_PRDATA = 32'd0;
assign DMAC_1_PREADY = 1'b1;
assign DMAC_1_PSLVERR = 1'b1;
// DMA Status Tie-off signals
assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}};
assign DMAC_1_DMA_ERR = 1'b0;
`endif
endmodule
\ No newline at end of file
socdebug_tech @ a29b9668
Compare 04639f9c...a29b9668
Subproject commit 04639f9ccf3717e38e741dadd5027453f6856a37
Subproject commit a29b96684da03df7701d8bf7fa3db1c13d171756
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