diff --git a/flist/nanosoc.flist b/flist/nanosoc.flist
index 8d57eecac9ba47f4582c7515190bd13dba5273aa..c54ebc1c8defb6a6fb44bb9eea4585c10f4fbd3b 100644
--- a/flist/nanosoc.flist
+++ b/flist/nanosoc.flist
@@ -31,6 +31,3 @@
// DMAC IP
-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
-
-// DMA Subystem
-$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
diff --git a/flist/nanosoc_ip.flist b/flist/nanosoc_ip.flist
index 76f4dd7b8b9c1a06349a8d35565f90554be648ab..ea78c8ca5db2f8d9f5fdb1dd21b83be9cddd1bd8 100644
--- a/flist/nanosoc_ip.flist
+++ b/flist/nanosoc_ip.flist
@@ -32,6 +32,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
// Bus Matrix
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix_ip.flist
diff --git a/fpga/makefile b/fpga/makefile
index 62ea7d8060c419ebb7625921019b44dca8cad641..71be7bce379cfb2c1382ca3d57857c4267510ce8 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -76,6 +76,8 @@ endif
# Defines to pass to filelist compile
NANOSOC_DEFINES += $(ACCELERATOR_SUBSYSTEM)
+NANOSOC_DEFINES += DMAC_0_PL230
+
# Compile Testcodes and Bootrom
code:
@@ -83,7 +85,8 @@ code:
@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) bootrom
defs_nanosoc:
- @$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) defs_gen DEFINES_DIR=$(DEFINES_DIR) NANOSOC_DEFINES=$(NANOSOC_DEFINES) DEFINES_FILE=$(DEFINES_FILE)
+ @mkdir -p $(DEFINES_DIR)
+ @$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
# Generate TCL filelist from flists
flist_nanosoc: defs_nanosoc
diff --git a/makefile b/makefile
index bd508e2e9fdc30cb4bfc20165035673900c3e37f..01e18b565729db619f3054470af80c0fbf29012d 100644
--- a/makefile
+++ b/makefile
@@ -95,6 +95,7 @@ ifeq ($(ACCELERATOR),yes)
NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
endif
+NANOSOC_DEFINES += DMAC_0_PL230
NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
# Is the Arm QuickStart being used?
diff --git a/nanosoc/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v
deleted file mode 100644
index 135db1b98dd3e16b2ce15ff10d282710c0deffc0..0000000000000000000000000000000000000000
--- a/nanosoc/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v
+++ /dev/null
@@ -1,119 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC DMA Subsystem - Contains DMA Controllers
-// - Version with no DMA Controllers connected
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module nanosoc_ss_dma #(
- parameter SYS_ADDR_W = 32, // System Address Width
- parameter SYS_DATA_W = 32, // System Data Width
- parameter DMAC_0_CFG_ADDR_W = 12, // DMAC 0 Configuration Port Address Width
- parameter DMAC_1_CFG_ADDR_W = 12, // DMAC 1 Configuration Port Address Width
- parameter DMAC_0_CHANNEL_NUM = 2, // DMAC 0 Number of DMA Channels
- parameter DMAC_1_CHANNEL_NUM = 2 // DMAC 1 Number of DMA Channels
-)(
- // System AHB Clocks and Resets
- input wire SYS_HCLK,
- input wire SYS_HRESETn,
- input wire SYS_PCLKEN, // APB clock enable
-
- // DMAC 0 AHB Lite Port
- output wire [SYS_ADDR_W-1:0] DMAC_0_HADDR, // Address bus
- output wire [1:0] DMAC_0_HTRANS, // Transfer type
- output wire DMAC_0_HWRITE, // Transfer direction
- output wire [2:0] DMAC_0_HSIZE, // Transfer size
- output wire [2:0] DMAC_0_HBURST, // Burst type
- output wire [3:0] DMAC_0_HPROT, // Protection control
- output wire [SYS_DATA_W-1:0] DMAC_0_HWDATA, // Write data
- output wire DMAC_0_HMASTLOCK, // Locked Sequence
- input wire [SYS_DATA_W-1:0] DMAC_0_HRDATA, // Read data bus
- input wire DMAC_0_HREADY, // HREADY feedback
- input wire DMAC_0_HRESP, // Transfer response
-
- // DMAC 0 APB Configurtation Port
- input wire DMAC_0_PSEL, // APB peripheral select
- input wire DMAC_0_PEN, // APB transfer enable
- input wire DMAC_0_PWRITE, // APB transfer direction
- input wire [DMAC_0_CFG_ADDR_W-1:0] DMAC_0_PADDR, // APB address
- input wire [SYS_DATA_W-1:0] DMAC_0_PWDATA, // APB write data
- output wire [SYS_DATA_W-1:0] DMAC_0_PRDATA, // APB read data
-
- // DMAC 0 DMA Request and Status Port
- input wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_REQ, // DMA transfer request
- output wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_DONE, // DMA transfer done
- output wire DMAC_0_DMA_ERR, // DMA slave response not OK
-
- // DMAC 1 AHB Lite Port
- output wire [SYS_ADDR_W-1:0] DMAC_1_HADDR, // Address bus
- output wire [1:0] DMAC_1_HTRANS, // Transfer type
- output wire DMAC_1_HWRITE, // Transfer direction
- output wire [2:0] DMAC_1_HSIZE, // Transfer size
- output wire [2:0] DMAC_1_HBURST, // Burst type
- output wire [3:0] DMAC_1_HPROT, // Protection control
- output wire [SYS_DATA_W-1:0] DMAC_1_HWDATA, // Write data
- output wire DMAC_1_HMASTLOCK, // Locked Sequence
- input wire [SYS_DATA_W-1:0] DMAC_1_HRDATA, // Read data bus
- input wire DMAC_1_HREADY, // HREADY feedback
- input wire DMAC_1_HRESP, // Transfer response
-
- // DMAC 1 APB Configurtation Port
- input wire DMAC_1_PSEL, // APB peripheral select
- input wire DMAC_1_PEN, // APB transfer enable
- input wire DMAC_1_PWRITE, // APB transfer direction
- input wire [DMAC_1_CFG_ADDR_W-1:0] DMAC_1_PADDR, // APB address
- input wire [SYS_DATA_W-1:0] DMAC_1_PWDATA, // APB write data
- output wire [SYS_DATA_W-1:0] DMAC_1_PRDATA, // APB read data
-
- // DMAC 1 DMA Request and Status Port
- input wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ, // DMA transfer request
- output wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_DONE, // DMA transfer done
- output wire DMAC_1_DMA_ERR // DMA slave response not OK
-);
-
- // -------------------------------
- // DMA Controller 0 Instantiation - Not implemented
- // -------------------------------
- // AHB Tie-off signals
- assign DMAC_0_HADDR = 32'd0;
- assign DMAC_0_HTRANS = 2'd0;
- assign DMAC_0_HWRITE = 1'd0;
- assign DMAC_0_HSIZE = 3'd0;
- assign DMAC_0_HBURST = 3'd0;
- assign DMAC_0_HPROT = 4'd0;
- assign DMAC_0_HWDATA = 32'd0;
- assign DMAC_0_HMASTLOCK = 1'd0;
-
- // APB Tie-off signals
- assign DMAC_0_PRDATA = 32'd0;
-
- // DMA Status Tie-off signals
- assign DMAC_0_DMA_DONE = {DMAC_0_CHANNEL_NUM{1'b0}};
- assign DMAC_0_DMA_ERR = 1'b0;
-
- // -------------------------------
- // DMA Controller 1 Instantiation - Not implemented
- // -------------------------------
- // AHB Tie-off signals
- assign DMAC_1_HADDR = 32'd0;
- assign DMAC_1_HTRANS = 2'd0;
- assign DMAC_1_HWRITE = 1'd0;
- assign DMAC_1_HSIZE = 3'd0;
- assign DMAC_1_HBURST = 3'd0;
- assign DMAC_1_HPROT = 4'd0;
- assign DMAC_1_HWDATA = 32'd0;
- assign DMAC_1_HMASTLOCK = 1'd0;
-
- // APB Tie-off signals
- assign DMAC_1_PRDATA = 32'd0;
-
- // DMA Status Tie-off signals
- assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}};
- assign DMAC_1_DMA_ERR = 1'b0;
-
-endmodule
\ No newline at end of file
diff --git a/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
similarity index 77%
rename from nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
rename to nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
index 3102dc43475ab75cefa99bff7c6ae0ab77f9604a..7c4df12b0616a132ea4affe1cc44592292883994 100644
--- a/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
+++ b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
@@ -80,6 +80,7 @@ module nanosoc_ss_dma #(
output wire DMAC_1_DMA_ERR // DMA slave response not OK
);
+`ifdef DMAC_0_PL230
// -------------------------------
// DMA Controller 0 Instantiation
// -------------------------------
@@ -125,10 +126,77 @@ module nanosoc_ss_dma #(
//--------------------------
assign DMAC_0_PREADY = 1'b1;
assign DMAC_0_PSLVERR = 1'b0;
+`else
+ // -------------------------------
+ // DMA Controller 0 Instantiation - Not implemented
+ // -------------------------------
+ // AHB Tie-off signals
+ assign DMAC_0_HADDR = 32'd0;
+ assign DMAC_0_HTRANS = 2'd0;
+ assign DMAC_0_HWRITE = 1'd0;
+ assign DMAC_0_HSIZE = 3'd0;
+ assign DMAC_0_HBURST = 3'd0;
+ assign DMAC_0_HPROT = 4'd0;
+ assign DMAC_0_HWDATA = 32'd0;
+ assign DMAC_0_HMASTLOCK = 1'd0;
+ // APB Tie-off signals
+ assign DMAC_0_PRDATA = 32'd0;
+ // DMA Status Tie-off signals
+ assign DMAC_0_DMA_DONE = {DMAC_0_CHANNEL_NUM{1'b0}};
+ assign DMAC_0_DMA_ERR = 1'b0;
+`endif
+
+`ifdef DMAC_1_PL230
// -------------------------------
- // DMA Controller 1 Instantiation - Not implemented
+ // DMA Controller 0 Instantiation
+ // -------------------------------
+ sldma230 #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
+ .CFG_ADDR_W (DMAC_1_CFG_ADDR_W),
+ .CHANNEL_NUM (DMAC_1_CHANNEL_NUM)
+ ) u_dmac_0 (
+ // AHB Clocks and Resets
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
+
+ // AHB Lite Port
+ .HADDR(DMAC_1_HADDR),
+ .HTRANS(DMAC_1_HTRANS),
+ .HWRITE(DMAC_1_HWRITE),
+ .HSIZE(DMAC_1_HSIZE),
+ .HBURST(DMAC_1_HBURST),
+ .HPROT(DMAC_1_HPROT),
+ .HWDATA(DMAC_1_HWDATA),
+ .HMASTLOCK(DMAC_1_HMASTLOCK),
+ .HRDATA(DMAC_1_HRDATA),
+ .HREADY(DMAC_1_HREADY),
+ .HRESP(DMAC_1_HRESP),
+
+ // APB Configuration Port
+ .PCLKEN(SYS_PCLKEN),
+ .PSEL(DMAC_1_PSEL),
+ .PEN(DMAC_1_PEN),
+ .PWRITE(DMAC_1_PWRITE),
+ .PADDR(DMAC_1_PADDR),
+ .PWDATA(DMAC_1_PWDATA),
+ .PRDATA(DMAC_1_PRDATA),
+
+ // DMA Request and Status Port
+ .DMA_REQ(DMAC_1_DMA_REQ),
+ .DMA_DONE(DMAC_1_DMA_DONE),
+ .DMA_ERR(DMAC_1_DMA_ERR)
+ );
+
+ // APB Assignments
+ //--------------------------
+ assign DMAC_1_PREADY = 1'b1;
+ assign DMAC_1_PSLVERR = 1'b0;
+`else
+ // -------------------------------
+ // DMA Controller 0 Instantiation - Not implemented
// -------------------------------
// AHB Tie-off signals
assign DMAC_1_HADDR = 32'd0;
@@ -142,13 +210,10 @@ module nanosoc_ss_dma #(
// APB Tie-off signals
assign DMAC_1_PRDATA = 32'd0;
- assign DMAC_1_PREADY = 1'b1;
- assign DMAC_1_PSLVERR = 1'b1;
// DMA Status Tie-off signals
assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}};
assign DMAC_1_DMA_ERR = 1'b0;
-
-
+`endif
endmodule
\ No newline at end of file
diff --git a/nanosoc/socdebug_tech b/nanosoc/socdebug_tech
index 04639f9ccf3717e38e741dadd5027453f6856a37..a29b96684da03df7701d8bf7fa3db1c13d171756 160000
--- a/nanosoc/socdebug_tech
+++ b/nanosoc/socdebug_tech
@@ -1 +1 @@
-Subproject commit 04639f9ccf3717e38e741dadd5027453f6856a37
+Subproject commit a29b96684da03df7701d8bf7fa3db1c13d171756