Linted DMA Subsystem

hal/nanosoc_ip.waive

@@ -40,6 +40,17 @@ lint_checking designunit = nanosoc_ss_cpu
     USEPRT {"HBURST|HMASTLOCK"} off;
 }
 
+lint_checking designunit = nanosoc_ss_dma
+{    
+    // Not Top-level in design_info
+    ATLGLC off;
+    TPOUNR off;
+    
+    // DMAC 1 Currently tied off
+    TIELOG {"DMAC_1"} off;
+    USEPRT {"DMAC_1"} off;
+}
+
 lint_checking designunit = nanosoc_region_bootrom_0
 {   
     // Some Bits of AHB Signals not Used

system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v

@@ -120,20 +120,20 @@ module nanosoc_ss_dma #(
     // DMA Controller 1 Instantiation - Not implemented
     // -------------------------------
     // AHB Tie-off signals
-    assign DMAC_1_HADDR     = 32'b0;
-    assign DMAC_1_HTRANS    = 2'b0;
-    assign DMAC_1_HWRITE    = 1'b0;
-    assign DMAC_1_HSIZE     = 3'b0;
-    assign DMAC_1_HBURST    = 3'b0;
-    assign DMAC_1_HPROT     = 4'b0;
-    assign DMAC_1_HWDATA    = 32'b0;
-    assign DMAC_1_HMASTLOCK = 1'b0;
+    assign DMAC_1_HADDR     = 32'd0;
+    assign DMAC_1_HTRANS    = 2'd0;
+    assign DMAC_1_HWRITE    = 1'd0;
+    assign DMAC_1_HSIZE     = 3'd0;
+    assign DMAC_1_HBURST    = 3'd0;
+    assign DMAC_1_HPROT     = 4'd0;
+    assign DMAC_1_HWDATA    = 32'd0;
+    assign DMAC_1_HMASTLOCK = 1'd0;
     
     // APB Tie-off signals
-    assign DMAC_1_PRDATA    = 32'b0;
+    assign DMAC_1_PRDATA    = 32'd0;
     
     // DMA Status Tie-off signals
-    assign DMAC_1_DMA_DONE  = 0;
-    assign DMAC_1_DMA_ERR   = 0;
+    assign DMAC_1_DMA_DONE  = {DMAC_1_CHANNEL_NUM{1'b0}};
+    assign DMAC_1_DMA_ERR   = 1'b0;
     
 endmodule
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