diff --git a/hal/nanosoc_ip.waive b/hal/nanosoc_ip.waive index 8050d6e427b68a4aaa204d744c95234b6d419acf..c37b45ecc761e934413136d6b42efa87dcb49a56 100644 --- a/hal/nanosoc_ip.waive +++ b/hal/nanosoc_ip.waive @@ -40,6 +40,17 @@ lint_checking designunit = nanosoc_ss_cpu USEPRT {"HBURST|HMASTLOCK"} off; } +lint_checking designunit = nanosoc_ss_dma +{ + // Not Top-level in design_info + ATLGLC off; + TPOUNR off; + + // DMAC 1 Currently tied off + TIELOG {"DMAC_1"} off; + USEPRT {"DMAC_1"} off; +} + lint_checking designunit = nanosoc_region_bootrom_0 { // Some Bits of AHB Signals not Used diff --git a/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v b/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v index ae3e12e457d663d398d4b20c83a7b9c7982c5f58..581c7a95b9c3504e72f2c5ef090ce21b8bff0468 100644 --- a/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v +++ b/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v @@ -120,20 +120,20 @@ module nanosoc_ss_dma #( // DMA Controller 1 Instantiation - Not implemented // ------------------------------- // AHB Tie-off signals - assign DMAC_1_HADDR = 32'b0; - assign DMAC_1_HTRANS = 2'b0; - assign DMAC_1_HWRITE = 1'b0; - assign DMAC_1_HSIZE = 3'b0; - assign DMAC_1_HBURST = 3'b0; - assign DMAC_1_HPROT = 4'b0; - assign DMAC_1_HWDATA = 32'b0; - assign DMAC_1_HMASTLOCK = 1'b0; + assign DMAC_1_HADDR = 32'd0; + assign DMAC_1_HTRANS = 2'd0; + assign DMAC_1_HWRITE = 1'd0; + assign DMAC_1_HSIZE = 3'd0; + assign DMAC_1_HBURST = 3'd0; + assign DMAC_1_HPROT = 4'd0; + assign DMAC_1_HWDATA = 32'd0; + assign DMAC_1_HMASTLOCK = 1'd0; // APB Tie-off signals - assign DMAC_1_PRDATA = 32'b0; + assign DMAC_1_PRDATA = 32'd0; // DMA Status Tie-off signals - assign DMAC_1_DMA_DONE = 0; - assign DMAC_1_DMA_ERR = 0; + assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}}; + assign DMAC_1_DMA_ERR = 1'b0; endmodule \ No newline at end of file