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Commit 9ce3a8ea authored by Daniel Newbrook's avatar Daniel Newbrook
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Update 140525 TSMC 28nm backend, still work in progress

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......@@ -53,6 +53,10 @@ ASIC/*/*/Synopsys_FC/reports
ASIC/*/*/Synopsys_FC/logs
ASIC/*/*/Synopsys_FC/work
ASIC/*/*/Cadence/outputs
ASIC/*/*/Cadence/reports
ASIC/*/*/Cadence/logs
ASIC/Synopsys/Formality/FM_INFO/*
ASIC/Synopsys/ICC2/CLIBs
ASIC/Synopsys/ICC2/PreFrameCheck
......
set_cpf_version 1.1
set_design nanosoc_chip_pads
create_power_domain -name TOP -default
create_power_domain -name ACCEL -instances u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator
create_nominal_condition -name nom -voltage 1.08
create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
create_ground_nets -nets VSS
create_power_nets -nets VDD
create_power_nets -nets VDDACC
create_global_connection -net VSS -pins VSS
create_global_connection -net VDD -pins VDD
create_global_connection -net VDDACC -pins VDDACC
update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
end_design
\ No newline at end of file
LIBS_DIR:=./libs
REPORT_DIR:=./reports
LOG_DIR:=./logs
WORK_DIR:=./work
make_directories:
mkdir -p $(LIBS_DIR)
mkdir -p $(REPORT_DIR)
mkdir -p $(LOG_DIR)
mkdir -p $(WORK_DIR)
syn_genus:
cd $(WORK_DIR); genus -f ../scripts/genus.tcl;
syn_genus_nodft:
cd $(WORK_DIR); genus -f ../scripts/genus_nodft.tcl;
innovus_full:
cd $(WORK_DIR); innovus -f ../scripts/pnr_flow.tcl;
all: generate_libs syn_genus innovus_full
############################################
# Script : Clock Tree Implementation
# Date : 24th May 2023
# Author : Srimanth Tenneti
# Description : Implements the Clock Tree
############################################
### Buffer Cells
set_db cts_buffer_cells {*BUFH*}
### Inverter Cells
set_db cts_inverter_cells {*INV*}
### Clock Tree Sepc
#create_clock_tree_spec -out_file design_clk.spec
### Creating a Clock Tree
ccopt_design
### Optimizing the design
optDesign -postCts
optDesign -postCts -hold
#########################################
# File : Design Import Logic
# Date : 22nd May 2022
# Author : Srimanth Tenneti
# Description : MMMC + Design Import
#########################################
### Settting PG Nets
set_db init_power_nets {VDD VDDIO VDDACC}
set_db init_ground_nets {VSS VSSIO}
### Processing MMMC
read_mmmc nanosoc.mmmc
# Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set TECH_LEF /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PRTF_EDI_N65_9M_6X1Z1U_RDL.24a.tlef
#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
set BASE_RVT_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_hvt/r0p0/lef/sc12_cln65lp_base_hvt.lef
set PMK_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_pmk_rvt_hvt/r0p0/lef/sc12_cln65lp_pmk_rvt_hvt.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/iolib/tpbn65v_200b_FE/TSMCHOME/digital/Back_End/lef/tpbn65v_200b/cup/9m/9M_6X1Z1U/lef/tpbn65v_9lm.lef
set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Back_End/lef/tpdn65lpnv2od3_140b/mt_2/9lm/lef/tpdn65lpnv2od3_9lm.lef
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
set RF_08K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
### Reading LEFs
read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${BASE_RVT_LEF} ${PMK_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${RF_08K_LEF} ${ROM_LEF}]
### Reading Netlist
read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v
### Read DEF scan chain
#read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
### Initializing the Design
init_design
### Adjusting the GUI
gui_fit
#ungroup u_nanosoc_chip_u_system
create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 2000.0 2500.0 140.0 140.0 140.0 140.0
read_power_intent -cpf ../cpf/nanosoc_syn_out.cpf
#########################################
# File : Design Import Logic
# Date : 22nd May 2022
# Author : Srimanth Tenneti
# Description : MMMC + Design Import
#########################################
### Settting PG Nets
set init_pwr_net {VDD VDDIO VDDACC}
set init_gnd_net {VSS VSSIO}
### Processing MMMC
set init_mmmc_file {../scripts/nanosoc.mmmc}
# Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set TECH_LEF $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.lef
#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set BASE_LEF $standard_cell_base_path/lef/sc12mcpp140z_cln28ht_base_svt_c35.lef
set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
set IO_PAD_DRIVER_LEF $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/9lm/lef/tphn28hpcpgv18_9lm.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
set SRAM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/sram_16k/sram_16k.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
### Reading LEFs
set init_lef_file [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${SRAM_LEF} ${ROM_LEF}]
### Reading Netlist
set init_top_cell {nanosoc_chip_pads}
set init_verilog {../outputs/nanosoc_chip_pads_44pin.v}
set init_cpf_file {../outputs/nanosoc_syn_out.cpf}
### Initializing the Design
init_design
#ungroup u_nanosoc_chip_u_system
floorPlan -coreMarginsBy die -site sc12mcpp140z_cln28ht -d 1666.6666 1666.6666 135 135 135 135
set_db design_process_node 28
### Timing Analysis Type
set_db timing_analysis_type ocv
# Add Encounter routing option commands in this file
setNanoRouteMode -routeBottomRoutingLayer 2
generateTracks -honorPitch
setNanoRouteMode -routeWithViaInPin true
setNanoRouteMode -routeWithViaOnlyForStandardCellPin true
#Customer is required to source the following placement options in EDI prior to placement
setPlaceMode -checkImplantWidth true
setPlaceMode -honorImplantSpacing true
setPlaceMode -checkImplantMinArea true
addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -fitGap -merge true -powerDomain ACCEL
addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -fitGap -merge true -powerDomain TOP
addFillerGap 0.8 -effort high
checkFiller > check_filler.log
addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -powerDomain ACCEL -fixDrc
addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -powerDomain TOP -fixDrc
#-----------------------------------------------------------------------------
# NanoSoC gate synthesis script for Cadence Genus
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# run: genus -f genus.tcl
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# David Flynn (d.w.flynn@soton.ac.uk)
# Srimanth Tenneti
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
set_multi_cpu_usage -local_cpu 8
## -- Setup libraries -- ##
# Paths to librarys
# Edit this
set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set IO_PAD_DRIVER_DIR $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
set BASE_LIB_DIR $standard_cell_base_path/lib
# Don't touch these
set SRAM_16K_DIR $::env(SOCLABS_PROJECT_DIR)/memories/sram_16k/
set ROM_DIR $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/
set_db init_lib_search_path "$IO_PAD_DRIVER_DIR $BASE_LIB_DIR $SRAM_16K_DIR $ROM_DIR"
set BASE_LIB sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.lib
set SRAM_LIB sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
set ROM_LIB rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
set IO_PAD_DRIVER tphn28hpcpgv18ssg0p81v1p62v125c.lib
create_library_domain domain1
set_db [get_db library_domains domain1] .library "$BASE_LIB $SRAM_LIB $ROM_LIB $IO_PAD_DRIVER"
# set_dont_touch SDFF*
check_library > syn_lib_check.log
## -- Load power intent for top and accelerator power domains -- ##
read_power_intent -cpf -version 1.1 -module nanosoc_chip_pads ../inputs/nanosoc.cpf
## -- Uncomment if you want to preserve hierarchy -- ##
#set_db auto_ungroup none
## -- Read in RTL and elaborate top level
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
elaborate nanosoc_chip_pads
# Preserve hierarchy for M0.
# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
## -- Apply power intent and check library and CPF -- ##
apply_power_intent
#check_cpf -license lpgxl -detail > syn_cpf_check.log
commit_power_intent
check_power_structure -license lpgxl > syn_pow_check.log
## -- Read constraints -- ##
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC28nm/constraints.sdc
set_db dft_scan_style muxed_scan
set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 4
set_db hinst:nanosoc_chip_pads/u_nanosoc_chip_cfg .dft_dont_scan true
define_test_signal -name TEST -active high -shared_input -hookup_pin u_nanosoc_chip/test_i -function test_mode -index 0 TEST
define_test_signal -name CLK -active high -hookup_pin u_nanosoc_chip/clk_i -function test_clock -index 0 CLK
define_test_signal -name NRST -active low -hookup_pin u_nanosoc_chip/nrst_i -function async_set_reset -index 0 NRST
define_test_signal -name SE -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable -function shift_enable -default -index 0 SE
define_scan_chain -name chain_ACCEL -sdi P0[0] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[0] -sdo P1[0] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[0] -shared_output -shared_input
define_scan_chain -name chain_TOP_1 -sdi P0[1] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[1] -sdo P1[1] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[1] -shared_output -shared_input
define_scan_chain -name chain_TOP_2 -sdi P0[2] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[2] -sdo P1[2] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[2] -shared_output -shared_input
define_scan_chain -name chain_TOP_3 -sdi P0[3] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[3] -sdo P1[3] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[3] -shared_output -shared_input
fix_pad_cfg -mode input -test_control TEST P0[0]
fix_pad_cfg -mode input -test_control TEST P0[1]
fix_pad_cfg -mode input -test_control TEST P0[2]
fix_pad_cfg -mode input -test_control TEST P0[3]
fix_pad_cfg -mode output -test_control TEST P1[0]
fix_pad_cfg -mode output -test_control TEST P1[1]
fix_pad_cfg -mode output -test_control TEST P1[2]
fix_pad_cfg -mode output -test_control TEST P1[3]
check_dft_rules
fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin CLK
fix_dft_violations -test_control TEST -async_set
set_db syn_generic_effort high
set_db syn_map_effort high
syn_generic
syn_map
convert_to_scan
connect_scan_chains
syn_opt
report_area > ../reports/syn_nanosoc_area_38pin.rep
report_timing > ../reports/syn_nanosoc_timing_38pin.rep
report_gates > ../reports/syn_nanosoc_gates_38pin.rep
report_power > ../reports/syn_nanosoc_power_38pin.rep
write_hdl > ../outputs/nanosoc_chip_pads_38pin.v
write_hdl -pg > ../outputs/nanosoc_chip_pads_38pin.vp
write_sdf -timescale ns > ../outputs/nanosoc_chip_pads_38pin.sdf
write_do_lec -revised_design ../outputs/nanosoc_chip_pads_38pin.v -no_lp -top nanosoc_chip_pads -logfile ../outputs/ > lec.dofile
write_power_intent -cpf -design nanosoc_chip_pads -base_name ../cpf/nanosoc_syn_out
report_scan_chains > ../outputs/nanosoc_scan_chains_38pin.rep
report_scan_setup > ../outputs/nanosoc_scan_setup_38pin.rep
report_scan_registers > ../outputs/nanosoc_scan_registers_38pin.rep
write_dft_abstract_model > ../outputs/nanosoc_dft_abstract_model_38pin
write_dft_atpg_other_vendor -mentor > ../outputs/nanosoc_atpg_38pin
write_scandef > ../outputs/nanosoc_chip_pads_38pin.def
#-----------------------------------------------------------------------------
# NanoSoC gate synthesis script for Cadence Genus
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# run: genus -f genus.tcl
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# David Flynn (d.w.flynn@soton.ac.uk)
# Srimanth Tenneti
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
set_multi_cpu_usage -local_cpu 8
## -- Setup libraries -- ##
# Paths to librarys
# Edit this
set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set IO_PAD_DRIVER_DIR $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
set BASE_LIB_DIR $standard_cell_base_path/lib
# Don't touch these
set SRAM_16K_DIR $::env(SOCLABS_PROJECT_DIR)/memories/sram_16k/
set ROM_DIR $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/
set_db init_lib_search_path "$IO_PAD_DRIVER_DIR $BASE_LIB_DIR $SRAM_16K_DIR $ROM_DIR"
set BASE_LIB sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.lib
set SRAM_LIB sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
set ROM_LIB rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
set IO_PAD_DRIVER tphn28hpcpgv18ssg0p81v1p62v125c.lib
create_library_domain domain1
set_db [get_db library_domains domain1] .library "$BASE_LIB $SRAM_LIB $ROM_LIB $IO_PAD_DRIVER"
set_dont_touch SDFF*
check_library > syn_lib_check.log
## -- Load power intent for top and accelerator power domains -- ##
read_power_intent -cpf -module nanosoc_chip_pads ../inputs/nanosoc.cpf
## -- Uncomment if you want to preserve hierarchy -- ##
#set_db auto_ungroup none
## -- Read in RTL and elaborate top level
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
elaborate nanosoc_chip_pads
# Preserve hierarchy for M0.
# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
## -- Apply power intent and check library and CPF -- ##
apply_power_intent
# check_cpf -license lpgxl > syn_cpf_check.log
commit_power_intent
check_power_structure -license lpgxl > syn_pow_check.log
## -- Read constraints -- ##
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC28nm/constraints.sdc
set_db syn_generic_effort high
set_db syn_map_effort high
set_db syn_opt_effort high
syn_generic
syn_map
syn_opt
report_area > ../reports/syn_noDFT_nanosoc_area_44pin.rep
report_timing > ../reports/syn_noDFT_nanosoc_timing_44pin.rep
report_gates > ../reports/syn_noDFT_nanosoc_gates_44pin.rep
report_power > ../reports/syn_noDFT_nanosoc_power_44pin.rep
write_hdl > ../outputs/nanosoc_chip_pads_44pin.v
write_hdl -pg > ../outputs/nanosoc_chip_pads_44pin.vp
write_sdf -timescale ns > ../outputs/nanosoc_chip_pads_44pin.sdf
write_do_lec -revised_design ../outputs/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile ../logs > lec.dofile
write_power_intent -cpf -design nanosoc_chip_pads -base_name ../outputs/nanosoc_syn_out
#-----------------------------------------------------------------------------
# NanoSoC IO plan for PnR in cadence Innovus
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
deleteIoFiller -cell PFILLER5_G
deleteIoFiller -cell PFILLER0005_G
loadIoFile ../scripts/nanosoc_io_plan.io
addIoFiller -cell PFILLER5_G -prefix FILLER
addIoFiller -cell PFILLER05_G -prefix FILLER
addIoFiller -cell PFILLER0005_G -prefix FILLER
\ No newline at end of file
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/cadence_captable/1p8m_5x2z_utalrdl
set standard_cell_setup_lib ${standard_cell_base_path}/lib-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_0c.lib_ccs_tn
set standard_cell_typ_lib ${standard_cell_base_path}/lib-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_85c.lib_ccs_tn
set standard_cell_hold_lib ${standard_cell_base_path}/lib-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_125c.lib_ccs_tn
set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
set tphn28hpcpgv18_lef_file ${TSMC_28NM_PDK_PATH}/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/9lm/lef/tphn28hpcpgv18_9lm.lef
set tphn28hpcpgv18_lib_path ${TSMC_28NM_PDK_PATH}/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
set IO_typ_lib ${tphn28hpcpgv18_lib_path}/tphn28hpcpgv18tt0p9v1p8v85c.lib
set IO_hold_lib ${tphn28hpcpgv18_lib_path}/tphn28hpcpgv18ffg0p99v1p98v125c.lib
set IO_setup_lib ${tphn28hpcpgv18_lib_path}/tphn28hpcpgv18ssg0p81v1p62v0c.lib
set SOCLABS_PROJECT_DIR /home/dwn1c21/SoC-Labs/TAPEOUT/feb2025/28nm/accelerator-project/
set sram_16k_path ${SOCLABS_PROJECT_DIR}/memories/sram_16k
set sram_16k_lef_file ${sram_16k_path}/sram_16k.lef
set sram_16k_gds_file ${sram_16k_path}/sram_16k.gds2
set sram_16k_setup_lib ${sram_16k_path}/sram_16k_ssg_cworstt_0p81v_0p81v_0c.lib
set sram_16k_typ_lib ${sram_16k_path}/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
set sram_16k_lib_hold_lib ${sram_16k_path}/sram_16k_ffg_cbestt_0p99v_0p99v_125c.lib
set rom_path ${SOCLABS_PROJECT_DIR}/memories/bootrom
set rom_via_lef_file ${rom_path}/rom_via.lef
set rom_via_gds_file ${rom_path}/rom_via.gds2
set rom_via_setup_lib ${rom_path}/rom_via_ssg_cworstt_0p81v_0p81v_m40c.lib
set rom_via_typ_lib ${rom_path}/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
set rom_via_hold_lib ${rom_path}/rom_via_ffg_cbestt_0p99v_0p99v_125c.lib
create_library_set -name default_libset_max\
-timing\
[list ${standard_cell_setup_lib} ${rom_via_setup_lib} ${sram_16k_setup_lib} \
${IO_setup_lib} ]
create_library_set -name default_libset_min\
-timing\
[list ${rom_via_hold_lib} ${sram_16k_lib_hold_lib} ${IO_hold_lib}\
${standard_cell_hold_lib}]
create_library_set -name typical_libset\
-timing\
[list ${rom_via_typ_lib} ${sram_16k_typ_lib} ${IO_typ_lib}\
${standard_cell_typ_lib}]
create_rc_corner -name default_rc_corner_worst\
-pre_route_res 1\
-post_route_res 1\
-pre_route_cap 1\
-post_route_cap 1\
-post_route_cross_cap 1\
-pre_route_clock_res 0\
-pre_route_clock_cap 0\
-cap_table ${tech_path}/rcworst_T.captbl
create_rc_corner -name default_rc_corner_best\
-pre_route_res 1\
-post_route_res 1\
-pre_route_cap 1\
-post_route_cap 1\
-post_route_cross_cap 1\
-pre_route_clock_res 0\
-pre_route_clock_cap 0\
-cap_table ${tech_path}/rcbest.captbl
create_rc_corner -name default_rc_corner_typical\
-pre_route_res 1\
-post_route_res 1\
-pre_route_cap 1\
-post_route_cap 1\
-post_route_cross_cap 1\
-pre_route_clock_res 0\
-pre_route_clock_cap 0\
-cap_table ${tech_path}/typical.captbl
create_delay_corner -name default_delay_corner_max\
-library_set {default_libset_max}\
-rc_corner default_rc_corner_worst
create_delay_corner -name default_delay_corner_ocv\
-early_library_set {default_libset_min}\
-late_library_set {default_libset_max}\
-rc_corner default_rc_corner_typical
create_delay_corner -name default_delay_corner_min\
-library_set default_libset_min\
-rc_corner default_rc_corner_best
create_delay_corner -name typical_delay_corner\
-library_set typical_libset\
-rc_corner default_rc_corner_typical
create_constraint_mode -name default_constraint_mode\
-sdc_files\
[list ../../../constraints.sdc]
create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
create_analysis_view -name default_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_min
create_analysis_view -name typical_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
create_analysis_view -name typical_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
create_analysis_view -name typical_analysis_view -constraint_mode default_constraint_mode -delay_corner typical_delay_corner
set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
###############################################################
# Generated by: Cadence Innovus 21.11-s130_1
# OS: Linux x86_64(Host ID srv03335)
# Generated on: Thu Nov 16 16:18:31 2023
# Design: nanosoc_chip_pads
# Command: write_io_file -locations -template nanosoc_chip_pads.save.io
###############################################################
(globals
version = 3
io_order = default
)
(iopad
(topright
(inst name="CornerCell2" cell=PCORNER_G offset=0 orientation=R90 place_status=fixed))
(top
(inst name="uPAD_TEST_I" offset=149.29 place_status=fixed)
(inst name="uPAD_SWDCK_I" offset=257.86 place_status=fixed )
(inst name="uPAD_VDD_3" offset=366.43 place_status=fixed )
(inst name="uPAD_VSS_3" offset=475.00 place_status=fixed )
(inst name="uPAD_VDDIO_3" offset=583.57 place_status=fixed )
(inst name="uPAD_P1_00" offset=692.14 place_status=fixed )
(inst name="uPAD_P1_01" offset=800.71 place_status=fixed )
)
(topleft
(inst name="CornerCell1" cell=PCORNER_G offset=0 orientation=R180 place_status=fixed))
(left
(inst name="uPAD_P0_04" offset=146.25 place_status=fixed )
(inst name="uPAD_P0_05" offset=251.25 place_status=fixed )
(inst name="uPAD_P0_03" offset=356.25 place_status=fixed )
(inst name="uPAD_VDDACC_0" offset=461.25 place_status=fixed )
(inst name="uPAD_VSS_0" offset=566.25 place_status=fixed )
(inst name="uPAD_CLK_I" offset=671.25 place_status=fixed )
(inst name="uPAD_VDD_0" offset=776.25 place_status=fixed )
(inst name="uPAD_VDDIO_0" offset=881.25 place_status=fixed )
(inst name="uPAD_SWDIO_IO" offset=986.25 place_status=fixed )
(inst name="uPAD_VSSIO_0" offset=1091.25 place_status=fixed )
(inst name="uPAD_P0_06" offset=1196.25 place_status=fixed )
(inst name="uPAD_P0_07" offset=1301.25 place_status=fixed )
)
(bottomleft
(inst name="CornerCell4" cell=PCORNER_G offset=0 orientation=R270 place_status=fixed))
(bottom
(inst name="uPAD_P0_02" offset=149.29 place_status=fixed )
(inst name="uPAD_VDDACC_1" offset=257.86 place_status=fixed )
(inst name="uPAD_SE_I" offset=366.43 place_status=fixed )
(inst name="uPAD_VDD_1" offset=475.00 place_status=fixed )
(inst name="uPAD_VSS_1" offset=583.57 place_status=fixed )
(inst name="uPAD_P0_01" offset=692.14 place_status=fixed )
(inst name="uPAD_P0_00" offset=800.71 place_status=fixed)
)
(bottomright
(inst name="CornerCell3" cell=PCORNER_G offset=0 orientation=R0 place_status=fixed))
(right
(inst name="uPAD_P1_07" offset=146.25 place_status=fixed )
(inst name="uPAD_P1_06" offset=251.25 place_status=fixed )
(inst name="uPAD_VSSIO_1" offset=356.25 place_status=fixed )
(inst name="uPAD_P1_03" offset=461.25 place_status=fixed )
(inst name="uPAD_P1_02" offset=566.25 place_status=fixed )
(inst name="uPAD_VDDACC_2" offset=671.25 place_status=fixed )
(inst name="uPAD_VDD_2" offset=776.25 place_status=fixed )
(inst name="uPAD_VSS_2" offset=881.25 place_status=fixed )
(inst name="uPAD_VDDIO_2" offset=986.25 place_status=fixed )
(inst name="uPAD_NRST_I" offset=1091.25 place_status=fixed )
(inst name="uPAD_P1_04" offset=1196.25 place_status=fixed )
(inst name="uPAD_P1_05" offset=1301.25 place_status=fixed )
)
)
############################################
# Script : Placement
# Date : 26th April 2025
# Authors : Srimanth Tenneti
# Daniel Newbrook
############################################
### Congestion and Timing Setting
set_db place_global_cong_effort auto
set_db place_global_timing_effort high
### Uniform Cell Distribution and fill gap
set_db place_global_uniform_density true
set_db place_detail_legalization_inst_gap 2
### Placement Mode Config
set_db place_design_floorplan_mode false
place_design
### Delay Calculation
write_sdf design.sdf -ideal_clock_network
set_db add_tieoffs_max_fanout 10
addTieHiLo -cell {TIELO_X1M_A12PP140ZTS_C35 TIEHI_X1M_A12PP140ZTS_C35} -prefix LTIE -powerDomain TOP -excludePin ../scripts/tieoff_exclude
addTieHiLo -cell {TIELO_X1M_A12PP140ZTS_C35 TIEHI_X1M_A12PP140ZTS_C35} -prefix LTIE -powerDomain ACCEL -excludePin ../scripts/tieoff_exclude
eval_legacy {addInst -cell PAD60LU -inst BPAD_TEST_I -loc {150.00 1928} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDCK_I -loc {425.00 1928} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_3 -loc {700.43 1928} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_3 -loc {975.00 1928} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_3 -loc {1250.57 1928} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_00 -loc {1525.14 1928} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_01 -loc {1800.00 1928} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_04 -loc {0.0 200.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_05 -loc {0.0 333.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_03 -loc {0.0 466.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_0 -loc {0.0 599.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_0 -loc {0.0 733.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_CLK_I -loc {0.0 866.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_0 -loc {0.0 999.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_0 -loc {0.0 1133.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDIO_IO -loc {0.0 1266.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_0 -loc {0.0 1399.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_06 -loc {0.0 1533.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_07 -loc {0.0 1666.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_02 -loc {150.29 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_1 -loc {425.86 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_1 -loc {700.43 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_1 -loc {975.00 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_1 -loc {1250.57 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_01 -loc {1525.14 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_00 -loc {1800.71 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_07 -loc {2028 200.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_06 -loc {2028 333.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_1 -loc {2028 466.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_03 -loc {2028 599.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_02 -loc {2028 733.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_2 -loc {2028 866.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_2 -loc {2028 999.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_2 -loc {2028 1133.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_2 -loc {2028 1266.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_NRST_I -loc {2028 1399.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_04 -loc {2028 1533.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_05 -loc {2028 1666.25} -ori R90}
#------------------------------------------------------------------------------------
# Cadence Innovus: Place macros
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# Copyright (c) 2023, SoC Labs (www.soclabs.org)
#------------------------------------------------------------------------------------
# relative floorplan
delete_relative_floorplan -all
create_relative_floorplan -orient R90 -ref_type core_boundary -horizontal_edge_separate {1 0 1} -vertical_edge_separate {2 0 2} -place u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h_u_expram_h_u_sram_genblk1.u_sram
create_relative_floorplan -orient R90 -ref_type object -horizontal_edge_separate {1 0 1} -vertical_edge_separate {1 -1 3} -place u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l_u_expram_l_u_sram_genblk1.u_sram -ref u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h_u_expram_h_u_sram_genblk1.u_sram
create_relative_floorplan -orient R90 -ref_type object -horizontal_edge_separate {1 0 1} -vertical_edge_separate {1 -1 3} -place u_nanosoc_chip/u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_sram -ref u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l_u_expram_l_u_sram_genblk1.u_sram
create_relative_floorplan -orient R90 -ref_type core_boundary -horizontal_edge_separate {1 0 1} -vertical_edge_separate {0 0 0} -place u_nanosoc_chip/u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_sram
create_relative_floorplan -orient R90 -ref_type object -horizontal_edge_separate {1 0 1} -vertical_edge_separate {3 1 1} -place u_nanosoc_chip/u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom -ref u_nanosoc_chip/u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_sram
move_obj u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -point {135 135}
update_floorplan_obj -obj u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -polygon {{135 135} {135 1320} {1532 1320} {1532 135}}
generate_fence -hInst u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -min_gap 2.4
#create_partition -hinst u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 0 -min_pitch_right 0 -min_pitch_top 2 -min_pitch_bottom 0 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 0 0 0 -route_halo 0.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
addHaloToBlock {2.4 2.4 2.4 2.4} -allMacro
#-----------------------------------------------------------------------------
# NanoSoC Place and route script for Cadence Innovus
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# run: innovus -f pnr_flow.tcl
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# David Flynn (d.w.flynn@soton.ac.uk)
# Srimanth Tenneti
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
set SC_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/gds2/sc12_cln65lp_base_rvt.gds2
set SC_HVT_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_hvt/r0p0/gds2/sc12_cln65lp_base_hvt.gds2
set PMK_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_pmk_rvt_hvt/r0p0/gds2/sc12_cln65lp_pmk_rvt_hvt.gds2
set RF_16K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.gds2
set RF_08K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.gds2
set ROM_VIA_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.gds2
setMultiCpuUsage -localCpu 8
puts "Starting PnR Flow ..."
### Design Import
source ../scripts/design_import_noDFT.tcl
### IO Planning
source ../scripts/io_plan.tcl
read_power_intent -cpf ../outputs/nanosoc_syn_out.cpf
commit_power_intent
reportPowerDomain
saveDesign nanosoc_chip_pads
update_delay_corner -name default_delay_corner_max -power_domain TOP
update_delay_corner -name default_delay_corner_max -power_domain ACCEL
update_delay_corner -name default_delay_corner_min -power_domain ACCEL
update_delay_corner -name default_delay_corner_min -power_domain TOP
update_delay_corner -name default_delay_corner_ocv -power_domain TOP
update_delay_corner -name default_delay_corner_ocv -power_domain ACCEL
update_delay_corner -name typical_delay_corner -power_domain ACCEL
update_delay_corner -name typical_delay_corner -power_domain TOP
### Memory and accelerator placement
source ../scripts/place_macros.tcl
### Power Plan
source ../scripts/power_plan.tcl
### Power Route
source ../scripts/power_route.tcl
report_timing -late > ../reports/1pre_place_nanosoc_imp_timing_late.rep
report_timing -early > ../reports/1pre_place_nanosoc_imp_timing_early.rep
uniquify nanosoc_chip_pads -verbose
saveDesign nanosoc_chip_pads
### Placement
source ../scripts/place.tcl
report_timing -late > ../reports/2post_place_nanosoc_imp_timing_late.rep
report_timing -early > ../reports/2post_place_nanosoc_imp_timing_early.rep
#reorder_scan
saveDesign nanosoc_chip_pads
### CTS
source ../scripts/clock_tree_synthesis.tcl
#reorder_scan -clock_aware true
report_timing -late > ../reports/3post_clock_nanosoc_imp_timing_late.rep
report_timing -early > ../reports/3post_clock_nanosoc_imp_timing_early.rep
saveDesign nanosoc_chip_pads
### Add fillers
source ../scripts/filler.tcl
### Routing
source ../scripts/route.tcl
report_timing -early > ../reports/4post_route_nanosoc_imp_timing_early.rep
report_timing -late > ../reports/4post_route_nanosoc_imp_timing_late.rep
optDesign -postRoute
report_timing -early > ../reports/5post_route_opt_nanosoc_imp_timing_early.rep
report_timing -late > ../reports/5post_route_opt_nanosoc_imp_timing_late.rep
check_antenna
saveDesign nanosoc_chip_pads
delete_routes -net VDDIO
delete_routes -net VSSIO
source place_bondpads.tcl
check_drc -out_file ../reports/nanosoc_imp_drc.rep
check_filler -out_file ../reports/nanosoc_imp_filler.rep
check_connectivity -out_file ../reports/nanosoc_imp_connectivity.rep
check_process_antenna -out_file ../reports/nanosoc_imp_antenna.rep
gui_show
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_default_early.mtarpt
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_default_late.mtarpt
set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_typical_early.mtarpt
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_typical_late.mtarpt
set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
write_stream ../outputs/nanosoc.gds \
-map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \
-lib_name DesignLib \
-merge [list ${SC_GDS2} ${RF_16K_GDS2} ${RF_08K_GDS2} ${ROM_VIA_GDS2}]\
-output_macros -unit 1000 -mode all
report_area > ../reports/nanosoc_imp_area.rep
report_power > ../reports/nanosoc_imp_power.rep
report_timing -late > ../reports/nanosoc_imp_timing_late.rep
report_timing -early > ../reports/nanosoc_imp_timing_early.rep
set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
report_timing -late > ../reports/nanosoc_imp_timing_typical_late.rep
report_timing -early > ../reports/nanosoc_imp_timing_typical_early.rep
set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
write_netlist ../outputs/nanosoc_chip_pads_38pin_pnr.v
write_sdf -min_view default_analysis_view_hold -typical_view typical_analysis_view -max_view default_analysis_view_setup ../outputs/nanosoc_chip_pads_38pin_pnr.sdf
saveDesign nanosoc_chip_pads
#########################################
# Script : Power Planning
# Tool : Cadence Innovus
# Date : May 22, 2023
# Author : Srimanth Tenneti
#########################################
### Connecting Global Nets
globalNetConnect VDD -type pg_pin -pin VDD -instanceBasename *
globalNetConnect VDDIO -type pg_pin -pin VDDIO -instanceBasename *
globalNetConnect VSS -type pg_pin -pin VSS -instanceBasename *
globalNetConnect VSSIO -type pg_pin -pin VSSIO -instanceBasename *
globalNetConnect VDDACC -type pg_pin -pin VDD -instanceBasename {} -hierarchicalInstance u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -override
### Top and Bottom Metal Declartions
set_db add_rings_stacked_via_top_layer M8
set_db add_rings_stacked_via_bottom_layer M1
### Adding Rings
addRing -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M7 bottom M7 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
sroute -connect {padPin padRing} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort allGeom} -padPinTarget nearestTarget -allowJogging 1 -crossoverViaLayerRange { M1(1) AP(9) } -nets { VSS } -allowLayerChange 1 -padPinWidth 1.5 -targetViaLayerRange { M1(1) AP(9) }
sroute -connect {padPin padRing} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort allGeom} -padPinTarget nearestTarget -allowJogging 1 -crossoverViaLayerRange { M1(1) AP(9) } -nets { VDD VDDACC } -allowLayerChange 1 -padPinWidth 1.41 -targetViaLayerRange { M1(1) AP(9) }
### Adding Stripes
set_db add_stripes_ignore_block_check true
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
set_db add_stripes_rows_without_stripes_only false
set_db add_stripes_extend_to_closest_target none
set_db add_stripes_stop_at_last_wire_for_area false
set_db add_stripes_ignore_non_default_domains true
set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0
set_db add_stripes_stripe_min_length stripe_width
set_db add_stripes_stacked_via_top_layer AP
set_db add_stripes_stacked_via_bottom_layer M1
set_db add_stripes_via_using_exact_crossover_size false
set_db add_stripes_split_vias false
set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
addStripe -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit AP -padcore_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
# Connect Accelerator region
select_obj u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator
set_db add_stripes_ignore_block_check true
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
set_db add_stripes_rows_without_stripes_only false
set_db add_stripes_extend_to_closest_target {ring stripe}
set_db add_stripes_stop_at_last_wire_for_area false
set_db add_stripes_partial_set_through_domain true
set_db add_stripes_ignore_non_default_domains false
set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0
set_db add_stripes_stripe_min_length stripe_width
set_db add_stripes_stacked_via_top_layer AP
set_db add_stripes_stacked_via_bottom_layer M4
set_db add_stripes_via_using_exact_crossover_size false
set_db add_stripes_split_vias false
set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
addStripe -nets {VDDACC VSS} -layer AP -direction horizontal -width 2 -spacing 2 -set_to_set_distance 20 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit AP -padcore_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
# connect Macros
select_obj [ list u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
set_db add_stripes_ignore_block_check false
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
set_db add_stripes_rows_without_stripes_only false
set_db add_stripes_extend_to_closest_target {ring stripe}
addStripe -nets {VDD VSS} -layer M5 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -start_from bottom -start_offset 8 -stop_offset 0 -switch_layer_over_obs false -merge_stripes_value 500 -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit AP -padcore_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
# Add END CAPS
addEndCap -preCap ENDCAPTIE3_A12PP140ZTS_C35 -postCap ENDCAPTIE3_A12PP140ZTS_C35 -prefix ENDCAP
addEndCap -powerDomain ACCEL -preCap ENDCAPTIE3_A12PP140ZTS_C35 -postCap ENDCAPTIE3_A12PP140ZTS_C35 -prefix ENDCAP
#add_endcaps -power_domain PD_SYS -start_row_cap ENDCAPBIAS2_A12TR -end_row_cap ENDCAPBIAS2_A12TR -prefix ENDCAP_SYS
#add_endcaps -power_domain PD_DBG -start_row_cap ENDCAPBIAS2_A12TR -end_row_cap ENDCAPBIAS2_A12TR -prefix ENDCAP_DBG
##################################
# Script : Special Route Script
# Date : May 24, 2023
# Description : Power Routing
# Author : Srimanth Tenneti
##################################
set_db route_special_via_connect_to_shape { padring stripe }
sroute -connect {blockPin corePin floatingStripe} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort oneGeom} -padPinTarget nearestTarget -corePinTarget firstAfterRowEnd -floatingStripeTarget {blockRing padRing ring stripe ringPin blockPin followpin} -allowJogging 1 -powerDomains { ACCEL } -crossoverViaLayerRange { M1(1) AP(9) } -nets { VDDACC VSS } -allowLayerChange 1 -blockPin useLef -targetViaLayerRange { M1(1) AP(9) }
sroute -connect {blockPin corePin floatingStripe} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort oneGeom} -padPinTarget nearestTarget -corePinTarget firstAfterRowEnd -floatingStripeTarget {blockRing padRing ring stripe ringPin blockPin followpin} -allowJogging 1 -powerDomains { TOP } -crossoverViaLayerRange { M1(1) AP(9) } -nets { VDD VSS } -allowLayerChange 1 -blockPin useLef -targetViaLayerRange { M1(1) AP(9) }
#route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { PD_SYS } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD_SYS VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
#route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { PD_DBG } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD_DBG VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
#route_special -nets {VDD VSS} -connect core_pin -block_pin_target nearest_target -core_pin_target first_after_row_end -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
### Clock Net Spacing
#set_route_attributes -nets clk -preferred_extra_space_tracks 2
### Multi Cut Via Effort
set_db route_design_detail_use_multi_cut_via_effort medium
### Timing Driven Route
set_db route_design_with_timing_driven 1
### SI Driven Route
set_db route_design_with_si_driven 1
### Route Design
routeDesign -globalDetail
uPAD_SE_I/IE
uPAD_SE_I/PE
uPAD_SE_I/DS
uPAD_SE_I/I
uPAD_SE_I/OEN
uPAD_CLK_I/IE
uPAD_CLK_I/PE
uPAD_CLK_I/DS
uPAD_CLK_I/I
uPAD_CLK_I/OEN
uPAD_TEST_I/IE
uPAD_TEST_I/PE
uPAD_TEST_I/DS
uPAD_TEST_I/I
uPAD_TEST_I/OEN
uPAD_NRST_I/IE
uPAD_NRST_I/PE
uPAD_NRST_I/DS
uPAD_NRST_I/I
uPAD_NRST_I/OEN
uPAD_SWDIO_IO/PE
uPAD_SWDIO_IO/DS
uPAD_SWDCK_I/IE
uPAD_SWDCK_I/PE
uPAD_SWDCK_I/DS
uPAD_SWDCK_I/I
uPAD_SWDCK_I/OEN
uPAD_P0_00/DS
uPAD_P0_01/DS
uPAD_P0_02/DS
uPAD_P0_03/DS
uPAD_P0_04/DS
uPAD_P0_05/DS
uPAD_P0_06/DS
uPAD_P0_07/DS
uPAD_P1_00/DS
uPAD_P1_01/DS
uPAD_P1_02/DS
uPAD_P1_03/DS
uPAD_P1_04/DS
uPAD_P1_05/DS
uPAD_P1_06/DS
uPAD_P1_07/DS
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