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Commit 18ea18ce authored by Daniel Newbrook's avatar Daniel Newbrook
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Update 28nm Fusion compiler flow

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.gitignore
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......@@ -49,6 +49,8 @@ ASIC/*/*/Synopsys_FC/io_lib
ASIC/*/*/Synopsys_FC/legalizer_debug_plots
ASIC/*/*/Synopsys_FC/libs
ASIC/*/*/Synopsys_FC/reports
ASIC/*/*/Synopsys_FC/logs
ASIC/*/*/Synopsys_FC/work
ASIC/Synopsys/Formality/FM_INFO/*
......
ASIC/TSMC28nm/38pin/Synopsys_FC/FC_flow.tcl deleted 100644 → 0
+ 0
− 51
View file @ cf777dbf
# Main flow for Synopsys fusion compiler
set REPORT_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
set LOG_DIR $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
# Design setup: read libraries and RTL
redirect -tee -file $LOG_DIR/01_design_setup.log {source ./design_setup.tcl}
# Floorplan setup
redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {1111.1111111 1111.11111} -core_offset {140}}
redirect -tee -file $LOG_DIR/03_floorplan.log {source ./floorplan/fp.tcl}
place_io
# Read Constraints
redirect -tee -file $LOG_DIR/04_constraints.log {read_sdc ../../constraints.sdc}
# Power Plan
load_upf nanosoc_chip_pads.upf
create_voltage_area -power_domains ACCEL
create_voltage_area -power_domains PD_DBG
create_voltage_area -power_domains PD_SYS
create_voltage_area_shape -voltage_area ACCEL \
-region {{{140.000 140.000} {370.655 311.165}}} \
-guard_band {2 2}
create_voltage_area_shape -voltage_area PD_DBG \
-region {{{703.115 140.000} {971.040 329.520}}} \
-guard_band {2 2}
create_voltage_area_shape -voltage_area PD_SYS \
-region {{{234.000 453.940} {548.100 645.665}}} \
-guard_band {2 2}
create_pg_region {pg_accel} -voltage_area {ACCEL}
create_pg_region {pg_dbg} -voltage_area {PD_DBG}
create_pg_region {pg_sys} -voltage_area {PD_SYS}
redirect -tee -file $LOG_DIR/05_power_plan.log {source ./power_plan.tcl}
# Init coarse placement
redirect -tee -file $LOG_DIR/06_init_placement.log {source ./init_placement.tcl}
# Physical aware synthesis
redirect -tee -file $LOG_DIR/07_compile.log {compile_fusion}
redirect -tee -file $REPORT_DIR/timing_01_compile.rep {report_timing}
save_lib nanosoc_chip_pads.dlib
redirect -tee -file $LOG_DIR/08_clock_tree.log {synthesize_clock_trees -clocks {clk swdclk}}
redirect -tee -file $LOG_DIR/09_clock_opt.log {clock_opt}
redirect -tee -file $REPORT_DIR/timing_02_clock_opt.rep {report_timing}
ASIC/TSMC28nm/38pin/Synopsys_FC/design_setup.tcl deleted 100644 → 0
+ 0
− 31
View file @ cf777dbf
set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
set TLU_cbest $TLU_dir/cbest.tluplus
set TLU_cworst $TLU_dir/cworst.tluplus
set TLU_rcbest $TLU_dir/rcbest.tluplus
set TLU_rcworst $TLU_dir/rcworst.tluplus
set TLU_map $TLU_dir/tluplus.map
create_lib nanosoc_chip_pads.dlib \
-technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf \
-ref_libs {./cln28ht/ ./cln28ht_pmk/ ./cln28ht_ret/ ./sram_16k/ ./rom_via/ ./io_lib/ ./pad_lib/}
source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
elaborate nanosoc_chip_pads
set_top_module nanosoc_chip_pads
redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary cln28ht}
redirect -tee -file ./lib_cell_pmk_summary.log {report_lib -cell_summary cln28ht_pmk}
redirect -tee -file ./lib_cell_ret_summary.log {report_lib -cell_summary cln28ht_ret}
read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map -sanity_check advanced
save_lib nanosoc_chip_pads.dlib
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def
+ 2
− 2
View file @ 18ea18ce
......@@ -2,12 +2,12 @@
# Fusion Compiler write_def
# Release : U-2022.12
# User Name : dwn1c21
# Date : Fri Oct 25 13:42:48 2024
# Date : Tue Apr 15 19:30:50 2025
#
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN nanosoc_chip_pads ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 0 1110700 ) ( 1111040 1110700 ) ( 1111040 0 ) ;
DIEAREA ( 0 0 ) ( 0 1610400 ) ( 1111100 1610400 ) ( 1111100 0 ) ;
END DESIGN
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl
+ 1
− 1
View file @ 18ea18ce
################################################################################
#
# Created by fc write_floorplan on Fri Oct 25 13:42:48 2024
# Created by fc write_floorplan on Tue Apr 15 19:30:50 2025
#
################################################################################
......
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
+ 30
− 33
View file @ 18ea18ce
################################################################################
#
# Created by fc compare_floorplans on Fri Oct 25 13:42:48 2024
# Created by fc compare_floorplans on Tue Apr 15 19:30:51 2025
#
# DO NOT EDIT - automatically generated file
#
......@@ -8,37 +8,34 @@
START nanosoc_chip_pads
MACROS
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {140.0000 919.4450} {304.6650 970.7000} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {626.6800 781.1650} {798.8600 970.7000} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {798.8600 781.1650} {971.0400 970.7000} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {798.8600 563.3200} {971.0400 752.8550} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {626.6800 563.3200} {798.8600 752.8550} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {180.0000 1399.3550} {275.0500 1430.4000} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {758.9200 1051.3300} {931.1000 1240.8650} }
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {586.7400 1051.3300} {758.9200 1240.8650} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {758.9200 1240.8650} {931.1000 1430.4000} }
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {586.7400 1240.8650} {758.9200 1430.4000} }
PINS
VDDIO { {555.5200 555.3500} {555.5201 555.3501} }
VSSIO { {555.5200 555.3500} {555.5201 555.3501} }
VDD { {555.5200 555.3500} {555.5201 555.3501} }
VSS { {555.5200 555.3500} {555.5201 555.3501} }
VDDACC { {555.5200 555.3500} {555.5201 555.3501} }
SE { {555.5200 555.3500} {555.5201 555.3501} }
CLK { {555.5200 555.3500} {555.5201 555.3501} }
TEST { {555.5200 555.3500} {555.5201 555.3501} }
NRST { {555.5200 555.3500} {555.5201 555.3501} }
P0[7] { {555.5200 555.3500} {555.5201 555.3501} }
P0[6] { {555.5200 555.3500} {555.5201 555.3501} }
P0[5] { {555.5200 555.3500} {555.5201 555.3501} }
P0[4] { {555.5200 555.3500} {555.5201 555.3501} }
P0[3] { {555.5200 555.3500} {555.5201 555.3501} }
P0[2] { {555.5200 555.3500} {555.5201 555.3501} }
P0[1] { {555.5200 555.3500} {555.5201 555.3501} }
P0[0] { {555.5200 555.3500} {555.5201 555.3501} }
P1[7] { {555.5200 555.3500} {555.5201 555.3501} }
P1[6] { {555.5200 555.3500} {555.5201 555.3501} }
P1[5] { {555.5200 555.3500} {555.5201 555.3501} }
P1[4] { {555.5200 555.3500} {555.5201 555.3501} }
P1[3] { {555.5200 555.3500} {555.5201 555.3501} }
P1[2] { {555.5200 555.3500} {555.5201 555.3501} }
P1[1] { {555.5200 555.3500} {555.5201 555.3501} }
P1[0] { {555.5200 555.3500} {555.5201 555.3501} }
SWDIO { {555.5200 555.3500} {555.5201 555.3501} }
SWDCK { {555.5200 555.3500} {555.5201 555.3501} }
VDDIO { {1110.7600 804.6750} {1111.1000 804.7250} }
VSSIO { {555.5750 1610.1200} {555.6250 1610.4000} }
SE { {0.0000 804.6750} {0.3400 804.7250} }
CLK { {70.0500 222.0150} {73.0500 238.0650} }
TEST { {1038.0500 797.1750} {1041.0500 813.2250} }
NRST { {70.0500 352.0550} {73.0500 368.1050} }
P0[7] { {920.2500 70.0500} {936.3000 73.0500} }
P0[6] { {70.0500 1262.3350} {73.0500 1278.3850} }
P0[5] { {70.0500 1132.2950} {73.0500 1148.3450} }
P0[4] { {70.0500 1002.2550} {73.0500 1018.3050} }
P0[3] { {70.0500 872.2150} {73.0500 888.2650} }
P0[2] { {70.0500 742.1750} {73.0500 758.2250} }
P0[1] { {70.0500 612.1350} {73.0500 628.1850} }
P0[0] { {70.0500 482.0950} {73.0500 498.1450} }
P1[7] { {257.6300 70.0500} {273.6800 73.0500} }
P1[6] { {340.4550 70.0500} {356.5050 73.0500} }
P1[5] { {423.2850 70.0500} {439.3350 73.0500} }
P1[4] { {506.1100 70.0500} {522.1600 73.0500} }
P1[3] { {588.9400 70.0500} {604.9900 73.0500} }
P1[2] { {671.7650 70.0500} {687.8150 73.0500} }
P1[1] { {754.5950 70.0500} {770.6450 73.0500} }
P1[0] { {837.4200 70.0500} {853.4700 73.0500} }
SWDIO { {1038.0500 1079.2550} {1041.0500 1095.3050} }
SWDCK { {1038.0500 1361.3350} {1041.0500 1377.3850} }
END nanosoc_chip_pads
ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl
+ 14
− 120
View file @ 18ea18ce
################################################################################
#
# Created by fc write_floorplan on Fri Oct 25 13:42:48 2024
# Created by fc write_floorplan on Tue Apr 15 19:30:50 2025
#
################################################################################
......@@ -20,107 +20,42 @@ read_def ${_dirName__0}/floorplan.def
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R0
set_attribute -quiet -objects $cellInst -name origin -value { 140.0000 919.4450 \
}
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 275.0500 \
1399.3550 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 781.1650 \
}
set_attribute -quiet -objects $cellInst -name origin -value { 931.1000 \
1051.3300 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 781.1650 \
}
set_attribute -quiet -objects $cellInst -name origin -value { 758.9200 \
1051.3300 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 971.0400 563.3200 \
}
set_attribute -quiet -objects $cellInst -name origin -value { 931.1000 \
1240.8650 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
}
set cellInst [get_cells { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R90
set_attribute -quiet -objects $cellInst -name origin -value { 798.8600 563.3200 \
}
set_attribute -quiet -objects $cellInst -name origin -value { 758.9200 \
1240.8650 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
create_keepout_margin -type soft -outer { 2.0000 2.0000 2.0000 2.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
create_keepout_margin -type routing_blockage -outer { 2.0000 2.0000 2.0000 \
2.0000 } -layers { M1 VIA1 M2 VIA2 M3 VIA3 M4 } { \
u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
}
################################################################################
......@@ -140,22 +75,6 @@ remove_bounds -all
################################################################################
################################################################################
# Blockages
################################################################################
remove_routing_blockages -all -force
remove_placement_blockages -all -force
remove_pin_blockages -all
remove_shaping_blockages -all
################################################################################
# User attributes of blockages
################################################################################
################################################################################
# Module Boundaries
################################################################################
......@@ -166,35 +85,10 @@ if [sizeof_collection $hbCells] {
}
################################################################################
# I/O guides
################################################################################
remove_io_guides -all
create_io_guide -name main_io_ring.left -side left -line { {0.0000 110.0000} \
890.7000 } -offset {0.0000 0.0000} -pad_cells { uPAD_CLK_I uPAD_NRST_I \
uPAD_P0_00 uPAD_P0_01 uPAD_P0_02 uPAD_P0_03 uPAD_P0_04 uPAD_P0_05 uPAD_P0_06 }
create_io_guide -name main_io_ring.bottom -side bottom -line { {1001.0400 \
0.0000} 891.0400 } -offset {0.0000 0.0000} -pad_cells { uPAD_P0_07 \
uPAD_P1_00 uPAD_P1_01 uPAD_P1_02 uPAD_P1_03 uPAD_P1_04 uPAD_P1_05 \
uPAD_P1_06 uPAD_P1_07 uPAD_SE_I }
create_io_guide -name main_io_ring.right -side right -line { {1111.0400 \
1000.7000} 890.7000 } -offset {0.0000 0.0000} -pad_cells { uPAD_SWDCK_I \
uPAD_SWDIO_IO uPAD_TEST_I uPAD_VDDACC_0 uPAD_VDDACC_1 uPAD_VDDACC_2 \
uPAD_VDDIO_0 uPAD_VDDIO_2 uPAD_VDDIO_3 }
create_io_guide -name main_io_ring.top -side top -line { {110.0000 1110.7000} \
891.0400 } -offset {0.0000 0.0000} -pad_cells { uPAD_VDD_0 uPAD_VDD_1 \
uPAD_VDD_2 uPAD_VDD_3 uPAD_VSSIO_0 uPAD_VSSIO_1 uPAD_VSS_0 uPAD_VSS_1 \
uPAD_VSS_2 uPAD_VSS_3 }
################################################################################
# User attributes of I/O guides
################################################################################
################################################################################
# User attributes of current block
################################################################################
set_attribute [current_design] achieved_target_routing_density 0.0
set_attribute [current_design] expanded_util 0.71
ASIC/TSMC28nm/38pin/Synopsys_FC/init_placement.tcl deleted 100644 → 0
+ 0
− 16
View file @ cf777dbf
set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
set_temperature -40 -min 125 -corners default
set_voltage 0.81 -min 0.99 -corners default
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD}] 0.81
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD_SYS}] 0.81
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDD_DBG}] 0.81
set_voltage -min 0.99 -corners default -object_list [get_supply_nets {VDDACC}] 0.81
set_voltage -min 0.0 -corners default -object_list [get_supply_nets {VSS}] 0.0
redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_nanosoc_chip u_nanosoc_chip_cfg}]
explore_logic_hierarchy -place -rectangular
save_lib nanosoc_chip_pads.dlib
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LIBS_DIR:=./libs
REPORT_DIR:=./reports
LOG_DIR:=./logs
WORK_DIR:=./work
make_directories:
mkdir -p $(LIBS_DIR)
mkdir -p $(REPORT_DIR)
mkdir -p $(LOG_DIR)
mkdir -p $(WORK_DIR)
generate_libs: make_directories
cd $(LIBS_DIR); lc_shell -f ../scripts/synopsys_lib_conversion.tcl;
fusion_init_design:
cd $(WORK_DIR); fc_shell -f ../scripts/1_design_setup.tcl;
fusion_synthesis:
cd $(WORK_DIR); fc_shell -f ../scripts/2_synthesis.tcl;
fusion_clock_opt:
cd $(WORK_DIR); fc_shell -f ../scripts/3_clock.tcl
fusion_route:
cd $(WORK_DIR); fc_shell;
fusion_full_flow: fusion_init_design fusion_synthesis fusion_clock_opt fusion_route
all: generate_libs fusion_full_flow
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################################################################################
# Create power domains
################################################################################
create_power_domain TOP
create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
create_power_domain PD_SYS -elements u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys
create_power_domain PD_DBG -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_dbg \
u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_dap/u_ap}
################################################################################
# Create and logically connect power ports and nets
################################################################################
# Always on VDD
create_supply_port VDD
create_supply_net VDD -domain TOP
create_supply_net VDD -domain PD_SYS -reuse
create_supply_net VDD -domain PD_DBG -reuse
connect_supply_net VDD -ports VDD
# Ground
create_supply_port VSS
create_supply_net VSS -domain TOP
create_supply_net VSS -domain PD_SYS -reuse
create_supply_net VSS -domain PD_DBG -reuse
create_supply_net VSS -domain ACCEL -reuse
connect_supply_net VSS -ports VSS
# Switched VDD
create_supply_net VDD_SYS -domain PD_SYS -resolve parallel
create_supply_net VDD_DBG -domain PD_DBG -resolve parallel
# VDDACC
create_supply_port VDDACC
create_supply_net VDDACC -domain ACCEL
connect_supply_net VDDACC -ports VDDACC
################################################################################
# Assign power supplies to power domains
################################################################################
set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
set_domain_supply_net PD_SYS -primary_power_net VDD_SYS -primary_ground_net VSS
set_domain_supply_net PD_DBG -primary_power_net VDD_DBG -primary_ground_net VSS
################################################################################
# Create Power Switches
################################################################################
create_power_switch uswitch1 -domain PD_SYS \
-input_supply_port {VDD VDD} \
-output_supply_port {VDD_SYS VDD_SYS} \
-control_port {SYSPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWN} \
-ack_port {SYSPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWNACK {SYSPWRDOWN}} \
-ack_delay {SYSPWRDOWNACK 65000} \
-on_state {on_state VDD {!SYSPWRDOWN}} \
-off_state {off_state { SYSPWRDOWN}}
create_power_switch uswitch2 -domain PD_DBG \
-input_supply_port {VDD VDD} \
-output_supply_port {VDD_DBG VDD_DBG} \
-control_port {DBGPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWN} \
-ack_port {DBGPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWNACK {DBGPWRDOWN}} \
-ack_delay {DBGPWRDOWNACK 65000} \
-on_state {on_state VDD {!DBGPWRDOWN}} \
-off_state {off_state { DBGPWRDOWN}}
################################################################################
# Set Isolation Controls
# - iso_low1, iso_high1 at PD_SYS outputs
# - iso_low2 at PD_DBG outputs
################################################################################
set_isolation iso_low1 -domain PD_SYS \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 0 \
-applies_to outputs
# The signals that need to be clamped HIGH
set_isolation iso_high1 -domain PD_SYS \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 1 \
-elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleeping_o \
u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleep_deep_o}
set_isolation_control iso_low1 -domain PD_SYS \
-isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
-isolation_sense low \
-location parent
set_isolation_control iso_high1 -domain PD_SYS \
-isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
-isolation_sense low \
-location parent
set_isolation iso_low2 -domain PD_DBG \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 0 \
-applies_to outputs
set_isolation_control iso_low2 -domain PD_DBG \
-isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGISOLATEn \
-isolation_sense low \
-location parent
################################################################################
# Set Retention
################################################################################
set_retention drff -domain PD_SYS -retention_power_net VDD -retention_ground_net VSS
set_retention_control drff -domain PD_SYS -save_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn high} \
-restore_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn low}
map_retention_cell drff -domain PD_SYS -lib_cell_type DRFF
################################################################################
# Define port states
################################################################################
add_port_state VSS -state {on 0.0 0.0 0.0}
add_port_state VDD -state {on 0.81 0.9 0.99}
add_port_state VDDACC -state {on 0.81 0.9 0.99}
add_port_state uswitch1/VDD_SYS -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
add_port_state uswitch2/VDD_DBG -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
################################################################################
# Define power state table
################################################################################
create_pst cm0_pst -supplies {VSS VDD VDD_SYS VDD_DBG VDDACC}
add_pst_state run -pst cm0_pst -state {on on on off on }
add_pst_state slp -pst cm0_pst -state {on on off off on }
add_pst_state dbg -pst cm0_pst -state {on on on on on }
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# Import verilog and setup libraries
set_host_options -max_cores 8 -num_processes 8
# Set paths !!! Please edit for your system !!!
set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
set TLU_cbest $TLU_dir/cbest.tluplus
set TLU_cbest_T $TLU_dir/cbest_T.tluplus
set TLU_cworst_T $TLU_dir/cworst_T.tluplus
set TLU_cworst $TLU_dir/cworst.tluplus
set TLU_rcbest_T $TLU_dir/rcbest_T.tluplus
set TLU_rcbest $TLU_dir/rcbest.tluplus
set TLU_rcworst_T $TLU_dir/rcworst_T.tluplus
set TLU_rcworst $TLU_dir/rcworst.tluplus
set TLU_typical $TLU_dir/typical.tluplus
set TLU_map $TLU_dir/tluplus.map
#Create the design library
create_lib nanosoc_chip_pads.dlib \
-technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf \
-ref_libs {../libs/cln28ht/ ../libs/cln28ht_pmk/ ../libs/cln28ht_ret/ ../libs/sram_16k/ ../libs/sram_32k/ ../libs/sram_64k/ ../libs/rom_via/ ../libs/io_lib/ ../libs/pad_lib/ ../libs/bump_lib/}
source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
elaborate nanosoc_chip_pads
set_top_module nanosoc_chip_pads
redirect -tee -file ../logs/lib_cell_summary.log {report_lib -cell_summary cln28ht}
redirect -tee -file ../logs/lib_cell_pmk_summary.log {report_lib -cell_summary cln28ht_pmk}
redirect -tee -file ../logs/lib_cell_ret_summary.log {report_lib -cell_summary cln28ht_ret}
redirect -tee -file ../logs/lib_cell_bump_summary.log {report_lib -cell_summary bump_lib}
remove_modes -all
remove_corners -all
remove_scenarios -all
read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name cbest_T -tlup $TLU_cbest_T -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name cworst_T -tlup $TLU_cworst_T -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcbest_T -tlup $TLU_rcbest_T -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcworst_T -tlup $TLU_rcworst_T -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name typical -tlup $TLU_typical -layermap $TLU_map -sanity_check advanced
set_technology -node 28
## Setup scenarios as below
create_mode hold_mode
create_corner hold_corner
create_scenario -name hold_scenario -mode hold_mode -corner hold_corner
set_scenario_status hold_scenario -none -setup false -hold true -leakage_power true -dynamic_power false -max_transition true -max_capacitance false -min_capacitance true -active true
set_app_options -name time.convert_constraint_from_bc_wc -value bc_only
read_sdc ../../../constraints.sdc
create_mode setup_mode
create_corner setup_corner
create_scenario -name setup_scenario -mode setup_mode -corner setup_corner
set_scenario_status setup_scenario -none -setup true -hold false -leakage_power true -dynamic_power true -max_transition true -max_capacitance true -min_capacitance false -active true
set_app_options -name time.convert_constraint_from_bc_wc -value wc_only
read_sdc ../../../constraints.sdc
set_app_options -name time.convert_constraint_from_bc_wc -value none
## hold - FFGNP V=+10% T=-40 and 125, parasitics cworst cbest rcworst rcbest
# SSSGNP V=-10%, T=-40 and 125, parasitics cworst and rcworst
current_corner hold_corner
set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
set_temperature 125 -min -40 -corners hold_corner
set_voltage 0.81 -min 0.99 -corners hold_corner
## setup SSGNP V=-10%, T=-40 parasitics cworst_t rcworst_t
# TT V=-10%, T=85C parasitics cworst_t rcworst_t
current_corner setup_corner
set_parasitic_parameters -early_spec cworst_T -early_temperature -40 -late_spec rcworst_T -late_temperature 125 -library nanosoc_chip_pads.dlib
set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min tt_ctypical_max_0p90v_25c
set_temperature 85 -min -40 -corners setup_corner
set_voltage 0.81 -corners setup_corner
## max transition - SSGNP V=-10% T=-40 P=cworst_t rcworst_t
## typical power - TT V=V T=85C P=ctypical
# Max IR drop - FFG V=V T=125 P=cworst
# Signal EM - FFG V=V T=125 P=rcworst_c cworst_T
redirect -file ../reports/design_setup.report_scenarios.rpt {report_scenarios}
save_block nanosoc_cip_pads
save_lib nanosoc_chip_pads.dlib
initialize_floorplan -control_type die -use_site_row -side_length {1111.1111 1611.11111} -core_offset {180}
source ../floorplan/fp.tcl
remove_io_guides -all
create_io_ring -name main_io -pad_cell_list {uPAD_CLK_I uPAD_NRST_I uPAD_P0_00 uPAD_P0_01 uPAD_P0_02 uPAD_P0_03 uPAD_P0_04 uPAD_P0_05 uPAD_P0_06 uPAD_P0_07 uPAD_P1_00 uPAD_P1_01 uPAD_P1_02 uPAD_P1_03 uPAD_P1_04 uPAD_P1_05 uPAD_P1_06 uPAD_P1_07 uPAD_SE_I uPAD_SWDCK_I uPAD_SWDIO_IO uPAD_TEST_I uPAD_VDDACC_0 uPAD_VDDACC_1 uPAD_VDDACC_2 uPAD_VDDIO_0 uPAD_VDDIO_2 uPAD_VDDIO_3 uPAD_VDD_0 uPAD_VDD_1 uPAD_VDD_2 uPAD_VDD_3 uPAD_VSSIO_0 uPAD_VSSIO_1 uPAD_VSS_0 uPAD_VSS_1 uPAD_VSS_2 uPAD_VSS_3}
create_io_corner_cell {main_io.left main_io.top} -reference_cell PCORNER_G
create_io_corner_cell {main_io.bottom main_io.left} -reference_cell PCORNER_G
create_io_corner_cell {main_io.top main_io.right} -reference_cell PCORNER_G
create_io_corner_cell {main_io.right main_io.bottom} -reference_cell PCORNER_G
place_io
create_io_filler_cells -io_guides [get_io_guides {main_io.top main_io.right main_io.bottom main_io.left}] -reference_cells PFILLER5_G -prefix io_filler
create_io_filler_cells -io_guides [get_io_guides {main_io.top main_io.right main_io.bottom main_io.left}] -reference_cells PFILLER0005_G -prefix io_filler
# Power Plan
load_upf ../scripts/nanosoc_chip_pads.upf
create_voltage_area -power_domains ACCEL
# create_voltage_area -power_domains PD_DBG
# create_voltage_area -power_domains PD_SYS
create_voltage_area_shape -voltage_area ACCEL \
-region {{{180.500 180.000} {925.150 1000.000}}} \
-guard_band {2 2}
#create_voltage_area_shape -voltage_area PD_DBG \
# -region {{{140.000 673.000} {464.150 970.400}}} \
# -guard_band {2 2}
#create_voltage_area_shape -voltage_area PD_SYS \
# -region {{{594.440 523.900} {1012.365 970.400}}} \
# -guard_band {2 2}
create_pg_region {pg_accel} -voltage_area {ACCEL}
# create_pg_region {pg_dbg} -voltage_area {PD_DBG}
# create_pg_region {pg_sys} -voltage_area {PD_SYS}
source ../scripts/power_plan.tcl
save_block
save_lib nanosoc_chip_pads.dlib
set topMetalLayer 8;
set RDLMetal AP;
set RDLVia RV;
remove_antenna_rules
define_antenna_layer_rule \
-mode 4 \
-layer "$RDLMetal" \
-ratio 2000 \
-diode_ratio {0.000025 0 8000 30000}
define_antenna_rule \
-mode 1 \
-diode_mode 4 \
-metal_ratio 0 \
-cut_ratio 20
define_antenna_layer_rule \
-mode 1 \
-layer "M$topMetalLayer" \
-ratio 5000 \
-diode_ratio {0.000025 0 8000 50000}
define_antenna_layer_rule \
-mode 1 \
-layer "$RDLVia" \
-ratio 200 \
-diode_ratio {0.000025 0 83 400}
for {set i 1} {$i < $topMetalLayer} {incr i} {
define_antenna_layer_rule \
-mode 1 \
-layer "VIA$i" \
-ratio 20 \
-diode_ratio {0.000025 0 210 900}
}
define_antenna_rule \
-mode 2 \
-diode_mode 4 \
-metal_ratio 0 \
-cut_ratio 0
for {set i 1} {$i < $topMetalLayer} {incr i} {
define_antenna_layer_rule \
-mode 2 \
-layer "M$i" \
-ratio 5000 \
-diode_ratio {0.000025 0 456 43000}
}
define_antenna_layer_rule \
-mode 2 \
-layer "M$topMetalLayer" \
-ratio 5000 \
-diode_ratio {0.000025 0 8000 50000}
for {set i 1} {$i < $topMetalLayer} {incr i} {
define_antenna_layer_rule \
-mode 2 \
-layer "VIA$i" \
-ratio 900 \
-diode_ratio {0.000025 0 210 900}
}
##### Routing Option Related to Antenna Fixing #####
set_parameter -name doAntennaConx -value 4 -module droute
redirect -tee -file ../reports/antenna_rules.rpt {report_antenna_rules}
set_voltage -min 0.99 -corners hold_corner -object_list [get_supply_nets {VDD}] 0.81
set_voltage -min 0.99 -corners hold_corner -object_list [get_supply_nets {VDDACC}] 0.81
set_voltage -min 1.98 -corners hold_corner -object_list [get_supply_nets {AVDDHV}] 1.62
set_voltage -min 0.99 -corners hold_corner -object_list [get_supply_nets {AVDD}] 0.81
set_voltage -min 0.0 -corners hold_corner -object_list [get_supply_nets {VSS}] 0.0
set_voltage -min 0.0 -corners hold_corner -object_list [get_supply_nets {AGND}] 0.0
set_voltage -corners setup_corner -object_list [get_supply_nets {VDD}] 0.81
set_voltage -corners setup_corner -object_list [get_supply_nets {VDDACC}] 0.81
set_voltage -corners setup_corner -object_list [get_supply_nets {AVDDHV}] 1.62
set_voltage -corners setup_corner -object_list [get_supply_nets {AVDD}] 0.81
set_voltage -corners setup_corner -object_list [get_supply_nets {VSS}] 0.0
set_voltage -corners setup_corner -object_list [get_supply_nets {AGND}] 0.0
redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_nanosoc_chip u_nanosoc_chip_cfg}]
explore_logic_hierarchy -place -rectangular
save_block
save_lib nanosoc_chip_pads.dlib
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open_lib nanosoc_chip_pads.dlib/
open_block nanosoc_chip_pads
set_host_options -max_cores 16 -num_processes 16
set REPORT_DIR ../reports
set LOG_DIR ../logs
set_qor_strategy -stage synthesis -metric timing
# Compile fusion takes about 6.5 hrs to run
set_stage -step synthesis
compile_fusion -to initial_opto
redirect -tee -file $REPORT_DIR/timing_02a_initial_opto_max.rep {report_timing -delay_type max}
redirect -tee -file $REPORT_DIR/timing_02a_initial_opto_min.rep {report_timing -delay_type min}
save_block
set_stage -step compile_place
compile_fusion -from final_place
redirect -tee -file $REPORT_DIR/timing_02b_compile_fusion_max.rep {report_timing -delay_type max}
redirect -tee -file $REPORT_DIR/timing_02b_compile_fusion_min.rep {report_timing -delay_type min}
redirect -tee -file $REPORT_DIR/qor_02_compile_fusion.rep {report_qor}
save_block
save_lib nanosoc_chip_pads.dlib
exit
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open_lib nanosoc_chip_pads.dlib/
open_block nanosoc_chip_pads
set_host_options -max_cores 16 -num_processes 16
set REPORT_DIR ../reports
set LOG_DIR ../logs
# Clock opt cts
set_stage -step cts
clock_opt -from build_clock -to build_clock
redirect -tee -file $REPORT_DIR/timing_03a_CTS_max.rep {report_timing -delay_type max}
redirect -tee -file $REPORT_DIR/timing_03a_CTS_min.rep {report_timing -delay_type min}
save_block
clock_opt -from route_clock -to route_clock
redirect -tee -file $REPORT_DIR/timing_03b_CTS_max.rep {report_timing -delay_type max}
redirect -tee -file $REPORT_DIR/timing_03b_CTS_min.rep {report_timing -delay_type min}
save_block
set_app_options -name time.aocvm_enable_analysis -value true ;
set_stage -step post_cts_opto
clock_opt -from final_opto -to final_opto
redirect -tee -file $REPORT_DIR/timing_03c_CTS_max.rep {report_timing -delay_type max}
redirect -tee -file $REPORT_DIR/timing_03c_CTS_min.rep {report_timing -delay_type min}
redirect -tee -file $REPORT_DIR/qor_03_CTS.rep {report_qor}
save_block
save_lib nanosoc_chip_pads.dlib
exit
\ No newline at end of file
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open_lib nanosoc_chip_pads.dlib/
open_block nanosoc_chip_pads
set_host_options -max_cores 16 -num_processes 16
set REPORT_DIR ../reports
set LOG_DIR ../logs
set_stage -step route
route_auto
redirect -tee -file $REPORT_DIR/timing_04a_route_auto_max.rep {report_timing -delay_type max}
redirect -tee -file $REPORT_DIR/timing_04a_route_auto_min.rep {report_timing -delay_type min}
set_stage -step post_route
route_opt
redirect -tee -file $REPORT_DIR/timing_04b_route_opt_max.rep {report_timing -delay_type max}
redirect -tee -file $REPORT_DIR/timing_04b_route_opt_min.rep {report_timing -delay_type min}
redirect -tee -file $REPORT_DIR/qor_04_route.rep {report_qor}
save_block
save_lib nanosoc_chip_pads.dlib
exit
\ No newline at end of file
ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/io_plan.tcl 0 → 100644
+ 15
− 0
View file @ 18ea18ce
remove_io_guides -all
create_io_guide -name {main_io.top} -side top -line {{110.000 2639.600} 1950.94} -offset {0.000 0.000} -pad_cells [list ]
create_io_guide -name {main_io.bottom} -side bottom -line {{2060.940 0.000} 1950.94} -offset {0.000 0.000} -pad_cells [list ]
create_io_guide -name {main_io.left} -side left -line {{0.000 110.000} 2419.6} -offset {0.000 0.000} -pad_cells [list ]
create_io_guide -name {main_io.right} -side right -line {{2170.940 2529.600} 2419.6} -offset {0.000 0.000} -pad_cells [list ]
create_io_corner_cell {main_io.left main_io.top} -reference_cell PCORNER_G
create_io_corner_cell {main_io.bottom main_io.left} -reference_cell PCORNER_G
create_io_corner_cell {main_io.top main_io.right} -reference_cell PCORNER_G
create_io_corner_cell {main_io.right main_io.bottom} -reference_cell PCORNER_G
place_io
ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/nanosoc_chip_pads.upf 0 → 100644
+ 169
− 0
View file @ 18ea18ce
################################################################################
# Create power domains
################################################################################
create_power_domain TOP
create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
#create_power_domain PD_SYS -elements u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys
#create_power_domain PD_DBG -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_dbg \
# u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_dap/u_ap}
################################################################################
# Create and logically connect power ports and nets
################################################################################
# Always on VDD
create_supply_port VDD
create_supply_net VDD -domain TOP
#create_supply_net VDD -domain PD_SYS -reuse
#create_supply_net VDD -domain PD_DBG -reuse
connect_supply_net VDD -ports VDD
# Ground
create_supply_port VSS
create_supply_net VSS -domain TOP
#create_supply_net VSS -domain PD_SYS -reuse
#create_supply_net VSS -domain PD_DBG -reuse
create_supply_net VSS -domain ACCEL -reuse
connect_supply_net VSS -ports VSS
# Switched VDD
#create_supply_net VDD_SYS -domain PD_SYS -resolve parallel
#create_supply_net VDD_DBG -domain PD_DBG -resolve parallel
# VDDACC
create_supply_port VDDACC
create_supply_net VDDACC -domain ACCEL
connect_supply_net VDDACC -ports VDDACC
create_supply_port AVDD
create_supply_net AVDD -domain TOP
connect_supply_net AVDD -ports AVDD
create_supply_port AVDDHV
create_supply_net AVDDHV -domain TOP
connect_supply_net AVDDHV -ports AVDDHV
create_supply_port AGND
create_supply_net AGND -domain TOP
connect_supply_net AGND -ports AGND
################################################################################
# Assign power supplies to power domains
################################################################################
set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
#set_domain_supply_net PD_SYS -primary_power_net VDD_SYS -primary_ground_net VSS
#set_domain_supply_net PD_DBG -primary_power_net VDD_DBG -primary_ground_net VSS
################################################################################
# Create Power Switches
################################################################################
#create_power_switch uswitch1 -domain PD_SYS \
# -input_supply_port {VDD VDD} \
# -output_supply_port {VDD_SYS VDD_SYS} \
# -control_port {SYSPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWN} \
# -ack_port {SYSPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSPWRDOWNACK {SYSPWRDOWN}} \
# -ack_delay {SYSPWRDOWNACK 65000} \
# -on_state {on_state VDD {!SYSPWRDOWN}} \
# -off_state {off_state { SYSPWRDOWN}}
#
#create_power_switch uswitch2 -domain PD_DBG \
# -input_supply_port {VDD VDD} \
# -output_supply_port {VDD_DBG VDD_DBG} \
# -control_port {DBGPWRDOWN u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWN} \
# -ack_port {DBGPWRDOWNACK u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGPWRDOWNACK {DBGPWRDOWN}} \
# -ack_delay {DBGPWRDOWNACK 65000} \
# -on_state {on_state VDD {!DBGPWRDOWN}} \
# -off_state {off_state { DBGPWRDOWN}}
#
################################################################################
# Set Isolation Controls
# - iso_low1, iso_high1 at PD_SYS outputs
# - iso_low2 at PD_DBG outputs
################################################################################
#set_isolation iso_low1 -domain PD_SYS \
# -isolation_power_net VDD \
# -isolation_ground_net VSS \
# -clamp_value 0 \
# -applies_to outputs
# The signals that need to be clamped HIGH
#set_isolation iso_high1 -domain PD_SYS \
# -isolation_power_net VDD \
# -isolation_ground_net VSS \
# -clamp_value 1 \
# -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleeping_o \
# u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0/u_top/u_sys/sleep_deep_o}
#
#set_isolation_control iso_low1 -domain PD_SYS \
# -isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
# -isolation_sense low \
# -location parent
#
#set_isolation_control iso_high1 -domain PD_SYS \
# -isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSISOLATEn \
# -isolation_sense low \
# -location parent
#
#set_isolation iso_low2 -domain PD_DBG \
# -isolation_power_net VDD \
# -isolation_ground_net VSS \
# -clamp_value 0 \
# -applies_to outputs
#
#set_isolation_control iso_low2 -domain PD_DBG \
# -isolation_signal u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/DBGISOLATEn \
# -isolation_sense low \
# -location parent
#
################################################################################
# Set Retention
################################################################################
#set_retention drff -domain PD_SYS -retention_power_net VDD -retention_ground_net VSS
#set_retention_control drff -domain PD_SYS -save_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn high} \
# -restore_signal {u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_core_prmu/u_cortexm0_pmu/SYSRETAINn low}
#
#map_retention_cell drff -domain PD_SYS -lib_cells [list DRFFQ_X1M_A12PP140ZTLTS_C30C35 \
# DRFFQ_X2M_A12PP140ZTLTS_C30C35 \
# DRFFQ_X3M_A12PP140ZTLTS_C30C35 \
# DRFFQ_X4M_A12PP140ZTLTS_C30C35 \
# DRFFRPQ_X1M_A12PP140ZTLTS_C30C35 \
# DRFFRPQ_X2M_A12PP140ZTLTS_C30C35 \
# DRFFRPQ_X3M_A12PP140ZTLTS_C30C35 \
# DRFFRPQ_X4M_A12PP140ZTLTS_C30C35 \
# DRFFSQ_X1M_A12PP140ZTLTS_C30C35 \
# DRFFSQ_X2M_A12PP140ZTLTS_C30C35 \
# DRFFSQ_X3M_A12PP140ZTLTS_C30C35 \
# DRFFSQ_X4M_A12PP140ZTLTS_C30C35]
################################################################################
# Define port states
################################################################################
add_port_state VSS -state {on 0.0 0.0 0.0}
add_port_state VDD -state {on 0.81 0.9 0.99}
add_port_state VDDACC -state {on 0.81 0.9 0.99}
# add_port_state uswitch1/VDD_SYS -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
# add_port_state uswitch2/VDD_DBG -state {on 0.81 0.9 0.99} -state {off 0.0 0.0 0.0}
add_port_state AVDD -state {on 0.81 0.9 0.99}
add_port_state AVDDHV -state {on 1.62 1.8 1.98}
add_port_state AGND -state {on 0.0 0.0 0.0}
################################################################################
# Define power state table
################################################################################
# create_pst cm0_pst -supplies {VSS VDD VDD_SYS VDD_DBG VDDACC AVDD AVDDHV }
# add_pst_state run -pst cm0_pst -state {on on on off on on on }
# add_pst_state slp -pst cm0_pst -state {on on off off on on on }
# add_pst_state dbg -pst cm0_pst -state {on on on on on on on }
create_pst cm0_pst -supplies {VSS VDD VDDACC AVDD AVDDHV }
add_pst_state run -pst cm0_pst -state {on on on on on }
ASIC/TSMC28nm/38pin/Synopsys_FC/power_plan.tcl → ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/power_plan.tcl
+ 29
− 0
View file @ 18ea18ce
......@@ -2,27 +2,28 @@ connect_pg_net -create_nets_only
connect_pg_net -automatic
create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2}\
-vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VDDACC VSS}} {offset: {3 3}}} -core
-vertical_layer M6 -vertical_width {4} -vertical_spacing {2} -nets {AGND AVDD AVDDHV VDD VSS}
set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS VDDACC AVDD AVDDHV AGND}} {offset: {3 3}}} -core
compile_pg -strategies core_ring
create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
{{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VDDACC VSS}}} -core
compile_pg -strategies M5M8_mesh
create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M6} {width: 4} {pitch: 30.566} {offset: 21.5}} \
{{horizontal_layer: M5} {width: 4} {pitch: 30} {offset: 20}}}
set_pg_strategy M5M6_mesh -pattern {{name: mesh_pattern} {nets: {VDD VDDACC VSS}}} -core -extension {{{stop : first_target}}}
compile_pg -strategies M5M6_mesh
create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
create_pg_std_cell_conn_pattern std_pattern -layers {M2} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
set_pg_strategy std_cell_accel -voltage_areas ACCEL -pattern {{name : std_pattern}{nets : {VDDACC VSS}}}
set_pg_strategy std_cell_dbg -voltage_areas PD_DBG -pattern {{name : std_pattern}{nets : {VDD_DBG VSS}}}
set_pg_strategy std_cell_sys -voltage_areas PD_SYS -pattern {{name : std_pattern}{nets : {VDD_SYS VSS}}}
#set_pg_strategy std_cell_dbg -voltage_areas PD_DBG -pattern {{name : std_pattern}{nets : {VDD_DBG VSS}}}
#set_pg_strategy std_cell_sys -voltage_areas PD_SYS -pattern {{name : std_pattern}{nets : {VDD_SYS VSS}}}
set_pg_strategy std_cell_strat -voltage_areas DEFAULT_VA -pattern {{name: std_pattern} {nets: {VDD VSS}}}
compile_pg -strategies std_cell_accel
compile_pg -strategies std_cell_dbg
compile_pg -strategies std_cell_sys
#compile_pg -strategies std_cell_dbg
#compile_pg -strategies std_cell_sys
compile_pg -strategies std_cell_strat
ASIC/TSMC28nm/38pin/Synopsys_FC/synopsys_lib_conversion.tcl → ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/synopsys_lib_conversion.tcl
+ 262
− 0
View file @ 18ea18ce
......@@ -35,25 +35,66 @@ set ret_antenna_file $ret_base_path/milkyway/1p8m_5x2z_ut
# IO Paths
set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
set tphn28hpcpgv18_lef_file $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/6lm/lef/tphn28hpcpgv18_6lm.lef
set tphn28hpcpgv18_lib_path $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
set tphn28hpcpgv18_lef_file $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/9lm/lef/tphn28hpcpgv18_9lm.lef
set tphn28hpcpgv18_lib_path $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
set IO_TT_0p9v_1p8v_25c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18tt0p9v1p8v25c.db
set IO_FF_0p99v_1p98v_m40c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ffg0p99v1p98vm40c.db
set IO_SS_0p81v_1p62v_125c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ssg0p81v1p62v125c.db
set pad_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
set pad_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
set bump_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/fc/fc_eu/MTRDL/8m/8M_Z/lef/tpbn28v_8lm.lef
# SRAM files (using Arm compiler)
set sram_16k_path $env(SOCLABS_PROJECT_DIR)/memories/sram_16k
set sram_16k_lef_file $sram_16k_path/sram_16k.lef
set sram_16k_gds_file $sram_16k_path/sram_16k.gds2
set sram_16k_lib_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
set sram_16k_lib_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
set sram_16k_lib_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.lib
set sram_16k_lib_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_16k_db_file_ss_0p81v_125c $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db
set sram_16k_db_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.db
set sram_16k_db_file_tt_0p90v_25c $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.db
set sram_16k_db_file_ff_0p99v_m40c $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db
set sram_32k_path $env(SOCLABS_PROJECT_DIR)/memories/sram_32k
set sram_32k_lef_file $sram_32k_path/sram_32k.lef
set sram_32k_gds_file $sram_32k_path/sram_32k.gds2
set sram_32k_lib_file_ss_0p81v_125c $sram_32k_path/sram_32k_ssg_cworstt_0p81v_0p81v_125c.lib
set sram_32k_lib_file_tt_0p90v_25c $sram_32k_path/sram_32k_tt_ctypical_0p90v_0p90v_25c.lib
set sram_32k_lib_file_ff_0p99v_m40c $sram_32k_path/sram_32k_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_32k_db_file_ss_0p81v_125c $sram_32k_path/sram_32k_ssg_cworstt_0p81v_0p81v_125c.db
set sram_32k_db_file_tt_0p90v_25c $sram_32k_path/sram_32k_tt_ctypical_0p90v_0p90v_25c.db
set sram_32k_db_file_ff_0p99v_m40c $sram_32k_path/sram_32k_ffg_cbestt_0p99v_0p99v_m40c.db
set sram_64k_path $env(SOCLABS_PROJECT_DIR)/memories/sram_64k
set sram_64k_lef_file $sram_64k_path/sram_64k.lef
set sram_64k_gds_file $sram_64k_path/sram_64k.gds2
set sram_64k_lib_file_ss_0p81v_125c $sram_64k_path/sram_64k_ssg_cworstt_0p81v_0p81v_125c.lib
set sram_64k_lib_file_tt_0p90v_25c $sram_64k_path/sram_64k_tt_ctypical_0p90v_0p90v_25c.lib
set sram_64k_lib_file_ff_0p99v_m40c $sram_64k_path/sram_64k_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_64k_db_file_ss_0p81v_125c $sram_64k_path/sram_64k_ssg_cworstt_0p81v_0p81v_125c.db
set sram_64k_db_file_tt_0p90v_25c $sram_64k_path/sram_64k_tt_ctypical_0p90v_0p90v_25c.db
set sram_64k_db_file_ff_0p99v_m40c $sram_64k_path/sram_64k_ffg_cbestt_0p99v_0p99v_m40c.db
set sram_flash_data_path $env(SOCLABS_PROJECT_DIR)/memories/sram_flash_data
set sram_flash_cache_lef_file $sram_flash_data_path/sram_flash_cache.lef
set sram_flash_cache_gds_file $sram_flash_data_path/sram_flash_cache.gds2
set sram_flash_cache_lib_file_ss_0p81v_125c $sram_flash_data_path/sram_flash_cache_ssg_cworstt_0p81v_0p81v_125c.lib
set sram_flash_cache_lib_file_tt_0p90v_25c $sram_flash_data_path/sram_flash_cache_tt_ctypical_0p90v_0p90v_25c.lib
set sram_flash_cache_lib_file_ff_0p99v_m40c $sram_flash_data_path/sram_flash_cache_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_flash_cache_db_file_ss_0p81v_125c $sram_flash_data_path/sram_flash_cache_ssg_cworstt_0p81v_0p81v_125c.db
set sram_flash_cache_db_file_tt_0p90v_25c $sram_flash_data_path/sram_flash_cache_tt_ctypical_0p90v_0p90v_25c.db
set sram_flash_cache_db_file_ff_0p99v_m40c $sram_flash_data_path/sram_flash_cache_ffg_cbestt_0p99v_0p99v_m40c.db
set sram_flash_tag_path $env(SOCLABS_PROJECT_DIR)/memories/sram_flash_tag
set sram_flash_tag_lef_file $sram_flash_tag_path/sram_flash_tag.lef
set sram_flash_tag_gds_file $sram_flash_tag_path/sram_flash_tag.gds2
set sram_flash_tag_lib_file_ss_0p81v_125c $sram_flash_tag_path/sram_flash_tag_ssg_cworstt_0p81v_0p81v_125c.lib
set sram_flash_tag_lib_file_tt_0p90v_25c $sram_flash_tag_path/sram_flash_tag_tt_ctypical_0p90v_0p90v_25c.lib
set sram_flash_tag_lib_file_ff_0p99v_m40c $sram_flash_tag_path/sram_flash_tag_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_flash_tag_db_file_ss_0p81v_125c $sram_flash_tag_path/sram_flash_tag_ssg_cworstt_0p81v_0p81v_125c.db
set sram_flash_tag_db_file_tt_0p90v_25c $sram_flash_tag_path/sram_flash_tag_tt_ctypical_0p90v_0p90v_25c.db
set sram_flash_tag_db_file_ff_0p99v_m40c $sram_flash_tag_path/sram_flash_tag_ffg_cbestt_0p99v_0p99v_m40c.db
# ROM Files (using arm Compiler)
set rom_path $env(SOCLABS_PROJECT_DIR)/memories/bootrom
set rom_via_lef_file $rom_path/rom_via.lef
......@@ -65,6 +106,33 @@ set rom_via_db_file_ss_0p81v_125c $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_12
set rom_via_db_file_tt_0p90v_25c $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
set rom_via_db_file_ff_0p99v_m40c $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db
# Synopsys PLL files
set Synopsys_PLL_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro
set Synopsys_PLL_lef_file $Synopsys_PLL_dir/lef/5m4x0z/dwc_z19606ts_ns_merged.lef
set Synopsys_PLL_db_file $Synopsys_PLL_dir/timing/lib_pg/dwc_z19606ts_ns_ssg0p81v125c_cworst_pg.db
set Synopsys_PLL_gds_file $Synopsys_PLL_dir/gds/5m4x0z/dwc_z19606ts_ns.gds
# Synopsys Temperature sensor files
set Synopsys_TS_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/1.01b
set Synopsys_TS_lef_file $Synopsys_TS_dir/lef/mr74127.lef
set Synopsys_TS_lib_file $Synopsys_TS_dir/liberty/mr74127_wc_vmin_125c.lib
set Synopsys_TS_db_file $Synopsys_TS_dir/db/mr74127_wc_vmin_125c.db
set Synopsys_TS_gds_file $Synopsys_TS_dir/gdsii/mr74127_v1r1.gds
# Synopsys Process detector Files
set Synopsys_PD_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_pd_tsmc28hpcp_1.00a/synopsys/dwc_sensors_pd_tsmc28hpcp/1.00a
set Synopsys_PD_lef_file $Synopsys_PD_dir/lef/mr74125.lef
set Synopsys_PD_lib_file $Synopsys_PD_dir/liberty/mr74125_wc_vmin_125c.lib
set Synopsys_PD_db_file $Synopsys_PD_dir/db/mr74125_wc_vmin_125c.db
set Synopsys_PD_gds_file $Synopsys_PD_dir/gds/mr74125_v1r2.gds
# Synopsys Voltage Monitor files
set Synopsys_VM_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_vm_shrink_tsmc28hpcp_1.00a/synopsys/dwc_sensors_vm_shrink_tsmc28hpcp/1.00a
set Synopsys_VM_lef_file $Synopsys_VM_dir/lef/mr74140.lef
set Synopsys_VM_lib_file $Synopsys_VM_dir/liberty/mr74140_wc_vmin_125c.lib
set Synopsys_VM_db_file $Synopsys_VM_dir/db/mr74140_wc_vmin_125c.db
set Synopsys_VM_gds_file $Synopsys_VM_dir/gdsii/mr74140_v1r1.gds
# Create standard cell fusion library
create_fusion_lib -dbs [list $standard_cell_db_file_ss_0p81v_125C $standard_cell_db_file_tt_0p90v_25C $standard_cell_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $standard_cell_lef_file] -technology $cln28ht_tech_file cln28ht
save_fusion_lib cln28ht
......@@ -86,7 +154,7 @@ write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db SRAM_16K_ssg_cworst
close_lib -all
read_lib $sram_16k_lib_file_tt_0p90v_25c
write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_85c
write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_25c
close_lib -all
read_lib $sram_16k_lib_file_ff_0p99v_m40c
......@@ -97,6 +165,40 @@ create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_t
save_fusion_lib sram_16k
close_fusion_lib sram_16k
# 32K SRAM
read_lib $sram_32k_lib_file_ss_0p81v_125c
write_lib -output $sram_32k_db_file_ss_0p81v_125c -format db SRAM_32K_ssg_cworstt_0p81v_0p81v_125c
close_lib -all
read_lib $sram_32k_lib_file_tt_0p90v_25c
write_lib -output $sram_32k_db_file_tt_0p90v_25c -format db SRAM_32K_tt_ctypical_0p90v_0p90v_25c
close_lib -all
read_lib $sram_32k_lib_file_ff_0p99v_m40c
write_lib -output $sram_32k_db_file_ff_0p99v_m40c -format db SRAM_32K_ffg_cbestt_0p99v_0p99v_m40c
close_lib -all
create_fusion_lib -dbs [list $sram_32k_db_file_ss_0p81v_125c $sram_32k_db_file_tt_0p90v_25c $sram_32k_db_file_ff_0p99v_m40c] -lefs $sram_32k_lef_file -technology $cln28ht_tech_file sram_32k
save_fusion_lib sram_32k
close_fusion_lib sram_32k
# 64K SRAM
read_lib $sram_64k_lib_file_ss_0p81v_125c
write_lib -output $sram_64k_db_file_ss_0p81v_125c -format db SRAM_64K_ssg_cworstt_0p81v_0p81v_125c
close_lib -all
read_lib $sram_64k_lib_file_tt_0p90v_25c
write_lib -output $sram_64k_db_file_tt_0p90v_25c -format db SRAM_64K_tt_ctypical_0p90v_0p90v_25c
close_lib -all
read_lib $sram_64k_lib_file_ff_0p99v_m40c
write_lib -output $sram_64k_db_file_ff_0p99v_m40c -format db SRAM_64K_ffg_cbestt_0p99v_0p99v_m40c
close_lib -all
create_fusion_lib -dbs [list $sram_64k_db_file_ss_0p81v_125c $sram_64k_db_file_tt_0p90v_25c $sram_64k_db_file_ff_0p99v_m40c] -lefs $sram_64k_lef_file -technology $cln28ht_tech_file sram_64k
save_fusion_lib sram_64k
close_fusion_lib sram_64k
# Boot ROM
read_lib $rom_via_lib_file_ss_0p81v_125c
write_lib -output $rom_via_db_file_ss_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
......@@ -119,8 +221,42 @@ create_fusion_lib -dbs [list $IO_SS_0p81v_1p62v_125c_db $IO_TT_0p9v_1p8v_25c_db
save_fusion_lib io_lib
close_fusion_lib io_lib
# Pad Lib
# Synopsys PLL
create_fusion_lib -dbs $Synopsys_PLL_db_file -lefs $Synopsys_PLL_lef_file -technology $cln28ht_tech_file Synopsys_PLL
save_fusion_lib Synopsys_PLL
close_fusion_lib Synopsys_PLL
# Synopsys TS
read_lib $Synopsys_TS_lib_file
write_lib -output $Synopsys_TS_db_file -format db mr74127_wc_vmin_125c
close_lib -all
create_fusion_lib -dbs $Synopsys_TS_db_file -lefs $Synopsys_TS_lef_file -technology $cln28ht_tech_file Synopsys_TS
save_fusion_lib Synopsys_TS
close_fusion_lib Synopsys_TS
# Synopsys PD
read_lib $Synopsys_PD_lib_file
write_lib -output $Synopsys_PD_db_file -format db mr74125_wc_vmin_125c
close_lib -all
create_fusion_lib -dbs $Synopsys_PD_db_file -lefs $Synopsys_PD_lef_file -technology $cln28ht_tech_file Synopsys_PD
save_fusion_lib Synopsys_PD
close_fusion_lib Synopsys_PD
# Synopsys VM
read_lib $Synopsys_VM_lib_file
write_lib -output $Synopsys_VM_db_file -format db mr74140_wc_vmin_125c
close_lib -all
create_fusion_lib -dbs $Synopsys_VM_db_file -lefs $Synopsys_VM_lef_file -technology $cln28ht_tech_file Synopsys_VM
save_fusion_lib Synopsys_VM
close_fusion_lib Synopsys_VM
# Pad Libs
create_fusion_lib -lefs $pad_lef_file -technology $cln28ht_tech_file pad_lib
save_fusion_lib pad_lib
close_fusion_lib pad_lib
create_fusion_lib -lefs $bump_lef_file -technology $cln28ht_tech_file bump_lib
save_fusion_lib bump_lib
close_fusion_lib bump_lib
exit
\ No newline at end of file
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