diff --git a/.gitignore b/.gitignore
index 97bd184e793fbe07c10dd140671c18dad0e88ca0..d9927db4adb432c29a0eae1a5a46a58a80217374 100644
--- a/.gitignore
+++ b/.gitignore
@@ -53,6 +53,10 @@ ASIC/*/*/Synopsys_FC/reports
 ASIC/*/*/Synopsys_FC/logs
 ASIC/*/*/Synopsys_FC/work
 
+ASIC/*/*/Cadence/outputs
+ASIC/*/*/Cadence/reports
+ASIC/*/*/Cadence/logs
+
 ASIC/Synopsys/Formality/FM_INFO/*
 ASIC/Synopsys/ICC2/CLIBs
 ASIC/Synopsys/ICC2/PreFrameCheck
diff --git a/ASIC/TSMC28nm/38pin/Cadence/inputs/nanosoc.cpf b/ASIC/TSMC28nm/38pin/Cadence/inputs/nanosoc.cpf
new file mode 100644
index 0000000000000000000000000000000000000000..f57a1ace58fd7473ee19d4cfe46bf7c5f776edf8
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/inputs/nanosoc.cpf
@@ -0,0 +1,23 @@
+set_cpf_version 1.1
+
+set_design nanosoc_chip_pads
+create_power_domain -name TOP -default
+create_power_domain -name ACCEL  -instances u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator
+
+create_nominal_condition -name nom -voltage 1.08
+
+create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
+
+create_ground_nets -nets VSS
+create_power_nets -nets VDD
+create_power_nets -nets VDDACC
+
+create_global_connection -net VSS -pins VSS
+create_global_connection -net VDD -pins VDD
+create_global_connection -net VDDACC -pins VDDACC
+
+update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
+update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+
+
+end_design
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/38pin/Cadence/makefile b/ASIC/TSMC28nm/38pin/Cadence/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..45000960ce8228ba55ff59fa140312a604cff7ed
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/makefile
@@ -0,0 +1,23 @@
+LIBS_DIR:=./libs
+REPORT_DIR:=./reports
+LOG_DIR:=./logs
+WORK_DIR:=./work
+
+make_directories:
+	mkdir -p $(LIBS_DIR)
+	mkdir -p $(REPORT_DIR)
+	mkdir -p $(LOG_DIR)
+	mkdir -p $(WORK_DIR)
+
+syn_genus:
+	cd $(WORK_DIR); genus -f ../scripts/genus.tcl;
+
+syn_genus_nodft:
+	cd $(WORK_DIR); genus -f ../scripts/genus_nodft.tcl;
+
+innovus_full:
+	cd $(WORK_DIR); innovus -f ../scripts/pnr_flow.tcl;
+
+
+all: generate_libs syn_genus innovus_full
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/clock_tree_synthesis.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/clock_tree_synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..20375984271297820027fd4b1fa40df65f927728
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/clock_tree_synthesis.tcl
@@ -0,0 +1,23 @@
+############################################
+# Script : Clock Tree Implementation
+# Date : 24th May 2023 
+# Author : Srimanth Tenneti 
+# Description : Implements the Clock Tree
+############################################ 
+
+### Buffer Cells 
+set_db cts_buffer_cells {*BUFH*}
+### Inverter Cells 
+set_db cts_inverter_cells {*INV*} 
+
+### Clock Tree Sepc 
+#create_clock_tree_spec -out_file design_clk.spec 
+
+### Creating a Clock Tree 
+ccopt_design 
+
+### Optimizing the design 
+optDesign -postCts 
+optDesign -postCts -hold 
+
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/design_import.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/design_import.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a34d1fedb9d3d492913b9e709309351de8402716
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/design_import.tcl
@@ -0,0 +1,52 @@
+#########################################
+# File : Design Import Logic 
+# Date : 22nd May 2022 
+# Author : Srimanth Tenneti 
+# Description : MMMC + Design Import 
+######################################### 
+
+### Settting PG Nets 
+set_db init_power_nets {VDD VDDIO VDDACC} 
+set_db init_ground_nets {VSS VSSIO} 
+
+### Processing MMMC 
+read_mmmc nanosoc.mmmc 
+
+# Set library paths 
+# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
+set TECH_LEF /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PRTF_EDI_N65_9M_6X1Z1U_RDL.24a.tlef
+#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
+set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
+set BASE_RVT_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_hvt/r0p0/lef/sc12_cln65lp_base_hvt.lef
+set PMK_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_pmk_rvt_hvt/r0p0/lef/sc12_cln65lp_pmk_rvt_hvt.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/iolib/tpbn65v_200b_FE/TSMCHOME/digital/Back_End/lef/tpbn65v_200b/cup/9m/9M_6X1Z1U/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Back_End/lef/tpdn65lpnv2od3_140b/mt_2/9lm/lef/tpdn65lpnv2od3_9lm.lef
+
+
+# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
+set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
+set RF_08K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.lef
+set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
+
+### Reading LEFs 
+read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${BASE_RVT_LEF} ${PMK_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${RF_08K_LEF} ${ROM_LEF}]
+
+### Reading Netlist 
+read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v
+
+### Read DEF scan chain
+#read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
+
+### Initializing the Design 
+init_design
+
+### Adjusting the GUI 
+gui_fit 
+
+#ungroup u_nanosoc_chip_u_system
+
+create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 2000.0 2500.0 140.0 140.0 140.0 140.0
+
+read_power_intent -cpf ../cpf/nanosoc_syn_out.cpf
+
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/design_import_noDFT.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/design_import_noDFT.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4b003a7999bb64364c1aff8656023d74ca606d7f
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/design_import_noDFT.tcl
@@ -0,0 +1,64 @@
+#########################################
+# File : Design Import Logic 
+# Date : 22nd May 2022 
+# Author : Srimanth Tenneti 
+# Description : MMMC + Design Import 
+######################################### 
+
+### Settting PG Nets 
+set init_pwr_net {VDD VDDIO VDDACC}
+set init_gnd_net {VSS VSSIO}
+
+### Processing MMMC 
+set init_mmmc_file {../scripts/nanosoc.mmmc}
+
+# Set library paths 
+# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
+set cln28ht_tech_path           /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set TECH_LEF                        $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.lef
+
+#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
+set standard_cell_base_path     /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+set BASE_LEF                  $standard_cell_base_path/lef/sc12mcpp140z_cln28ht_base_svt_c35.lef
+set TSMC_28NM_PDK_PATH          /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
+set IO_PAD_DRIVER_LEF     $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/9lm/lef/tphn28hpcpgv18_9lm.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
+
+
+# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
+set SRAM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/sram_16k/sram_16k.lef
+set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
+
+### Reading LEFs 
+set init_lef_file [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${SRAM_LEF} ${ROM_LEF}]
+
+### Reading Netlist 
+set init_top_cell {nanosoc_chip_pads}
+set init_verilog {../outputs/nanosoc_chip_pads_44pin.v}
+
+set init_cpf_file {../outputs/nanosoc_syn_out.cpf}
+
+### Initializing the Design 
+init_design
+
+#ungroup u_nanosoc_chip_u_system
+
+floorPlan -coreMarginsBy die -site sc12mcpp140z_cln28ht -d 1666.6666 1666.6666 135 135 135 135
+
+set_db design_process_node 28
+### Timing Analysis Type 
+set_db timing_analysis_type ocv
+
+# Add Encounter routing option commands in this file
+
+setNanoRouteMode -routeBottomRoutingLayer 2
+generateTracks -honorPitch
+setNanoRouteMode -routeWithViaInPin true
+setNanoRouteMode -routeWithViaOnlyForStandardCellPin true
+
+#Customer is required to source the following placement options in EDI prior to placement 
+setPlaceMode  -checkImplantWidth true
+setPlaceMode -honorImplantSpacing true
+setPlaceMode  -checkImplantMinArea true
+
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/filler.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/filler.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..213d9fdf82a7026a5379fe3e3a5bf2bd561d7dfe
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/filler.tcl
@@ -0,0 +1,9 @@
+addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -fitGap -merge true -powerDomain ACCEL 
+addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -fitGap -merge true -powerDomain TOP
+
+addFillerGap 0.8 -effort high
+
+checkFiller > check_filler.log
+addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -powerDomain ACCEL -fixDrc
+addFiller -cell [list FILLTIE4_A12PP140ZTS_C35 FILLTIE4_A12PP140ZTS_C35 FILLXGCAP8_A12PP140ZTS_C35 FILLXGCAP64_A12PP140ZTS_C35 FILLXGCAP4_A12PP140ZTS_C35 FILLXGCAP3_A12PP140ZTS_C35 FILLXGCAP32_A12PP140ZTS_C35 FILLXGCAP2_A12PP140ZTS_C35 FILLXGCAP16_A12PP140ZTS_C35 FILLXGCAP128_A12PP140ZTS_C35 FILLSGCAP8_A12PP140ZTS_C35 FILLSGCAP64_A12PP140ZTS_C35 FILLSGCAP4_A12PP140ZTS_C35 FILLSGCAP3_A12PP140ZTS_C35 FILLSGCAP32_A12PP140ZTS_C35 FILLSGCAP2_A12PP140ZTS_C35 FILLSGCAP16_A12PP140ZTS_C35 FILLSGCAP128_A12PP140ZTS_C35 ] -prefix FILLER -powerDomain TOP -fixDrc
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/genus.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/genus.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..14152ef91a113a7616676bc8073147049d456cd6
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/genus.tcl
@@ -0,0 +1,124 @@
+#-----------------------------------------------------------------------------
+# NanoSoC gate synthesis script for Cadence Genus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# run: genus -f genus.tcl
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# David Flynn (d.w.flynn@soton.ac.uk)
+# Srimanth Tenneti
+#
+# Copyright (C) 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+set_multi_cpu_usage -local_cpu 8
+## -- Setup libraries -- ##
+
+# Paths to librarys 
+# Edit this
+set TSMC_28NM_PDK_PATH          /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
+set standard_cell_base_path     /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+
+set IO_PAD_DRIVER_DIR $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
+set BASE_LIB_DIR        $standard_cell_base_path/lib
+
+# Don't touch these
+set SRAM_16K_DIR $::env(SOCLABS_PROJECT_DIR)/memories/sram_16k/
+set ROM_DIR $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/
+
+
+set_db init_lib_search_path "$IO_PAD_DRIVER_DIR $BASE_LIB_DIR $SRAM_16K_DIR $ROM_DIR"
+set BASE_LIB sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.lib
+
+set SRAM_LIB        sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
+set ROM_LIB         rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
+set IO_PAD_DRIVER   tphn28hpcpgv18ssg0p81v1p62v125c.lib
+create_library_domain domain1
+set_db [get_db library_domains domain1] .library "$BASE_LIB  $SRAM_LIB  $ROM_LIB $IO_PAD_DRIVER"
+# set_dont_touch SDFF*
+check_library > syn_lib_check.log
+
+## -- Load power intent for top and accelerator power domains -- ##
+read_power_intent -cpf -version 1.1 -module nanosoc_chip_pads ../inputs/nanosoc.cpf
+
+## -- Uncomment if you want to preserve hierarchy -- ##
+#set_db auto_ungroup none
+ 
+## -- Read in RTL and elaborate top level
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
+elaborate nanosoc_chip_pads
+
+# Preserve hierarchy for M0.
+# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
+
+## -- Apply power intent and check library and CPF -- ##
+apply_power_intent
+#check_cpf -license lpgxl -detail > syn_cpf_check.log
+commit_power_intent
+check_power_structure -license lpgxl > syn_pow_check.log
+
+## -- Read constraints -- ##
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC28nm/constraints.sdc 
+
+
+set_db dft_scan_style muxed_scan
+set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 4
+set_db hinst:nanosoc_chip_pads/u_nanosoc_chip_cfg .dft_dont_scan true
+define_test_signal -name TEST  -active high -shared_input -hookup_pin u_nanosoc_chip/test_i -function test_mode -index 0 TEST
+define_test_signal -name CLK  -active high -hookup_pin u_nanosoc_chip/clk_i -function test_clock -index 0 CLK
+define_test_signal -name NRST  -active low -hookup_pin u_nanosoc_chip/nrst_i -function async_set_reset -index 0 NRST
+define_test_signal -name SE  -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable  -function shift_enable -default -index 0 SE
+define_scan_chain -name chain_ACCEL -sdi P0[0] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[0] -sdo P1[0] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[0] -shared_output -shared_input
+define_scan_chain -name chain_TOP_1 -sdi P0[1] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[1] -sdo P1[1] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[1] -shared_output -shared_input
+define_scan_chain -name chain_TOP_2 -sdi P0[2] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[2] -sdo P1[2] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[2] -shared_output -shared_input
+define_scan_chain -name chain_TOP_3 -sdi P0[3] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[3] -sdo P1[3] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[3] -shared_output -shared_input
+
+fix_pad_cfg -mode input -test_control TEST P0[0]
+fix_pad_cfg -mode input -test_control TEST P0[1]
+fix_pad_cfg -mode input -test_control TEST P0[2]
+fix_pad_cfg -mode input -test_control TEST P0[3]
+
+fix_pad_cfg -mode output -test_control TEST P1[0]
+fix_pad_cfg -mode output -test_control TEST P1[1]
+fix_pad_cfg -mode output -test_control TEST P1[2]
+fix_pad_cfg -mode output -test_control TEST P1[3]
+
+check_dft_rules
+fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin CLK
+fix_dft_violations -test_control TEST -async_set
+
+set_db syn_generic_effort high
+set_db syn_map_effort high
+
+syn_generic
+syn_map
+
+convert_to_scan
+connect_scan_chains
+
+syn_opt
+
+report_area > ../reports/syn_nanosoc_area_38pin.rep
+report_timing > ../reports/syn_nanosoc_timing_38pin.rep
+report_gates > ../reports/syn_nanosoc_gates_38pin.rep
+report_power > ../reports/syn_nanosoc_power_38pin.rep
+
+write_hdl > ../outputs/nanosoc_chip_pads_38pin.v
+write_hdl -pg > ../outputs/nanosoc_chip_pads_38pin.vp
+
+write_sdf -timescale ns > ../outputs/nanosoc_chip_pads_38pin.sdf
+
+write_do_lec -revised_design ../outputs/nanosoc_chip_pads_38pin.v -no_lp -top nanosoc_chip_pads -logfile ../outputs/ > lec.dofile  
+
+write_power_intent -cpf -design nanosoc_chip_pads -base_name ../cpf/nanosoc_syn_out
+
+
+report_scan_chains > ../outputs/nanosoc_scan_chains_38pin.rep
+report_scan_setup > ../outputs/nanosoc_scan_setup_38pin.rep
+report_scan_registers > ../outputs/nanosoc_scan_registers_38pin.rep
+write_dft_abstract_model > ../outputs/nanosoc_dft_abstract_model_38pin
+write_dft_atpg_other_vendor -mentor > ../outputs/nanosoc_atpg_38pin
+
+write_scandef > ../outputs/nanosoc_chip_pads_38pin.def
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/genus_nodft.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/genus_nodft.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c25eeeea30bcabee4122bec77e3d2249e4843981
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/genus_nodft.tcl
@@ -0,0 +1,86 @@
+#-----------------------------------------------------------------------------
+# NanoSoC gate synthesis script for Cadence Genus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# run: genus -f genus.tcl
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# David Flynn (d.w.flynn@soton.ac.uk)
+# Srimanth Tenneti
+#
+# Copyright (C) 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+set_multi_cpu_usage -local_cpu 8
+## -- Setup libraries -- ##
+
+# Paths to librarys 
+# Edit this
+set TSMC_28NM_PDK_PATH          /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
+set standard_cell_base_path     /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+
+set IO_PAD_DRIVER_DIR $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
+set BASE_LIB_DIR        $standard_cell_base_path/lib
+
+# Don't touch these
+set SRAM_16K_DIR $::env(SOCLABS_PROJECT_DIR)/memories/sram_16k/
+set ROM_DIR $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/
+
+
+set_db init_lib_search_path "$IO_PAD_DRIVER_DIR $BASE_LIB_DIR $SRAM_16K_DIR $ROM_DIR"
+set BASE_LIB sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.lib
+
+set SRAM_LIB        sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
+set ROM_LIB         rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
+set IO_PAD_DRIVER   tphn28hpcpgv18ssg0p81v1p62v125c.lib
+create_library_domain domain1
+set_db [get_db library_domains domain1] .library "$BASE_LIB  $SRAM_LIB  $ROM_LIB $IO_PAD_DRIVER"
+set_dont_touch SDFF*
+check_library > syn_lib_check.log
+
+## -- Load power intent for top and accelerator power domains -- ##
+read_power_intent -cpf -module nanosoc_chip_pads ../inputs/nanosoc.cpf
+
+## -- Uncomment if you want to preserve hierarchy -- ##
+#set_db auto_ungroup none
+ 
+## -- Read in RTL and elaborate top level
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
+elaborate nanosoc_chip_pads
+
+# Preserve hierarchy for M0.
+# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
+
+## -- Apply power intent and check library and CPF -- ##
+apply_power_intent
+# check_cpf -license lpgxl > syn_cpf_check.log
+commit_power_intent
+check_power_structure -license lpgxl > syn_pow_check.log
+
+## -- Read constraints -- ##
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC28nm/constraints.sdc 
+
+
+set_db syn_generic_effort high
+set_db syn_map_effort high
+set_db syn_opt_effort high
+
+syn_generic
+syn_map
+
+syn_opt
+
+report_area >   ../reports/syn_noDFT_nanosoc_area_44pin.rep
+report_timing > ../reports/syn_noDFT_nanosoc_timing_44pin.rep
+report_gates >  ../reports/syn_noDFT_nanosoc_gates_44pin.rep
+report_power >  ../reports/syn_noDFT_nanosoc_power_44pin.rep
+
+write_hdl > ../outputs/nanosoc_chip_pads_44pin.v
+write_hdl -pg > ../outputs/nanosoc_chip_pads_44pin.vp
+
+write_sdf -timescale ns > ../outputs/nanosoc_chip_pads_44pin.sdf
+
+write_do_lec -revised_design ../outputs/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile ../logs > lec.dofile  
+
+write_power_intent -cpf -design nanosoc_chip_pads -base_name ../outputs/nanosoc_syn_out
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/io_plan.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/io_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..018306cd799b0b6a219b58530d980b6ab8758037
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/io_plan.tcl
@@ -0,0 +1,21 @@
+#-----------------------------------------------------------------------------
+# NanoSoC IO plan for PnR in cadence Innovus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+
+deleteIoFiller -cell PFILLER5_G
+deleteIoFiller -cell PFILLER0005_G
+
+
+loadIoFile ../scripts/nanosoc_io_plan.io
+
+addIoFiller -cell PFILLER5_G -prefix FILLER 
+addIoFiller -cell PFILLER05_G -prefix FILLER 
+addIoFiller -cell PFILLER0005_G -prefix FILLER 
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/nanosoc.mmmc b/ASIC/TSMC28nm/38pin/Cadence/scripts/nanosoc.mmmc
new file mode 100644
index 0000000000000000000000000000000000000000..8a6405f6ed0e8ae7ed347e296fea9a3fa8388019
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/nanosoc.mmmc
@@ -0,0 +1,112 @@
+set cln28ht_tech_path           /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set standard_cell_base_path     /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+set tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/cadence_captable/1p8m_5x2z_utalrdl
+
+set standard_cell_setup_lib   ${standard_cell_base_path}/lib-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_0c.lib_ccs_tn
+set standard_cell_typ_lib     ${standard_cell_base_path}/lib-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_85c.lib_ccs_tn
+set standard_cell_hold_lib    ${standard_cell_base_path}/lib-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_125c.lib_ccs_tn
+
+set TSMC_28NM_PDK_PATH          /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
+set tphn28hpcpgv18_lef_file     ${TSMC_28NM_PDK_PATH}/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/9lm/lef/tphn28hpcpgv18_9lm.lef
+set tphn28hpcpgv18_lib_path     ${TSMC_28NM_PDK_PATH}/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
+set IO_typ_lib                  ${tphn28hpcpgv18_lib_path}/tphn28hpcpgv18tt0p9v1p8v85c.lib
+set IO_hold_lib                 ${tphn28hpcpgv18_lib_path}/tphn28hpcpgv18ffg0p99v1p98v125c.lib
+set IO_setup_lib                ${tphn28hpcpgv18_lib_path}/tphn28hpcpgv18ssg0p81v1p62v0c.lib
+
+set SOCLABS_PROJECT_DIR /home/dwn1c21/SoC-Labs/TAPEOUT/feb2025/28nm/accelerator-project/
+
+set sram_16k_path             ${SOCLABS_PROJECT_DIR}/memories/sram_16k
+set sram_16k_lef_file         ${sram_16k_path}/sram_16k.lef
+set sram_16k_gds_file         ${sram_16k_path}/sram_16k.gds2
+set sram_16k_setup_lib        ${sram_16k_path}/sram_16k_ssg_cworstt_0p81v_0p81v_0c.lib
+set sram_16k_typ_lib          ${sram_16k_path}/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
+set sram_16k_lib_hold_lib     ${sram_16k_path}/sram_16k_ffg_cbestt_0p99v_0p99v_125c.lib
+
+set rom_path            ${SOCLABS_PROJECT_DIR}/memories/bootrom
+set rom_via_lef_file    ${rom_path}/rom_via.lef       
+set rom_via_gds_file    ${rom_path}/rom_via.gds2
+set rom_via_setup_lib   ${rom_path}/rom_via_ssg_cworstt_0p81v_0p81v_m40c.lib
+set rom_via_typ_lib     ${rom_path}/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
+set rom_via_hold_lib    ${rom_path}/rom_via_ffg_cbestt_0p99v_0p99v_125c.lib
+
+
+create_library_set -name default_libset_max\
+   -timing\
+    [list ${standard_cell_setup_lib} ${rom_via_setup_lib} ${sram_16k_setup_lib} \
+    ${IO_setup_lib} ] 
+
+create_library_set -name default_libset_min\
+   -timing\
+    [list ${rom_via_hold_lib} ${sram_16k_lib_hold_lib} ${IO_hold_lib}\
+    ${standard_cell_hold_lib}] 
+
+create_library_set -name typical_libset\
+   -timing\
+    [list ${rom_via_typ_lib} ${sram_16k_typ_lib} ${IO_typ_lib}\
+    ${standard_cell_typ_lib}] 
+
+
+create_rc_corner -name default_rc_corner_worst\
+   -pre_route_res 1\
+   -post_route_res 1\
+   -pre_route_cap 1\
+   -post_route_cap 1\
+   -post_route_cross_cap 1\
+   -pre_route_clock_res 0\
+   -pre_route_clock_cap 0\
+   -cap_table ${tech_path}/rcworst_T.captbl
+
+create_rc_corner -name default_rc_corner_best\
+   -pre_route_res 1\
+   -post_route_res 1\
+   -pre_route_cap 1\
+   -post_route_cap 1\
+   -post_route_cross_cap 1\
+   -pre_route_clock_res 0\
+   -pre_route_clock_cap 0\
+   -cap_table ${tech_path}/rcbest.captbl
+
+create_rc_corner -name default_rc_corner_typical\
+   -pre_route_res 1\
+   -post_route_res 1\
+   -pre_route_cap 1\
+   -post_route_cap 1\
+   -post_route_cross_cap 1\
+   -pre_route_clock_res 0\
+   -pre_route_clock_cap 0\
+   -cap_table ${tech_path}/typical.captbl
+
+
+
+create_delay_corner -name default_delay_corner_max\
+   -library_set {default_libset_max}\
+   -rc_corner default_rc_corner_worst
+
+create_delay_corner -name default_delay_corner_ocv\
+   -early_library_set {default_libset_min}\
+   -late_library_set {default_libset_max}\
+   -rc_corner default_rc_corner_typical
+
+create_delay_corner -name default_delay_corner_min\
+   -library_set default_libset_min\
+   -rc_corner default_rc_corner_best
+
+create_delay_corner -name typical_delay_corner\
+   -library_set typical_libset\
+   -rc_corner default_rc_corner_typical
+
+create_constraint_mode -name default_constraint_mode\
+   -sdc_files\
+    [list ../../../constraints.sdc]
+
+create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
+
+create_analysis_view -name default_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_min
+
+
+create_analysis_view -name typical_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+create_analysis_view -name typical_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+
+create_analysis_view -name typical_analysis_view -constraint_mode default_constraint_mode -delay_corner typical_delay_corner
+
+set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/nanosoc_io_plan.io b/ASIC/TSMC28nm/38pin/Cadence/scripts/nanosoc_io_plan.io
new file mode 100644
index 0000000000000000000000000000000000000000..7a0049400b64636fd15550433d3526c96b6b2ee5
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/nanosoc_io_plan.io
@@ -0,0 +1,68 @@
+###############################################################
+#  Generated by:      Cadence Innovus 21.11-s130_1
+#  OS:                Linux x86_64(Host ID srv03335)
+#  Generated on:      Thu Nov 16 16:18:31 2023
+#  Design:            nanosoc_chip_pads
+#  Command:           write_io_file -locations -template nanosoc_chip_pads.save.io
+###############################################################
+
+(globals
+    version = 3
+    io_order = default
+)
+(iopad
+	(topright
+	(inst name="CornerCell2" cell=PCORNER_G offset=0 orientation=R90 place_status=fixed))
+    (top
+	(inst  name="uPAD_TEST_I"		offset=149.29 place_status=fixed)
+	(inst  name="uPAD_SWDCK_I"		offset=257.86 place_status=fixed )
+	(inst  name="uPAD_VDD_3"		offset=366.43 place_status=fixed )
+	(inst  name="uPAD_VSS_3"		offset=475.00 place_status=fixed )
+	(inst  name="uPAD_VDDIO_3"		offset=583.57 place_status=fixed )
+	(inst  name="uPAD_P1_00"		offset=692.14 place_status=fixed )
+	(inst  name="uPAD_P1_01"		offset=800.71 place_status=fixed )
+    )
+	(topleft
+	(inst name="CornerCell1" cell=PCORNER_G offset=0 orientation=R180 place_status=fixed))
+    (left
+	(inst  name="uPAD_P0_04"	offset=146.25 place_status=fixed )
+	(inst  name="uPAD_P0_05"	offset=251.25 place_status=fixed )
+	(inst  name="uPAD_P0_03"	offset=356.25 place_status=fixed )
+	(inst  name="uPAD_VDDACC_0"	offset=461.25 place_status=fixed )
+	(inst  name="uPAD_VSS_0"	offset=566.25 place_status=fixed )
+	(inst  name="uPAD_CLK_I"	offset=671.25 place_status=fixed )
+	(inst  name="uPAD_VDD_0"	offset=776.25 place_status=fixed )
+	(inst  name="uPAD_VDDIO_0"	offset=881.25 place_status=fixed )
+	(inst  name="uPAD_SWDIO_IO"	offset=986.25 place_status=fixed )
+	(inst  name="uPAD_VSSIO_0"	offset=1091.25  place_status=fixed )
+	(inst  name="uPAD_P0_06"	offset=1196.25  place_status=fixed )
+	(inst  name="uPAD_P0_07"	offset=1301.25  place_status=fixed )
+    )
+	(bottomleft
+	(inst name="CornerCell4" cell=PCORNER_G offset=0 orientation=R270 place_status=fixed))
+    (bottom
+	(inst  name="uPAD_P0_02"	offset=149.29 place_status=fixed )
+	(inst  name="uPAD_VDDACC_1"	offset=257.86 place_status=fixed )
+	(inst  name="uPAD_SE_I"		offset=366.43 place_status=fixed )
+	(inst  name="uPAD_VDD_1"	offset=475.00 place_status=fixed )
+	(inst  name="uPAD_VSS_1"	offset=583.57 place_status=fixed )
+	(inst  name="uPAD_P0_01"	offset=692.14 place_status=fixed )
+	(inst  name="uPAD_P0_00"	offset=800.71 place_status=fixed)
+    )
+	(bottomright
+	(inst name="CornerCell3" cell=PCORNER_G offset=0 orientation=R0 place_status=fixed))
+    (right
+	(inst  name="uPAD_P1_07"	offset=146.25 place_status=fixed )
+	(inst  name="uPAD_P1_06"	offset=251.25 place_status=fixed )
+	(inst  name="uPAD_VSSIO_1"	offset=356.25 place_status=fixed )
+	(inst  name="uPAD_P1_03"	offset=461.25 place_status=fixed )
+	(inst  name="uPAD_P1_02"	offset=566.25 place_status=fixed )
+	(inst  name="uPAD_VDDACC_2"	offset=671.25 place_status=fixed )
+	(inst  name="uPAD_VDD_2"	offset=776.25 place_status=fixed )
+	(inst  name="uPAD_VSS_2"	offset=881.25 place_status=fixed )
+	(inst  name="uPAD_VDDIO_2"	offset=986.25 place_status=fixed )
+	(inst  name="uPAD_NRST_I"	offset=1091.25 place_status=fixed )
+	(inst  name="uPAD_P1_04"	offset=1196.25  place_status=fixed )
+	(inst  name="uPAD_P1_05"	offset=1301.25  place_status=fixed )
+    )
+)
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/place.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/place.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3efc399cb58b7b9cba60bf2306e418abe4e978da
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/place.tcl
@@ -0,0 +1,24 @@
+############################################ 
+# Script : Placement 
+# Date : 26th April 2025 
+# Authors : Srimanth Tenneti 
+#           Daniel Newbrook
+############################################ 
+
+### Congestion and Timing Setting 
+set_db place_global_cong_effort auto 
+set_db place_global_timing_effort high 
+
+### Uniform Cell Distribution and fill gap
+set_db place_global_uniform_density true
+set_db place_detail_legalization_inst_gap 2
+
+### Placement Mode Config 
+set_db place_design_floorplan_mode false 
+place_design
+
+### Delay Calculation 
+write_sdf design.sdf -ideal_clock_network 
+set_db add_tieoffs_max_fanout 10
+addTieHiLo -cell {TIELO_X1M_A12PP140ZTS_C35 TIEHI_X1M_A12PP140ZTS_C35} -prefix LTIE -powerDomain TOP -excludePin ../scripts/tieoff_exclude
+addTieHiLo -cell {TIELO_X1M_A12PP140ZTS_C35 TIEHI_X1M_A12PP140ZTS_C35} -prefix LTIE -powerDomain ACCEL -excludePin ../scripts/tieoff_exclude
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/place_bondpads.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/place_bondpads.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..869f091fecb63e77c8b16c40a4a0f2fa967f64d9
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/place_bondpads.tcl
@@ -0,0 +1,42 @@
+eval_legacy {addInst -cell PAD60LU -inst BPAD_TEST_I    -loc {150.00 1928} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDCK_I   -loc {425.00 1928} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_3     -loc {700.43 1928} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_3     -loc {975.00 1928} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_3   -loc {1250.57 1928} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_00     -loc {1525.14 1928} -ori R180}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_01     -loc {1800.00 1928} -ori R180}
+
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_04     -loc {0.0 200.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_05     -loc {0.0 333.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_03     -loc {0.0 466.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_0  -loc {0.0 599.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_0     -loc {0.0 733.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_CLK_I     -loc {0.0 866.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_0     -loc {0.0 999.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_0   -loc {0.0 1133.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDIO_IO  -loc {0.0 1266.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_0   -loc {0.0 1399.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_06     -loc {0.0 1533.25} -ori R270}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_07     -loc {0.0 1666.25} -ori R270}
+
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_02     -loc {150.29 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_1  -loc {425.86 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_1   -loc {700.43 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_1     -loc {975.00 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_1     -loc {1250.57 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_01     -loc {1525.14 0} -ori R0}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_00     -loc {1800.71 0} -ori R0}
+
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_07     -loc {2028 200.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_06     -loc {2028 333.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_1   -loc {2028 466.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_03     -loc {2028 599.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_02     -loc {2028 733.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_2  -loc {2028 866.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_2     -loc {2028 999.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_2     -loc {2028 1133.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_2   -loc {2028 1266.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_NRST_I    -loc {2028 1399.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_04     -loc {2028 1533.25} -ori R90}
+eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_05     -loc {2028 1666.25} -ori R90}
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/place_macros.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/place_macros.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0b059df34ecde9fd9c631fbf21fa0044e95227d6
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/place_macros.tcl
@@ -0,0 +1,29 @@
+#------------------------------------------------------------------------------------
+# Cadence Innovus: Place  macros
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# Copyright (c) 2023, SoC Labs (www.soclabs.org)
+#------------------------------------------------------------------------------------
+
+# relative floorplan
+delete_relative_floorplan -all
+
+create_relative_floorplan -orient R90 -ref_type core_boundary -horizontal_edge_separate {1  0  1} -vertical_edge_separate {2  0 2} -place u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h_u_expram_h_u_sram_genblk1.u_sram
+create_relative_floorplan -orient R90 -ref_type object -horizontal_edge_separate {1  0  1} -vertical_edge_separate {1  -1  3} -place  u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l_u_expram_l_u_sram_genblk1.u_sram -ref u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h_u_expram_h_u_sram_genblk1.u_sram
+create_relative_floorplan -orient R90 -ref_type object -horizontal_edge_separate {1  0  1} -vertical_edge_separate {1  -1  3} -place  u_nanosoc_chip/u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_sram -ref u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l_u_expram_l_u_sram_genblk1.u_sram
+create_relative_floorplan -orient R90 -ref_type core_boundary -horizontal_edge_separate {1  0  1} -vertical_edge_separate {0  0  0} -place  u_nanosoc_chip/u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_sram 
+
+create_relative_floorplan -orient R90 -ref_type object -horizontal_edge_separate {1 0 1} -vertical_edge_separate {3 1 1} -place u_nanosoc_chip/u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom -ref u_nanosoc_chip/u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_sram
+
+
+move_obj u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -point {135 135}
+update_floorplan_obj -obj u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -polygon {{135 135} {135 1320} {1532 1320}  {1532 135}}
+generate_fence -hInst u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator  -min_gap 2.4
+#create_partition -hinst u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 0 -min_pitch_right 0 -min_pitch_top 2 -min_pitch_bottom 0 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 0 0 0 -route_halo 0.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
+
+addHaloToBlock {2.4 2.4 2.4 2.4} -allMacro
+
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/pnr_flow.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/pnr_flow.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d59377a8e54c92d75d0655862e33e6638c0c6328
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/pnr_flow.tcl
@@ -0,0 +1,133 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Place and route script for Cadence Innovus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# run: innovus -f pnr_flow.tcl
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# David Flynn (d.w.flynn@soton.ac.uk)
+# Srimanth Tenneti
+#
+# Copyright (C) 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set SC_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/gds2/sc12_cln65lp_base_rvt.gds2
+set SC_HVT_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_hvt/r0p0/gds2/sc12_cln65lp_base_hvt.gds2
+set PMK_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_pmk_rvt_hvt/r0p0/gds2/sc12_cln65lp_pmk_rvt_hvt.gds2
+set RF_16K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.gds2
+set RF_08K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.gds2
+set ROM_VIA_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.gds2
+
+setMultiCpuUsage -localCpu 8
+puts "Starting PnR Flow ..."
+
+
+### Design Import 
+source ../scripts/design_import_noDFT.tcl  
+
+### IO Planning 
+source ../scripts/io_plan.tcl
+
+read_power_intent -cpf ../outputs/nanosoc_syn_out.cpf
+commit_power_intent
+reportPowerDomain
+saveDesign nanosoc_chip_pads
+
+update_delay_corner -name default_delay_corner_max -power_domain TOP
+update_delay_corner -name default_delay_corner_max -power_domain ACCEL
+update_delay_corner -name default_delay_corner_min -power_domain ACCEL
+update_delay_corner -name default_delay_corner_min -power_domain TOP
+update_delay_corner -name default_delay_corner_ocv -power_domain TOP
+update_delay_corner -name default_delay_corner_ocv -power_domain ACCEL
+update_delay_corner -name typical_delay_corner -power_domain ACCEL
+update_delay_corner -name typical_delay_corner -power_domain TOP
+
+### Memory and accelerator placement
+source ../scripts/place_macros.tcl
+
+### Power Plan 
+source ../scripts/power_plan.tcl 
+
+### Power Route 
+source ../scripts/power_route.tcl 
+
+report_timing -late > ../reports/1pre_place_nanosoc_imp_timing_late.rep
+report_timing -early > ../reports/1pre_place_nanosoc_imp_timing_early.rep
+
+uniquify nanosoc_chip_pads -verbose
+saveDesign nanosoc_chip_pads
+### Placement 
+source ../scripts/place.tcl 
+
+report_timing -late > ../reports/2post_place_nanosoc_imp_timing_late.rep
+report_timing -early > ../reports/2post_place_nanosoc_imp_timing_early.rep
+
+#reorder_scan 
+saveDesign nanosoc_chip_pads
+
+### CTS 
+source ../scripts/clock_tree_synthesis.tcl 
+#reorder_scan -clock_aware true
+
+report_timing -late > ../reports/3post_clock_nanosoc_imp_timing_late.rep
+report_timing -early > ../reports/3post_clock_nanosoc_imp_timing_early.rep
+
+saveDesign nanosoc_chip_pads
+
+### Add fillers
+source ../scripts/filler.tcl
+
+### Routing 
+source ../scripts/route.tcl 
+
+report_timing -early > ../reports/4post_route_nanosoc_imp_timing_early.rep
+report_timing -late > ../reports/4post_route_nanosoc_imp_timing_late.rep
+
+optDesign -postRoute
+
+report_timing -early > ../reports/5post_route_opt_nanosoc_imp_timing_early.rep
+report_timing -late > ../reports/5post_route_opt_nanosoc_imp_timing_late.rep
+
+check_antenna
+saveDesign nanosoc_chip_pads
+
+delete_routes -net VDDIO
+delete_routes -net VSSIO
+source place_bondpads.tcl
+
+check_drc -out_file ../reports/nanosoc_imp_drc.rep
+check_filler -out_file ../reports/nanosoc_imp_filler.rep
+check_connectivity -out_file ../reports/nanosoc_imp_connectivity.rep
+check_process_antenna -out_file ../reports/nanosoc_imp_antenna.rep
+gui_show 
+
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_default_early.mtarpt
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_default_late.mtarpt
+set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_typical_early.mtarpt
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_typical_late.mtarpt
+set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
+
+write_stream ../outputs/nanosoc.gds \
+    -map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \
+    -lib_name DesignLib \
+    -merge [list ${SC_GDS2} ${RF_16K_GDS2} ${RF_08K_GDS2} ${ROM_VIA_GDS2}]\
+    -output_macros -unit 1000 -mode all  
+
+report_area > ../reports/nanosoc_imp_area.rep
+report_power > ../reports/nanosoc_imp_power.rep
+
+report_timing -late > ../reports/nanosoc_imp_timing_late.rep
+report_timing -early > ../reports/nanosoc_imp_timing_early.rep
+
+set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
+report_timing -late > ../reports/nanosoc_imp_timing_typical_late.rep
+report_timing -early > ../reports/nanosoc_imp_timing_typical_early.rep
+
+set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
+
+write_netlist ../outputs/nanosoc_chip_pads_38pin_pnr.v
+write_sdf -min_view default_analysis_view_hold -typical_view typical_analysis_view -max_view default_analysis_view_setup ../outputs/nanosoc_chip_pads_38pin_pnr.sdf
+
+saveDesign nanosoc_chip_pads
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/power_plan.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ac2cca324cdedcd15a1270b29fd98491cccc1e5e
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/power_plan.tcl
@@ -0,0 +1,89 @@
+#########################################
+# Script : Power Planning 
+# Tool : Cadence Innovus 
+# Date : May 22, 2023
+# Author : Srimanth Tenneti
+######################################### 
+
+### Connecting Global Nets
+globalNetConnect VDD -type pg_pin -pin VDD -instanceBasename * 
+globalNetConnect VDDIO -type pg_pin -pin VDDIO -instanceBasename * 
+globalNetConnect VSS -type pg_pin -pin VSS -instanceBasename * 
+globalNetConnect VSSIO -type pg_pin -pin VSSIO -instanceBasename * 
+globalNetConnect VDDACC -type pg_pin -pin VDD -instanceBasename {} -hierarchicalInstance u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator -override
+### Top and Bottom Metal Declartions
+set_db add_rings_stacked_via_top_layer M8
+set_db add_rings_stacked_via_bottom_layer M1 
+
+### Adding Rings 
+addRing -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M7 bottom M7 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+sroute -connect {padPin padRing} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort allGeom} -padPinTarget nearestTarget -allowJogging 1 -crossoverViaLayerRange { M1(1) AP(9) } -nets { VSS } -allowLayerChange 1 -padPinWidth 1.5 -targetViaLayerRange { M1(1) AP(9) }
+sroute -connect {padPin padRing} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort allGeom} -padPinTarget nearestTarget -allowJogging 1 -crossoverViaLayerRange { M1(1) AP(9) } -nets { VDD VDDACC } -allowLayerChange 1 -padPinWidth 1.41 -targetViaLayerRange { M1(1) AP(9) }
+
+### Adding Stripes 
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target none
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_ignore_non_default_domains true
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M1
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring  block_ring }
+set_db add_stripes_skip_via_on_pin {  standardcell }
+set_db add_stripes_skip_via_on_wire_shape {  noshape   }
+addStripe -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit AP -padcore_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Connect Accelerator region
+select_obj u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target {ring stripe}
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_partial_set_through_domain true
+set_db add_stripes_ignore_non_default_domains false
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M4
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring  block_ring }
+set_db add_stripes_skip_via_on_pin {  standardcell }
+set_db add_stripes_skip_via_on_wire_shape {  noshape   }
+addStripe -nets {VDDACC VSS} -layer AP -direction horizontal -width 2 -spacing 2 -set_to_set_distance 20 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit AP -padcore_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# connect Macros
+select_obj [ list u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
+set_db add_stripes_ignore_block_check false
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target {ring stripe}
+addStripe -nets {VDD VSS} -layer M5 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -start_from bottom -start_offset 8 -stop_offset 0 -switch_layer_over_obs false -merge_stripes_value 500 -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit AP -padcore_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Add END CAPS
+addEndCap -preCap ENDCAPTIE3_A12PP140ZTS_C35 -postCap ENDCAPTIE3_A12PP140ZTS_C35 -prefix ENDCAP
+addEndCap -powerDomain ACCEL -preCap ENDCAPTIE3_A12PP140ZTS_C35 -postCap ENDCAPTIE3_A12PP140ZTS_C35 -prefix ENDCAP
+#add_endcaps -power_domain PD_SYS -start_row_cap ENDCAPBIAS2_A12TR -end_row_cap ENDCAPBIAS2_A12TR -prefix ENDCAP_SYS
+#add_endcaps -power_domain PD_DBG -start_row_cap ENDCAPBIAS2_A12TR -end_row_cap ENDCAPBIAS2_A12TR -prefix ENDCAP_DBG
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/power_route.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/power_route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3bb204e1eaa09809e3517088ea279eddd96fbb17
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/power_route.tcl
@@ -0,0 +1,13 @@
+##################################
+# Script : Special Route Script 
+# Date : May 24, 2023 
+# Description : Power Routing 
+# Author : Srimanth Tenneti 
+##################################
+set_db route_special_via_connect_to_shape { padring stripe }
+sroute -connect {blockPin corePin floatingStripe} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort oneGeom} -padPinTarget nearestTarget -corePinTarget firstAfterRowEnd -floatingStripeTarget {blockRing padRing ring stripe ringPin blockPin followpin} -allowJogging 1 -powerDomains { ACCEL } -crossoverViaLayerRange { M1(1) AP(9) } -nets { VDDACC VSS } -allowLayerChange 1 -blockPin useLef -targetViaLayerRange { M1(1) AP(9) }
+sroute -connect {blockPin corePin floatingStripe} -layerChangeRange { M1(1) AP(9) } -blockPinTarget nearestTarget -padPinPortConnect {allPort oneGeom} -padPinTarget nearestTarget -corePinTarget firstAfterRowEnd -floatingStripeTarget {blockRing padRing ring stripe ringPin blockPin followpin} -allowJogging 1 -powerDomains { TOP } -crossoverViaLayerRange { M1(1) AP(9) } -nets { VDD VSS } -allowLayerChange 1 -blockPin useLef -targetViaLayerRange { M1(1) AP(9) }
+#route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { PD_SYS } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD_SYS VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+#route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { PD_DBG } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD_DBG VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+
+#route_special  -nets {VDD VSS} -connect core_pin  -block_pin_target nearest_target -core_pin_target first_after_row_end  -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/route.tcl b/ASIC/TSMC28nm/38pin/Cadence/scripts/route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..56aae70c33bbb8ad2ab6cfac4b9c3ef83d2bd5dc
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/route.tcl
@@ -0,0 +1,16 @@
+
+### Clock Net Spacing
+#set_route_attributes -nets clk -preferred_extra_space_tracks 2 
+
+### Multi Cut Via Effort 
+set_db route_design_detail_use_multi_cut_via_effort medium
+
+### Timing Driven Route
+set_db route_design_with_timing_driven 1 
+
+### SI Driven Route 
+set_db route_design_with_si_driven 1 
+
+### Route Design 
+routeDesign -globalDetail
+
diff --git a/ASIC/TSMC28nm/38pin/Cadence/scripts/tieoff_exclude b/ASIC/TSMC28nm/38pin/Cadence/scripts/tieoff_exclude
new file mode 100644
index 0000000000000000000000000000000000000000..c28aa791fb21bb1267244c41c20eb0743d344a6e
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Cadence/scripts/tieoff_exclude
@@ -0,0 +1,43 @@
+uPAD_SE_I/IE
+uPAD_SE_I/PE
+uPAD_SE_I/DS
+uPAD_SE_I/I
+uPAD_SE_I/OEN
+uPAD_CLK_I/IE
+uPAD_CLK_I/PE
+uPAD_CLK_I/DS
+uPAD_CLK_I/I
+uPAD_CLK_I/OEN
+uPAD_TEST_I/IE
+uPAD_TEST_I/PE
+uPAD_TEST_I/DS
+uPAD_TEST_I/I
+uPAD_TEST_I/OEN
+uPAD_NRST_I/IE
+uPAD_NRST_I/PE
+uPAD_NRST_I/DS
+uPAD_NRST_I/I
+uPAD_NRST_I/OEN
+uPAD_SWDIO_IO/PE 
+uPAD_SWDIO_IO/DS
+uPAD_SWDCK_I/IE
+uPAD_SWDCK_I/PE
+uPAD_SWDCK_I/DS
+uPAD_SWDCK_I/I
+uPAD_SWDCK_I/OEN
+uPAD_P0_00/DS
+uPAD_P0_01/DS
+uPAD_P0_02/DS
+uPAD_P0_03/DS
+uPAD_P0_04/DS
+uPAD_P0_05/DS
+uPAD_P0_06/DS
+uPAD_P0_07/DS
+uPAD_P1_00/DS
+uPAD_P1_01/DS
+uPAD_P1_02/DS
+uPAD_P1_03/DS
+uPAD_P1_04/DS
+uPAD_P1_05/DS
+uPAD_P1_06/DS
+uPAD_P1_07/DS
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/makefile b/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..be08c378189da917e11b1ace3d4c41140cf16102
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/makefile
@@ -0,0 +1,35 @@
+LIBS_DIR:=./libs
+REPORT_DIR:=./reports
+LOG_DIR:=./logs
+WORK_DIR:=./work
+OUT_DIR:=./outputs
+
+make_directories:
+	mkdir -p $(LIBS_DIR)
+	mkdir -p $(REPORT_DIR)
+	mkdir -p $(LOG_DIR)
+	mkdir -p $(WORK_DIR)
+	mkdir -p $(OUT_DIR)
+
+generate_libs: make_directories
+	cd $(LIBS_DIR); lc_shell; -f ../scripts/synopsys_lib_conversion.tcl;
+
+synthesis:  
+	cd $(WORK_DIR); dc_shell
+
+fusion_init_design:
+	cd $(WORK_DIR); fc_shell -f ../scripts/1_design_setup.tcl;
+
+fusion_synthesis:
+	cd $(WORK_DIR); fc_shell -f ../scripts/2_synthesis.tcl;
+
+fusion_clock_opt:
+	cd $(WORK_DIR); fc_shell -f ../scripts/3_clock.tcl 
+
+fusion_route:
+	cd $(WORK_DIR); fc_shell;
+
+fusion_full_flow: fusion_init_design fusion_synthesis fusion_clock_opt fusion_route
+
+all: generate_libs fusion_full_flow
+
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/scripts/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/scripts/synopsys_lib_conversion.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c1a7a267fd82007526f0d99c687f7994eec111ee
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/scripts/synopsys_lib_conversion.tcl
@@ -0,0 +1,45 @@
+# SRAM files (using Arm compiler)
+set sram_16k_path                       $env(SOCLABS_PROJECT_DIR)/memories/sram_16k
+set sram_16k_lib_file_ss_0p81v_125c     $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
+set sram_16k_lib_file_tt_0p90v_25c      $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.lib
+set sram_16k_lib_file_ff_0p99v_m40c     $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
+set sram_16k_db_file_ss_0p81v_125c      $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db
+set sram_16k_db_file_tt_0p90v_25c       $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.db
+set sram_16k_db_file_ff_0p99v_m40c      $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db
+
+# ROM Files (using arm Compiler)
+set rom_path                        $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+set rom_via_lib_file_ss_0p81v_125c  $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
+set rom_via_lib_file_tt_0p90v_25c   $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
+set rom_via_lib_file_ff_0p99v_m40c  $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.lib
+set rom_via_db_file_ss_0p81v_125c   $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.db
+set rom_via_db_file_tt_0p90v_25c    $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
+set rom_via_db_file_ff_0p99v_m40c   $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db
+
+# 16K SRAM
+read_lib $sram_16k_lib_file_ss_0p81v_125c
+write_lib -output ./sram_16k_db_file_ss_0p81v_125c.db -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
+
+read_lib $sram_16k_lib_file_tt_0p90v_25c 
+write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_25c
+close_lib -all
+
+read_lib $sram_16k_lib_file_ff_0p99v_m40c 
+write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
+
+# Boot ROM
+read_lib $rom_via_lib_file_ss_0p81v_125c 
+write_lib -output $rom_via_db_file_ss_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
+
+read_lib $rom_via_lib_file_tt_0p90v_25c 
+write_lib -output $rom_via_db_file_tt_0p90v_25c -format db rom_via_tt_ctypical_0p90v_0p90v_25c
+close_lib -all
+
+read_lib $rom_via_lib_file_ff_0p99v_m40c 
+write_lib -output $rom_via_db_file_ff_0p99v_m40c -format db rom_via_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
+
+exit
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/scripts/synthesis.tcl b/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/scripts/synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4853e8eee45134e68abdf623b941a1467467cd33
--- /dev/null
+++ b/ASIC/TSMC28nm/38pin/Synopsys_DC_ICC2/scripts/synthesis.tcl
@@ -0,0 +1,85 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Synopsys synthesis tcl file to be run with dc_shell
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set rtlPath $env(SOCLABS_PROJECT_DIR)
+set report_path ../reports/
+set top_module nanosoc_chip_pads
+set io_path /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
+#supress_message = {ELAB-405}
+#####
+# Set search_path
+#
+# List locations where your standard cell libraries may be located
+#
+#####
+set standard_cell_db_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0/db
+
+set search_path [list . $search_path $standard_cell_db_path $env(SOCLABS_PROJECT_DIR)/memories/sram_16k $env(SOCLABS_PROJECT_DIR)/memories/bootrom $io_path]
+set search_path [concat $rtlPath $search_path]
+######
+# Set Target Library
+#
+# Set a default target library for Design Compiler to target when compiling a design
+#
+######
+set target_library "sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db sram_16k_ssg_cworstt_0p81v_0p81v_125c.db rom_via_ssg_cworstt_0p81v_0p81v_125c.db tphn28hpcpgv18ssg0p81v1p62v125c.db"
+
+######
+# Set Link Library
+#
+# Set a default link library for Design Compiler to target when compiling a design
+#
+######
+set link_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db sram_16k_ssg_cworstt_0p81v_0p81v_125c.db rom_via_ssg_cworstt_0p81v_0p81v_125c.db tphn28hpcpgv18ssg0p81v1p62v125c.db"
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
+elaborate $top_module -lib WORK
+current_design $top_module
+
+# Link Design
+link
+
+read_sdc ../../constraints.sdc 
+
+load_upf ../nanosoc_chip_pads.upf
+
+set_voltage -object_list {VDD VDDACC VDD_VSS.power VDDACC_VSS.power TOP.primary.power ACCEL.primary.power} 1.08
+set_voltage -object_list {VSS VDD_VSS.ground VDDACC_VSS.ground TOP.primary.ground ACCEL.primary.ground} 0.00
+
+set_operating_conditions -library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c ss_typical_max_1p08v_125c
+
+set_app_var compile_delete_unloaded_sequential_cells false
+compile_ultra -gate_clock -scan 
+
+set_scan_configuration -chain_count 2
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_1
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_2
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_1
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_2
+set_dft_signal -view spec -type ScanEnable -port TEST -active_state 1
+set_dft_signal -view existing_dft -type Reset -port NRST -active_state 0
+set_scan_configuration -power_domain_mixing false
+create_test_protocol -infer_clock -infer_asynch 
+dft_drc
+insert_dft
+
+write -hierarchy -format verilog -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
+write -hierarchy -format verilog -pg -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vp
+write_scan_def -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
+write_test_protocol -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads_scan.stil 
+
+redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
+redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference }
+redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
+redirect [format "%s%s%s" $report_path $top_module _scan_path.rep] { report_scan_path }
+redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
+  { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
+
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def
index f85dc7a18f6029be8a20c8d55331bee2eaa1f134..dd16dee7ed3326b813b42aa906834c03e8b0aa18 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.def
@@ -2,12 +2,12 @@
 # Fusion Compiler write_def
 # Release      : U-2022.12
 # User Name    : dwn1c21
-# Date         : Tue Apr 15 19:30:50 2025
+# Date         : Fri May  2 22:00:00 2025
 # 
 VERSION 5.8 ;
 DIVIDERCHAR "/" ;
 BUSBITCHARS "[]" ;
 DESIGN nanosoc_chip_pads ;
 UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 0 1610400 ) ( 1111100 1610400 ) ( 1111100 0 ) ;
+DIEAREA ( 0 0 ) ( 0 1665600 ) ( 1666640 1665600 ) ( 1666640 0 ) ;
 END DESIGN
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl
index 9a053489d182278335a32dc37bda3c25998316fb..1c728c115eb85767d23a994286a2bc2bf7ec5d67 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan.tcl
@@ -1,6 +1,6 @@
 ################################################################################
 #
-# Created by fc write_floorplan on Tue Apr 15 19:30:50 2025
+# Created by fc write_floorplan on Fri May  2 22:00:00 2025
 #
 ################################################################################
 
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
index 2cb4692a81bd4b913dab40fe48b33c17832c27ed..0e1c27b1e2275d33d4e331531c2856f7b65985b6 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/floorplan_compare_data.txt
@@ -1,6 +1,6 @@
 ################################################################################
 #
-# Created by fc compare_floorplans on Tue Apr 15 19:30:51 2025
+# Created by fc compare_floorplans on Fri May  2 22:00:01 2025
 #
 # DO NOT EDIT - automatically generated file
 #
@@ -8,34 +8,34 @@
 
 START nanosoc_chip_pads
  MACROS
-  u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {180.0000 1399.3550} {275.0500 1430.4000} }
-  u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {758.9200 1051.3300} {931.1000 1240.8650} }
-  u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {586.7400 1051.3300} {758.9200 1240.8650} }
-  u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {758.9200 1240.8650} {931.1000 1430.4000} }
-  u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {586.7400 1240.8650} {758.9200 1430.4000} }
+  u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom { {747.8700 1504.0350} {842.9200 1530.6000} }
+  u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram { {1015.1000 1341.0650} {1187.2800 1530.6000} }
+  u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram { {842.9200 1341.0650} {1015.1000 1530.6000} }
+  u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram { {1187.2800 1341.0650} {1359.4600 1530.6000} }
+  u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram { {1359.4600 1341.0650} {1531.6400 1530.6000} }
  PINS
-  VDDIO { {1110.7600 804.6750} {1111.1000 804.7250} }
-  VSSIO { {555.5750 1610.1200} {555.6250 1610.4000} }
-  SE { {0.0000 804.6750} {0.3400 804.7250} }
-  CLK { {70.0500 222.0150} {73.0500 238.0650} }
-  TEST { {1038.0500 797.1750} {1041.0500 813.2250} }
-  NRST { {70.0500 352.0550} {73.0500 368.1050} }
-  P0[7] { {920.2500 70.0500} {936.3000 73.0500} }
-  P0[6] { {70.0500 1262.3350} {73.0500 1278.3850} }
-  P0[5] { {70.0500 1132.2950} {73.0500 1148.3450} }
-  P0[4] { {70.0500 1002.2550} {73.0500 1018.3050} }
-  P0[3] { {70.0500 872.2150} {73.0500 888.2650} }
-  P0[2] { {70.0500 742.1750} {73.0500 758.2250} }
-  P0[1] { {70.0500 612.1350} {73.0500 628.1850} }
-  P0[0] { {70.0500 482.0950} {73.0500 498.1450} }
-  P1[7] { {257.6300 70.0500} {273.6800 73.0500} }
-  P1[6] { {340.4550 70.0500} {356.5050 73.0500} }
-  P1[5] { {423.2850 70.0500} {439.3350 73.0500} }
-  P1[4] { {506.1100 70.0500} {522.1600 73.0500} }
-  P1[3] { {588.9400 70.0500} {604.9900 73.0500} }
-  P1[2] { {671.7650 70.0500} {687.8150 73.0500} }
-  P1[1] { {754.5950 70.0500} {770.6450 73.0500} }
-  P1[0] { {837.4200 70.0500} {853.4700 73.0500} }
-  SWDIO { {1038.0500 1079.2550} {1041.0500 1095.3050} }
-  SWDCK { {1038.0500 1361.3350} {1041.0500 1377.3850} }
+  VDDIO { {1666.3000 832.2750} {1666.6400 832.3250} }
+  VSSIO { {833.2750 1665.3200} {833.3250 1665.6000} }
+  SE { {0.0000 832.2750} {0.3400 832.3250} }
+  CLK { {70.0500 238.5350} {73.0500 254.5850} }
+  TEST { {1593.5900 824.7750} {1596.5900 840.8250} }
+  NRST { {70.0500 385.0950} {73.0500 401.1450} }
+  P0[7] { {1425.2850 70.0500} {1441.3350 73.0500} }
+  P0[6] { {70.0500 1411.0150} {73.0500 1427.0650} }
+  P0[5] { {70.0500 1264.4550} {73.0500 1280.5050} }
+  P0[4] { {70.0500 1117.8950} {73.0500 1133.9450} }
+  P0[3] { {70.0500 971.3350} {73.0500 987.3850} }
+  P0[2] { {70.0500 824.7750} {73.0500 840.8250} }
+  P0[1] { {70.0500 678.2150} {73.0500 694.2650} }
+  P0[0] { {70.0500 531.6550} {73.0500 547.7050} }
+  P1[7] { {358.6350 70.0500} {374.6850 73.0500} }
+  P1[6] { {491.9700 70.0500} {508.0200 73.0500} }
+  P1[5] { {625.3000 70.0500} {641.3500 73.0500} }
+  P1[4] { {758.6300 70.0500} {774.6800 73.0500} }
+  P1[3] { {891.9600 70.0500} {908.0100 73.0500} }
+  P1[2] { {1025.2900 70.0500} {1041.3400 73.0500} }
+  P1[1] { {1158.6200 70.0500} {1174.6700 73.0500} }
+  P1[0] { {1291.9550 70.0500} {1308.0050 73.0500} }
+  SWDIO { {1593.5900 1117.8950} {1596.5900 1133.9450} }
+  SWDCK { {1593.5900 1411.0150} {1596.5900 1427.0650} }
 END nanosoc_chip_pads
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl
index 3b8ca2a23e80958e8fc05b2677b2aa14fe69c770..cbd5fb7704c3229a0ee105f7804fc22d82a47232 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/floorplan/fp.tcl
@@ -1,6 +1,6 @@
 ################################################################################
 #
-# Created by fc write_floorplan on Tue Apr 15 19:30:50 2025
+# Created by fc write_floorplan on Fri May  2 22:00:00 2025
 #
 ################################################################################
 
@@ -21,40 +21,40 @@ set cellInst [get_cells { \
     u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
     }]
 set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 275.0500 \
-    1399.3550 }
+set_attribute -quiet -objects $cellInst -name origin -value { 842.9200 \
+    1504.0350 }
 set_attribute -quiet -objects $cellInst -name status -value placed
 
 set cellInst [get_cells { \
     u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/genblk1.u_sram \
     }]
 set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 931.1000 \
-    1051.3300 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1187.2800 \
+    1341.0650 }
 set_attribute -quiet -objects $cellInst -name status -value placed
 
 set cellInst [get_cells { \
     u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/genblk1.u_sram \
     }]
 set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 758.9200 \
-    1051.3300 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1015.1000 \
+    1341.0650 }
 set_attribute -quiet -objects $cellInst -name status -value placed
 
 set cellInst [get_cells { \
     u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/genblk1.u_sram \
     }]
 set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 931.1000 \
-    1240.8650 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1359.4600 \
+    1341.0650 }
 set_attribute -quiet -objects $cellInst -name status -value placed
 
 set cellInst [get_cells { \
     u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/genblk1.u_sram \
     }]
 set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 758.9200 \
-    1240.8650 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1531.6400 \
+    1341.0650 }
 set_attribute -quiet -objects $cellInst -name status -value placed
 
 
@@ -62,6 +62,7 @@ set_attribute -quiet -objects $cellInst -name status -value placed
 # User attributes of macros
 ################################################################################
 
+define_user_attribute -classes cell -type boolean SNPS_MuxEO
 
 ################################################################################
 # Bounds and user attributes of bound shapes
@@ -75,6 +76,22 @@ remove_bounds -all
 ################################################################################
 
 
+################################################################################
+# Blockages
+################################################################################
+
+remove_routing_blockages -all -force
+
+remove_placement_blockages -all -force
+
+remove_pin_blockages -all
+
+remove_shaping_blockages -all
+
+################################################################################
+# User attributes of blockages
+################################################################################
+
 ################################################################################
 # Module Boundaries
 ################################################################################
@@ -89,6 +106,16 @@ if [sizeof_collection $hbCells] {
 # User attributes of current block
 ################################################################################
 
+define_user_attribute -classes design -type double \
+    achieved_target_routing_density
+define_user_attribute -classes design -type int buf_inv_counts
+define_user_attribute -classes design -type double expanded_util
+define_user_attribute -classes design -type int ldp_flow_stage
+define_user_attribute -classes design -type string sqs_step
+define_user_attribute -classes design -type string write_qor_data
+set_attribute [current_design] write_qor_data {qor_strategy {high_effort_timing \
+    0 reduced_effort 0 default 0 stage synthesis metric timing}}
 set_attribute [current_design] achieved_target_routing_density 0.0
-set_attribute [current_design] expanded_util 0.71
+set_attribute [current_design] sqs_step synthesis
+set_attribute [current_design] expanded_util 0.42
 
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/1_design_setup.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/1_design_setup.tcl
index 019bbb94ae227dad12d5a45a121ef92013bd863b..84d2e2307aaaea206321e118e8a35ecba8c34223 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/1_design_setup.tcl
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/1_design_setup.tcl
@@ -21,7 +21,10 @@ set TLU_map $TLU_dir/tluplus.map
 #Create the design library 
 create_lib nanosoc_chip_pads.dlib \
     -technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf \
-    -ref_libs {../libs/cln28ht/ ../libs/cln28ht_pmk/ ../libs/cln28ht_ret/ ../libs/sram_16k/ ../libs/sram_32k/ ../libs/sram_64k/ ../libs/rom_via/ ../libs/io_lib/ ../libs/pad_lib/ ../libs/bump_lib/}
+    -ref_libs {../libs/cln28ht/ ../libs/cln28ht_pmk/ ../libs/cln28ht_hpk ../libs/cln28ht_ret/ ../libs/sram_16k/  ../libs/rom_via/ ../libs/io_lib/ ../libs/pad_lib/}
+
+set lib_list {cln28ht cln28ht_pmk cln28ht_hpk cln28ht_ret sram_16k rom_via io_lib pad_lib}
+
 
 source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
 analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
@@ -32,7 +35,11 @@ set_top_module nanosoc_chip_pads
 redirect -tee -file ../logs/lib_cell_summary.log {report_lib -cell_summary cln28ht}
 redirect -tee -file ../logs/lib_cell_pmk_summary.log {report_lib -cell_summary cln28ht_pmk}
 redirect -tee -file ../logs/lib_cell_ret_summary.log {report_lib -cell_summary cln28ht_ret}
-redirect -tee -file ../logs/lib_cell_bump_summary.log {report_lib -cell_summary bump_lib}
+redirect -tee -file ../logs/lib_cell_hpk_summary.log {report_lib -cell_summary cln28ht_hpk}
+redirect -tee -file ../logs/lib_cell_io_lib_summary.log {report_lib -cell_summary io_lib}
+redirect -tee -file ../logs/lib_cell_pad_lib_summary.log {report_lib -cell_summary pad_lib}
+redirect -tee -file ../logs/lib_cell_sram_16k_summary.log {report_lib -cell_summary sram_16k}
+redirect -tee -file ../logs/lib_cell_rom_via_summary.log {report_lib -cell_summary rom_via}
 
 remove_modes -all
 remove_corners -all
@@ -56,8 +63,8 @@ create_corner hold_corner
 create_scenario -name hold_scenario -mode hold_mode -corner hold_corner
 set_scenario_status hold_scenario -none -setup false -hold true -leakage_power true -dynamic_power false -max_transition true -max_capacitance false -min_capacitance true -active true
 
-set_app_options -name time.convert_constraint_from_bc_wc -value bc_only
-read_sdc ../../../constraints.sdc
+current_corner hold_corner
+read_sdc ../../../constraints_hold.sdc
 
 
 create_mode setup_mode
@@ -65,28 +72,60 @@ create_corner setup_corner
 create_scenario -name setup_scenario -mode setup_mode -corner setup_corner
 set_scenario_status setup_scenario -none -setup true -hold false -leakage_power true -dynamic_power true -max_transition true -max_capacitance true -min_capacitance false -active true
 
-set_app_options -name time.convert_constraint_from_bc_wc -value wc_only
-read_sdc ../../../constraints.sdc
+current_corner setup_corner 
+read_sdc ../../../constraints_setup.sdc
 
-set_app_options -name time.convert_constraint_from_bc_wc -value none
+#create_mode em_mode
+#create_corner em_corner
+#create_scenario -name em_scenario -mode em_mode -corner em_corner
+#set_scenario_status em_scenario -none -setup false -hold false -leakage_power false -dynamic_power false -max_transition false -max_capacitance false -min_capacitance false -cell_em true -signal_em true -active true 
 
 ## hold - FFGNP V=+10% T=-40 and 125, parasitics cworst cbest rcworst rcbest
 #         SSSGNP V=-10%, T=-40 and 125, parasitics cworst and rcworst
+
+
 current_corner hold_corner
-set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
-set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
-set_temperature 125 -min -40 -corners hold_corner
-set_voltage 0.81 -min 0.99 -corners hold_corner
+set_parasitic_parameters -early_spec cbest -early_temperature 125 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
+set_operating_conditions -max_library cln28ht_pmk -max ffg_cbestt_min_0p99v_125c -min_library cln28ht_pmk -min ffg_cbestt_min_0p99v_125c
+set_operating_conditions -max_library cln28ht_hpk -max ffg_cbestt_min_0p99v_125c -min_library cln28ht_hpk -min ffg_cbestt_min_0p99v_125c
+set_operating_conditions -max_library cln28ht_ret -max ffg_cbestt_min_0p99v_125c -min_library cln28ht_ret -min ffg_cbestt_min_0p99v_125c
+set_operating_conditions -max_library sram_16k -max ffg_cbestt_0p99v_0p99v_125c -min_library sram_16k -min ffg_cbestt_0p99v_0p99v_125c
+set_operating_conditions -max_library rom_via -max ffg_cbestt_0p99v_0p99v_125c -min_library rom_via -min ffg_cbestt_0p99v_0p99v_125c
+set_operating_conditions -max_library io_lib -max ffg0p99v1p98vm40c -min_library io_lib -min ffg0p99v1p98vm40c
+set_operating_conditions -max_library cln28ht -max ffg_cbestt_min_0p99v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_125c
+set_temperature 125 -min 125 -corners hold_corner
+set_voltage 0.99 -min 0.99 -corners hold_corner
+
+#set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library nanosoc_chip_pads.dlib
+#set_operating_conditions -max_library cln28ht_pmk -max ssg_cworstt_max_0p81v_125c -min_library cln28ht_pmk -min ffg_cbestt_min_0p99v_m40c
+#set_operating_conditions -max_library cln28ht_hpk -max ssg_cworstt_max_0p81v_125c -min_library cln28ht_hpk -min ffg_cbestt_min_0p99v_m40c
+#set_operating_conditions -max_library cln28ht_ret -max ssg_cworstt_max_0p81v_125c -min_library cln28ht_ret -min ffg_cbestt_min_0p99v_m40c
+#set_operating_conditions -max_library sram_16k -max ssg_cworstt_0p81v_0p81v_125c -min_library sram_16k -min ffg_cbestt_0p99v_0p99v_m40c
+#set_operating_conditions -max_library rom_via -max ssg_cworstt_0p81v_0p81v_125c -min_library rom_via -min ffg_cbestt_0p99v_0p99v_m40c
+#set_operating_conditions -max_library io_lib -max ssg0p81v1p62v125c -min_library io_lib -min ffg0p99v1p98vm40c
+#set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
+#set_temperature 125 -min -40 -corners hold_corner
+#set_voltage 0.81 -min 0.99 -corners hold_corner
 
 ## setup SSGNP V=-10%, T=-40 parasitics cworst_t rcworst_t
 #        TT V=-10%, T=85C parasitics cworst_t rcworst_t
+#set_parasitic_parameters -early_spec cworst_T -early_temperature -40 -late_spec rcworst_T -late_temperature 25 -library nanosoc_chip_pads.dlib
+#set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min tt_ctypical_max_0p90v_25c
+#set_temperature -40 -min 25 -corners setup_corner
+#set_voltage 0.81 -corners setup_corner
 current_corner setup_corner
-set_parasitic_parameters -early_spec cworst_T -early_temperature -40 -late_spec rcworst_T -late_temperature 125 -library nanosoc_chip_pads.dlib
-set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min tt_ctypical_max_0p90v_25c
-set_temperature 85 -min -40 -corners setup_corner
+set_parasitic_parameters -early_spec rcworst_T -early_temperature 125 -library nanosoc_chip_pads.dlib
+
+set_operating_conditions -max_library cln28ht_pmk -max ssg_cworstt_max_0p81v_125c -min_library cln28ht_pmk -min ssg_cworstt_max_0p81v_125c
+set_operating_conditions -max_library cln28ht_hpk -max ssg_cworstt_max_0p81v_125c -min_library cln28ht_hpk -min ssg_cworstt_max_0p81v_125c
+set_operating_conditions -max_library cln28ht_ret -max ssg_cworstt_max_0p81v_125c -min_library cln28ht_ret -min ssg_cworstt_max_0p81v_125c
+set_operating_conditions -max_library sram_16k -max ssg_cworstt_0p81v_0p81v_125c -min_library sram_16k -min ssg_cworstt_0p81v_0p81v_125c
+set_operating_conditions -max_library rom_via -max ssg_cworstt_0p81v_0p81v_125c -min_library rom_via -min ssg_cworstt_0p81v_0p81v_125c
+set_operating_conditions -max_library io_lib -max ssg0p81v1p62v125c -min_library io_lib -min ssg0p81v1p62v125c
+set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
+set_temperature 125 -corners setup_corner
 set_voltage 0.81 -corners setup_corner
 
-
 ## max transition - SSGNP V=-10% T=-40 P=cworst_t rcworst_t
 
 ## typical power - TT V=V T=85C P=ctypical
@@ -96,24 +135,125 @@ set_voltage 0.81 -corners setup_corner
 # Signal EM - FFG V=V T=125 P=rcworst_c cworst_T
 
 redirect -file ../reports/design_setup.report_scenarios.rpt {report_scenarios} 
+redirect -file ../reports/design_setup.report_pvt.rpt {report_pvt} 
+redirect -file ../reports/design_setup.report_corners.rpt {report_corners} 
 
-save_block nanosoc_cip_pads
+save_block nanosoc_chip_pads
 save_lib nanosoc_chip_pads.dlib
 
-initialize_floorplan -control_type die -use_site_row -side_length {1111.1111 1611.11111} -core_offset {180}
-source ../floorplan/fp.tcl
+initialize_floorplan -control_type die -use_site_row -side_length {1666.666666 1666.666666} -core_offset {135}
+source ../floorplan/floorplan.tcl
 
 remove_io_guides -all 
 
-create_io_ring -name main_io -pad_cell_list {uPAD_CLK_I uPAD_NRST_I uPAD_P0_00 uPAD_P0_01 uPAD_P0_02 uPAD_P0_03 uPAD_P0_04 uPAD_P0_05 uPAD_P0_06 uPAD_P0_07 uPAD_P1_00 uPAD_P1_01 uPAD_P1_02 uPAD_P1_03 uPAD_P1_04 uPAD_P1_05 uPAD_P1_06 uPAD_P1_07 uPAD_SE_I uPAD_SWDCK_I uPAD_SWDIO_IO uPAD_TEST_I uPAD_VDDACC_0 uPAD_VDDACC_1 uPAD_VDDACC_2 uPAD_VDDIO_0 uPAD_VDDIO_2 uPAD_VDDIO_3 uPAD_VDD_0 uPAD_VDD_1 uPAD_VDD_2 uPAD_VDD_3 uPAD_VSSIO_0 uPAD_VSSIO_1 uPAD_VSS_0 uPAD_VSS_1 uPAD_VSS_2 uPAD_VSS_3}
+
+create_io_guide -name {main_io.top} -side top -line {{110.000 1665.600} 1556.640} -offset {0.000 0.000} -pad_cells [list  \
+  uPAD_TEST_I \
+  uPAD_SWDCK_I \
+  uPAD_VDD_3 \
+  uPAD_VSS_3 \
+  uPAD_VDDIO_3 \
+  uPAD_P1_00 \
+  uPAD_P1_01 \
+]
+
+create_io_guide -name {main_io.bottom} -side bottom -line {{1666.640 0.000} 1556.640 } -offset {0.000 0.000} -pad_cells [list \
+  uPAD_P0_02 \
+  uPAD_VDDACC_1 \
+  uPAD_SE_I \
+  uPAD_VDD_1 \
+  uPAD_VSS_1 \
+  uPAD_P0_01 \
+  uPAD_P0_00 \
+]
+
+create_io_guide -name {main_io.left} -side left -line {{0.000 110.000} 1555.600} -offset {0.000 0.000} -pad_cells [list \
+  uPAD_P0_04 \
+  uPAD_P0_05 \
+  uPAD_P0_03 \
+  uPAD_VDDACC_0 \
+  uPAD_VSS_0 \
+  uPAD_CLK_I \
+  uPAD_VDD_0 \
+  uPAD_VDDIO_0 \
+  uPAD_SWDIO_IO \
+  uPAD_VSSIO_0 \
+  uPAD_P0_06 \
+  uPAD_P0_07 \
+]
+
+create_io_guide -name {main_io.right} -side right -line {{1666.640 1555.600} 1555.600} -offset {0.000 0.000} -pad_cells [list \
+  uPAD_P1_04 \
+  uPAD_P1_05 \
+  uPAD_NRST_I \
+  uPAD_VDDIO_2 \
+  uPAD_VSS_2 \
+  uPAD_VDD_2 \
+  uPAD_VDDACC_2 \
+  uPAD_P1_02 \
+  uPAD_P1_03 \
+  uPAD_VSSIO_1 \
+  uPAD_P1_06 \
+  uPAD_P1_07 \
+]
+
 create_io_corner_cell {main_io.left main_io.top} -reference_cell PCORNER_G
 create_io_corner_cell {main_io.bottom main_io.left} -reference_cell PCORNER_G
 create_io_corner_cell {main_io.top main_io.right} -reference_cell PCORNER_G
 create_io_corner_cell {main_io.right main_io.bottom} -reference_cell PCORNER_G
 
+set_signal_io_constraints -io_guide_object {main_io.top} -constraint {{order_only} \
+  uPAD_TEST_I \
+  uPAD_SWDCK_I \
+  uPAD_VDD_3 \
+  uPAD_VSS_3 \
+  uPAD_VDDIO_3 \
+  uPAD_P1_00 \
+  uPAD_P1_01 \
+}
+
+set_signal_io_constraints -io_guide_object {main_io.bottom} -constraint {{order_only} \
+  uPAD_P0_00 \
+  uPAD_P0_01 \
+  uPAD_VSS_1 \
+  uPAD_VDD_1 \
+  uPAD_SE_I \
+  uPAD_VDDACC_1 \
+  uPAD_P0_02 \
+}
+
+set_signal_io_constraints -io_guide_object {main_io.left} -constraint {{order_only} \
+  uPAD_P0_04 \
+  uPAD_P0_05 \
+  uPAD_P0_03 \
+  uPAD_VDDACC_0 \
+  uPAD_VSS_0 \
+  uPAD_CLK_I \
+  uPAD_VDD_0 \
+  uPAD_VDDIO_0 \
+  uPAD_SWDIO_IO \
+  uPAD_VSSIO_0 \
+  uPAD_P0_06 \
+  uPAD_P0_07 \
+}
+
+set_signal_io_constraints -io_guide_object {main_io.right} -constraint {{order_only} \
+  uPAD_P1_04 \
+  uPAD_P1_05 \
+  uPAD_NRST_I \
+  uPAD_VDDIO_2 \
+  uPAD_VSS_2 \
+  uPAD_VDD_2 \
+  uPAD_VDDACC_2 \
+  uPAD_P1_02 \
+  uPAD_P1_03 \
+  uPAD_VSSIO_1 \
+  uPAD_P1_06 \
+  uPAD_P1_07 \
+}
+
 place_io
-create_io_filler_cells -io_guides [get_io_guides {main_io.top main_io.right main_io.bottom main_io.left}] -reference_cells PFILLER5_G -prefix io_filler
-create_io_filler_cells -io_guides [get_io_guides {main_io.top main_io.right main_io.bottom main_io.left}] -reference_cells PFILLER0005_G -prefix io_filler
+create_io_filler_cells -io_guides [get_io_guides {main_io.top main_io.right main_io.bottom main_io.left}] -reference_cells [list PFILLER20_G PFILLER10_G PFILLER5_G PFILLER0005_G ] -prefix io_filler
 
 
 # Power Plan
@@ -124,7 +264,7 @@ create_voltage_area -power_domains ACCEL
 # create_voltage_area -power_domains PD_SYS
  
 create_voltage_area_shape -voltage_area ACCEL \
-				-region {{{180.500 180.000} {925.150 1000.000}}} \
+				-region {{{135.000 135.000} {1432 1320}}} \
 				-guard_band {2 2}
 
 #create_voltage_area_shape -voltage_area PD_DBG \
@@ -234,6 +374,23 @@ redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
 explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_nanosoc_chip u_nanosoc_chip_cfg}]
 explore_logic_hierarchy -place -rectangular
 
+create_boundary_cells -left_boundary_cell [get_lib_cells {cln28ht/ENDCAPTIE3_A12PP140ZTS_C35}] -right_boundary_cell [get_lib_cells {cln28ht/ENDCAPTIE3_A12PP140ZTS_C35}]
+
+
+set timing_use_enhanced_capacitance_modeling true
+set_app_var compile_clock_gating_through_hierarchy true
+set timing_separate_clock_gating_group TRUE
+
+set_lib_cell_purpose -exclude hold {**}
+set_lib_cell_purpose -include hold {*DLY*}
+#set_lib_cell_purpose -include hold {*BUF*X0* INV*X0*}
+set_lib_cell_purpose -include cts  {*FRICG*}
+
+set_lib_cell_purpose -include none  {HEAD* FOOT*}
+set_lib_cell_purpose -include none  {HEAD* FOOT*}
+
+set_message_info -id ATTR-11 -limit  5
+get_lib_cells cln28ht/* -filter "valid_purposes(block) =~ *hold*"
 
 save_block 
 save_lib nanosoc_chip_pads.dlib
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/2_synthesis.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/2_synthesis.tcl
index 0ee623a9325017a0259e7c81519296b7bc889405..56dccc1b90da4ace5ade6a38d3d455c0b2c3a191 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/2_synthesis.tcl
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/2_synthesis.tcl
@@ -1,12 +1,22 @@
-open_lib nanosoc_chip_pads.dlib/
-open_block nanosoc_chip_pads
+#open_lib nanosoc_chip_pads.dlib/
+#open_block nanosoc_chip_pads
 
 set_host_options -max_cores 16 -num_processes 16
 set REPORT_DIR ../reports
 set LOG_DIR ../logs
 
-set_qor_strategy -stage synthesis -metric timing
+set_qor_strategy -stage synthesis -metric timing -high_effort_timing
 
+set_app_options -list {compile.flow.hold_area_budgeting {enhanced}}
+set_app_options -list {compile.flow.enable_multibit {true}}
+set_app_options -list {compile.flow.high_effort_timing {1}}
+set_app_options -list {compile.initial_place.buffering_aware_placement_effort {high}}
+set_app_options -list {compile.flow.high_effort_area {true}}
+set_app_options -list {compile.final_place.effort {high}}
+set_app_options -list {compile.early_place.effort {high}}
+
+set_app_options -list {compile.final_place.placement_congestion_effort {ultra}}
+set_app_options -list {compile.initial_opto.placement_congestion_effort {high}}
 
 # Compile fusion takes about 6.5 hrs to run
 set_stage -step synthesis
@@ -23,6 +33,13 @@ redirect -tee -file $REPORT_DIR/timing_02b_compile_fusion_max.rep {report_timing
 redirect -tee -file $REPORT_DIR/timing_02b_compile_fusion_min.rep {report_timing -delay_type min}
 
 redirect -tee -file $REPORT_DIR/qor_02_compile_fusion.rep {report_qor}
+
+# Hold time investigateion
+redirect -tee -file $REPORT_DIR/timing_global_compile_fusion_interclock.rep {report_global_timing -delay_type min -include inter_clock}
+redirect -tee -file $REPORT_DIR/timing_global_compile_fusion.rep {report_global_timing -delay_type min}
+redirect -tee -file $REPORT_DIR/timing_worst_path_detailed_compile_fusion.rep {report_timing -delay_type min -path_type full_clock_expanded -scenarios hold_scenario -from u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/u_acubed_ahb/myproject_/normalize_array_ap_fixed_64u_array_ap_fixed_16_9_0_0_0_64u_config15_U0/tmp_data_59_V_reg_11477_reg[15:12] -to u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/u_acubed_ahb/myproject_/layer15_out_V_data_59_V_U/U_fifo_w16_d1_A_ram/SRL_SIG_reg[0][15:12]}
+redirect -tee -file $REPORT_DIR/area_compiler_fusion.rep {report_area}
+
 save_block
 save_lib nanosoc_chip_pads.dlib
 
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/3_clock.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/3_clock.tcl
index f04e1e2910183ab1a5939e0cd94f78addeb82c39..95b46ced2f3e2c9b9b0eeb9a6e982a6a84b80555 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/3_clock.tcl
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/3_clock.tcl
@@ -1,10 +1,13 @@
-open_lib nanosoc_chip_pads.dlib/
-open_block nanosoc_chip_pads
+#open_lib nanosoc_chip_pads.dlib/
+#open_block nanosoc_chip_pads
 
 set_host_options -max_cores 16 -num_processes 16
 set REPORT_DIR ../reports
 set LOG_DIR ../logs
 
+redirect -tee -file $REPORT_DIR/glob_min_timing_prects.rep {report_global_timing -delay_type min}
+
+
 # Clock opt cts
 set_stage -step cts
 
@@ -26,8 +29,13 @@ redirect -tee -file $REPORT_DIR/timing_03c_CTS_max.rep {report_timing -delay_typ
 redirect -tee -file $REPORT_DIR/timing_03c_CTS_min.rep {report_timing -delay_type min}
 
 redirect -tee -file $REPORT_DIR/qor_03_CTS.rep {report_qor}
+redirect -tee -file $REPORT_DIR/glob_min_timing_postcts.rep {report_global_timing -delay_type min}
+redirect -tee -file $REPORT_DIR/post_clock_opt_dly_collection {sizeof_collection [get_cells -physical_context *_h_inst*]}
+
+redirect -tee -file $REPORT_DIR/timing_global_post_cts_interclock.rep {report_global_timing -delay_type min -include inter_clock}
+redirect -tee -file $REPORT_DIR/timing_worst_path_detailed_post_cts.rep {report_timing -delay_type min -path_type full_clock_expanded -scenarios hold_scenario -from u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/u_acubed_ahb/myproject_/normalize_array_ap_fixed_64u_array_ap_fixed_16_9_0_0_0_64u_config15_U0/tmp_data_59_V_reg_11477_reg[15:12] -to u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/u_acubed_ahb/myproject_/layer15_out_V_data_59_V_U/U_fifo_w16_d1_A_ram/SRL_SIG_reg[0][15:12]}
 
 save_block
-save_lib nanosoc_chip_pads.dlib
+#save_lib nanosoc_chip_pads.dlib
 
 exit
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/4_route.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/4_route.tcl
index 0c8af2c1454a3d772001c0d51688d5c3ef084972..58ef2bcd22a4f11779f73b28d137f2114f5f4924 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/4_route.tcl
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/4_route.tcl
@@ -1,5 +1,5 @@
-open_lib nanosoc_chip_pads.dlib/
-open_block nanosoc_chip_pads
+#open_lib nanosoc_chip_pads.dlib/
+#open_block nanosoc_chip_pads
 
 set_host_options -max_cores 16 -num_processes 16
 set REPORT_DIR ../reports
diff --git a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/synopsys_lib_conversion.tcl
index e4789845dc1c6674ede6ec582cab3c69c6e749fa..19b709633f98ce9c738c42dba835fa33ede436ef 100644
--- a/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/synopsys_lib_conversion.tcl
+++ b/ASIC/TSMC28nm/38pin/Synopsys_FC/scripts/synopsys_lib_conversion.tcl
@@ -3,26 +3,53 @@ set cln28ht_tech_path           /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/
 set standard_cell_base_path     /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
 set pmk_base_path               /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_pmk_svt_c35/r1p0
 set ret_base_path               /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_rklo_lvt_svt_c30_c35/r1p0
-
+set hpc_base_path               /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_hpk_svt_c35/r1p0
 # Technology files
 set cln28ht_tech_file                       $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf
 set cln28ht_lef_file                        $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.lef
 
 # Standard Cell libraries
-set standard_cell_lef_file                  $standard_cell_base_path/lef/sc12mcpp140z_cln28ht_base_svt_c35.lef
-set standard_cell_gds_file                  $standard_cell_base_path/gds2/sc12mcpp140z_cln28ht_base_svt_c35.gds2
-set standard_cell_db_file_ss_0p81v_125C     $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
-set standard_cell_db_file_tt_0p90v_25C      $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
-set standard_cell_db_file_ff_0p99v_m40C     $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
-set standard_cell_antenna_file              $standard_cell_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_base_svt_c35_antenna.clf
+set standard_cell_lef_file                      $standard_cell_base_path/lef/sc12mcpp140z_cln28ht_base_svt_c35.lef
+set standard_cell_gds_file                      $standard_cell_base_path/gds2/sc12mcpp140z_cln28ht_base_svt_c35.gds2
+set standard_cell_antenna_file                  $standard_cell_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_base_svt_c35_antenna.clf
+set db_base_svt_c35_ffg_cbestt_min_0p99v_0c     $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_0c.db_ccs_tn      
+set db_base_svt_c35_ffg_cbestt_min_0p99v_125c   $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_125c.db_ccs_tn    
+set db_base_svt_c35_ffg_cbestt_min_0p99v_m40c   $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db_ccs_tn    
+set db_base_svt_c35_ffg_ctypical_max_0p90v_85c  $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ffg_ctypical_max_0p90v_85c.db_ccs_tn   
+set db_base_svt_c35_ffg_ctypical_max_0p99v_125c $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ffg_ctypical_max_0p99v_125c.db_ccs_tn  
+set db_base_svt_c35_ssg_cworstt_max_0p81v_0c    $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_0c.db_ccs_tn
+set db_base_svt_c35_ssg_cworstt_max_0p81v_125c  $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db_ccs_tn
+set db_base_svt_c35_ssg_cworstt_max_0p81v_m40c  $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_m40c.db_ccs_tn
+set db_base_svt_c35_ssg_cworstt_max_0p90v_0c    $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p90v_0c.db_ccs_tn
+set db_base_svt_c35_ssg_cworstt_max_0p90v_125c  $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p90v_125c.db_ccs_tn
+set db_base_svt_c35_ssg_cworstt_max_0p90v_m40c  $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p90v_m40c.db_ccs_tn
+set db_base_svt_c35_tt_ctypical_max_0p81v_0c    $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p81v_0c.db_ccs_tn
+set db_base_svt_c35_tt_ctypical_max_0p90v_0c    $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_0c.db_ccs_tn
+set db_base_svt_c35_tt_ctypical_max_0p90v_125c  $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_125c.db_ccs_tn
+set db_base_svt_c35_tt_ctypical_max_0p90v_25c   $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db_ccs_tn
+set db_base_svt_c35_tt_ctypical_max_0p90v_85c   $standard_cell_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_85c.db_ccs_tn
 
 # Power Management Kit 
-set pmk_lef_file                            $pmk_base_path/lef/sc12mcpp140z_cln28ht_pmk_svt_c35.lef
-set pmk_gds_file                            $pmk_base_path/gds2/sc12mcpp140z_cln28ht_pmk_svt_c35.gds2
-set pmk_db_file_ss_0p81v_125C               $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p81v_125c.db
-set pmk_db_file_tt_0p90v_25C                $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_25c.db
-set pmk_db_file_ff_0p99v_m40C               $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_cbestt_min_0p99v_m40c.db
-set pmk_antenna_file                        $pmk_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_pmk_svt_c35_antenna.clf
+set pmk_lef_file                                $pmk_base_path/lef/sc12mcpp140z_cln28ht_pmk_svt_c35.lef
+set pmk_gds_file                                $pmk_base_path/gds2/sc12mcpp140z_cln28ht_pmk_svt_c35.gds2
+set pmk_antenna_file                            $pmk_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_pmk_svt_c35_antenna.clf
+set db_pmk_svt_c35_ffg_cbestt_min_0p99v_0c      $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_cbestt_min_0p99v_0c.db_ccs_tn      
+set db_pmk_svt_c35_ffg_cbestt_min_0p99v_125c    $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_cbestt_min_0p99v_125c.db_ccs_tn    
+set db_pmk_svt_c35_ffg_cbestt_min_0p99v_m40c    $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_cbestt_min_0p99v_m40c.db_ccs_tn    
+set db_pmk_svt_c35_ffg_ctypical_max_0p90v_85c   $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_ctypical_max_0p90v_85c.db_ccs_tn   
+set db_pmk_svt_c35_ffg_ctypical_max_0p99v_125c  $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_ctypical_max_0p99v_125c.db_ccs_tn  
+set db_pmk_svt_c35_ssg_cworstt_max_0p81v_0c     $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p81v_0c.db_ccs_tn
+set db_pmk_svt_c35_ssg_cworstt_max_0p81v_125c   $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p81v_125c.db_ccs_tn
+set db_pmk_svt_c35_ssg_cworstt_max_0p81v_m40c   $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p81v_m40c.db_ccs_tn
+set db_pmk_svt_c35_ssg_cworstt_max_0p90v_0c     $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p90v_0c.db_ccs_tn
+set db_pmk_svt_c35_ssg_cworstt_max_0p90v_125c   $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p90v_125c.db_ccs_tn
+set db_pmk_svt_c35_ssg_cworstt_max_0p90v_m40c   $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p90v_m40c.db_ccs_tn
+set db_pmk_svt_c35_tt_ctypical_max_0p81v_0c     $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p81v_0c.db_ccs_tn
+set db_pmk_svt_c35_tt_ctypical_max_0p90v_0c     $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_0c.db_ccs_tn
+set db_pmk_svt_c35_tt_ctypical_max_0p90v_125c   $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_125c.db_ccs_tn
+set db_pmk_svt_c35_tt_ctypical_max_0p90v_25c    $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_25c.db_ccs_tn
+set db_pmk_svt_c35_tt_ctypical_max_0p90v_85c    $pmk_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_85c.db_ccs_tn
+
 
 # Retention Kit
 set ret_lef_file                            $ret_base_path/lef/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.lef
@@ -31,6 +58,46 @@ set ret_db_file_ss_0p81v_125C               $ret_base_path/db/sc12mcpp140z_cln28
 set ret_db_file_tt_0p90v_25C                $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_25c.db
 set ret_db_file_ff_0p99v_m40C               $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_cbestt_min_0p99v_m40c.db
 set ret_antenna_file                        $ret_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_antenna.clf
+set db_ret_c35_ffg_cbestt_min_0p99v_0c      $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_cbestt_min_0p99v_0c.db_ccs_tn      
+set db_ret_c35_ffg_cbestt_min_0p99v_125c    $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_cbestt_min_0p99v_125c.db_ccs_tn    
+set db_ret_c35_ffg_cbestt_min_0p99v_m40c    $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_cbestt_min_0p99v_m40c.db_ccs_tn    
+set db_ret_c35_ffg_ctypical_max_0p90v_85c   $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_ctypical_max_0p90v_85c.db_ccs_tn   
+set db_ret_c35_ffg_ctypical_max_0p99v_125c  $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_ctypical_max_0p99v_125c.db_ccs_tn  
+set db_ret_c35_ssg_cworstt_max_0p81v_0c     $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p81v_0c.db_ccs_tn
+set db_ret_c35_ssg_cworstt_max_0p81v_125c   $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p81v_125c.db_ccs_tn
+set db_ret_c35_ssg_cworstt_max_0p81v_m40c   $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p81v_m40c.db_ccs_tn
+set db_ret_c35_ssg_cworstt_max_0p90v_0c     $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p90v_0c.db_ccs_tn
+set db_ret_c35_ssg_cworstt_max_0p90v_125c   $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p90v_125c.db_ccs_tn
+set db_ret_c35_ssg_cworstt_max_0p90v_m40c   $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p90v_m40c.db_ccs_tn
+set db_ret_c35_tt_ctypical_max_0p81v_0c     $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p81v_0c.db_ccs_tn
+set db_ret_c35_tt_ctypical_max_0p90v_0c     $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_0c.db_ccs_tn
+set db_ret_c35_tt_ctypical_max_0p90v_125c   $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_125c.db_ccs_tn
+set db_ret_c35_tt_ctypical_max_0p90v_25c    $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_25c.db_ccs_tn
+set db_ret_c35_tt_ctypical_max_0p90v_85c    $ret_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_85c.db_ccs_tn
+
+# High Performance Kit
+set hpc_lef_file                            $hpc_base_path/lef/sc12mcpp140z_cln28ht_hpk_svt_c35.lef
+set hpc_gds_file                            $hpc_base_path/gds2/sc12mcpp140z_cln28ht_hpk_svt_c35.gds2
+set hpc_db_file_ss_0p81v_125C               $hpc_base_path/db/sc12mcpp140z_cln28ht_hpk_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set hpc_db_file_tt_0p90v_25C                $hpc_base_path/db/sc12mcpp140z_cln28ht_hpk_svt_c35_tt_ctypical_max_0p90v_25c.db
+set hpc_db_file_ff_0p99v_m40C               $hpc_base_path/db/sc12mcpp140z_cln28ht_hpk_svt_c35_ffg_cbestt_min_0p99v_m40c.db
+set hpc_antenna_file                        $hpc_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_hpk_svt_c35_antenna.clf
+set db_hpk_c35_ffg_cbestt_min_0p99v_0c      $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ffg_cbestt_min_0p99v_0c.db_ccs_tn      
+set db_hpk_c35_ffg_cbestt_min_0p99v_125c    $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ffg_cbestt_min_0p99v_125c.db_ccs_tn    
+set db_hpk_c35_ffg_cbestt_min_0p99v_m40c    $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ffg_cbestt_min_0p99v_m40c.db_ccs_tn    
+set db_hpk_c35_ffg_ctypical_max_0p90v_85c   $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ffg_ctypical_max_0p90v_85c.db_ccs_tn   
+set db_hpk_c35_ffg_ctypical_max_0p99v_125c  $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ffg_ctypical_max_0p99v_125c.db_ccs_tn  
+set db_hpk_c35_ssg_cworstt_max_0p81v_0c     $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ssg_cworstt_max_0p81v_0c.db_ccs_tn
+set db_hpk_c35_ssg_cworstt_max_0p81v_125c   $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ssg_cworstt_max_0p81v_125c.db_ccs_tn
+set db_hpk_c35_ssg_cworstt_max_0p81v_m40c   $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ssg_cworstt_max_0p81v_m40c.db_ccs_tn
+set db_hpk_c35_ssg_cworstt_max_0p90v_0c     $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ssg_cworstt_max_0p90v_0c.db_ccs_tn
+set db_hpk_c35_ssg_cworstt_max_0p90v_125c   $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ssg_cworstt_max_0p90v_125c.db_ccs_tn
+set db_hpk_c35_ssg_cworstt_max_0p90v_m40c   $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_ssg_cworstt_max_0p90v_m40c.db_ccs_tn
+set db_hpk_c35_tt_ctypical_max_0p81v_0c     $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_tt_ctypical_max_0p81v_0c.db_ccs_tn
+set db_hpk_c35_tt_ctypical_max_0p90v_0c     $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_tt_ctypical_max_0p90v_0c.db_ccs_tn
+set db_hpk_c35_tt_ctypical_max_0p90v_125c   $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_tt_ctypical_max_0p90v_125c.db_ccs_tn
+set db_hpk_c35_tt_ctypical_max_0p90v_25c    $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_tt_ctypical_max_0p90v_25c.db_ccs_tn
+set db_hpk_c35_tt_ctypical_max_0p90v_85c    $hpc_base_path/db-ccs-tn/sc12mcpp140z_cln28ht_hpk_svt_c35_tt_ctypical_max_0p90v_85c.db_ccs_tn
 
 
 # IO Paths
@@ -42,69 +109,66 @@ set IO_FF_0p99v_1p98v_m40c_db   $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ffg0p99v1
 set IO_SS_0p81v_1p62v_125c_db   $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ssg0p81v1p62v125c.db
 
 set pad_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
-set bump_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/fc/fc_eu/MTRDL/8m/8M_Z/lef/tpbn28v_8lm.lef
 
 # SRAM files (using Arm compiler)
 set sram_16k_path                       $env(SOCLABS_PROJECT_DIR)/memories/sram_16k
 set sram_16k_lef_file                   $sram_16k_path/sram_16k.lef
 set sram_16k_gds_file                   $sram_16k_path/sram_16k.gds2
-set sram_16k_lib_file_ss_0p81v_125c     $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib
-set sram_16k_lib_file_tt_0p90v_25c      $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.lib
-set sram_16k_lib_file_ff_0p99v_m40c     $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
-set sram_16k_db_file_ss_0p81v_125c      $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db
-set sram_16k_db_file_tt_0p90v_25c       $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.db
-set sram_16k_db_file_ff_0p99v_m40c      $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db
-
-set sram_32k_path                       $env(SOCLABS_PROJECT_DIR)/memories/sram_32k
-set sram_32k_lef_file                   $sram_32k_path/sram_32k.lef
-set sram_32k_gds_file                   $sram_32k_path/sram_32k.gds2
-set sram_32k_lib_file_ss_0p81v_125c     $sram_32k_path/sram_32k_ssg_cworstt_0p81v_0p81v_125c.lib
-set sram_32k_lib_file_tt_0p90v_25c      $sram_32k_path/sram_32k_tt_ctypical_0p90v_0p90v_25c.lib
-set sram_32k_lib_file_ff_0p99v_m40c     $sram_32k_path/sram_32k_ffg_cbestt_0p99v_0p99v_m40c.lib
-set sram_32k_db_file_ss_0p81v_125c      $sram_32k_path/sram_32k_ssg_cworstt_0p81v_0p81v_125c.db
-set sram_32k_db_file_tt_0p90v_25c       $sram_32k_path/sram_32k_tt_ctypical_0p90v_0p90v_25c.db
-set sram_32k_db_file_ff_0p99v_m40c      $sram_32k_path/sram_32k_ffg_cbestt_0p99v_0p99v_m40c.db
-
-set sram_64k_path                       $env(SOCLABS_PROJECT_DIR)/memories/sram_64k
-set sram_64k_lef_file                   $sram_64k_path/sram_64k.lef
-set sram_64k_gds_file                   $sram_64k_path/sram_64k.gds2
-set sram_64k_lib_file_ss_0p81v_125c     $sram_64k_path/sram_64k_ssg_cworstt_0p81v_0p81v_125c.lib
-set sram_64k_lib_file_tt_0p90v_25c      $sram_64k_path/sram_64k_tt_ctypical_0p90v_0p90v_25c.lib
-set sram_64k_lib_file_ff_0p99v_m40c     $sram_64k_path/sram_64k_ffg_cbestt_0p99v_0p99v_m40c.lib
-set sram_64k_db_file_ss_0p81v_125c      $sram_64k_path/sram_64k_ssg_cworstt_0p81v_0p81v_125c.db
-set sram_64k_db_file_tt_0p90v_25c       $sram_64k_path/sram_64k_tt_ctypical_0p90v_0p90v_25c.db
-set sram_64k_db_file_ff_0p99v_m40c      $sram_64k_path/sram_64k_ffg_cbestt_0p99v_0p99v_m40c.db
-
-set sram_flash_data_path                    $env(SOCLABS_PROJECT_DIR)/memories/sram_flash_data
-set sram_flash_cache_lef_file               $sram_flash_data_path/sram_flash_cache.lef
-set sram_flash_cache_gds_file               $sram_flash_data_path/sram_flash_cache.gds2
-set sram_flash_cache_lib_file_ss_0p81v_125c $sram_flash_data_path/sram_flash_cache_ssg_cworstt_0p81v_0p81v_125c.lib
-set sram_flash_cache_lib_file_tt_0p90v_25c  $sram_flash_data_path/sram_flash_cache_tt_ctypical_0p90v_0p90v_25c.lib
-set sram_flash_cache_lib_file_ff_0p99v_m40c $sram_flash_data_path/sram_flash_cache_ffg_cbestt_0p99v_0p99v_m40c.lib
-set sram_flash_cache_db_file_ss_0p81v_125c  $sram_flash_data_path/sram_flash_cache_ssg_cworstt_0p81v_0p81v_125c.db
-set sram_flash_cache_db_file_tt_0p90v_25c   $sram_flash_data_path/sram_flash_cache_tt_ctypical_0p90v_0p90v_25c.db
-set sram_flash_cache_db_file_ff_0p99v_m40c  $sram_flash_data_path/sram_flash_cache_ffg_cbestt_0p99v_0p99v_m40c.db
-
-set sram_flash_tag_path                     $env(SOCLABS_PROJECT_DIR)/memories/sram_flash_tag
-set sram_flash_tag_lef_file                 $sram_flash_tag_path/sram_flash_tag.lef
-set sram_flash_tag_gds_file                 $sram_flash_tag_path/sram_flash_tag.gds2
-set sram_flash_tag_lib_file_ss_0p81v_125c   $sram_flash_tag_path/sram_flash_tag_ssg_cworstt_0p81v_0p81v_125c.lib
-set sram_flash_tag_lib_file_tt_0p90v_25c    $sram_flash_tag_path/sram_flash_tag_tt_ctypical_0p90v_0p90v_25c.lib
-set sram_flash_tag_lib_file_ff_0p99v_m40c   $sram_flash_tag_path/sram_flash_tag_ffg_cbestt_0p99v_0p99v_m40c.lib
-set sram_flash_tag_db_file_ss_0p81v_125c    $sram_flash_tag_path/sram_flash_tag_ssg_cworstt_0p81v_0p81v_125c.db
-set sram_flash_tag_db_file_tt_0p90v_25c     $sram_flash_tag_path/sram_flash_tag_tt_ctypical_0p90v_0p90v_25c.db
-set sram_flash_tag_db_file_ff_0p99v_m40c    $sram_flash_tag_path/sram_flash_tag_ffg_cbestt_0p99v_0p99v_m40c.db
+set lib_sram_16k_ffg_cbestt_0p99v_0c     $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_0c.lib    
+set lib_sram_16k_ffg_cbestt_0p99v_125c   $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_125c.lib  
+set lib_sram_16k_ffg_cbestt_0p99v_m40c   $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.lib  
+set lib_sram_16k_ffg_ctypical_0p90v_85c  $sram_16k_path/sram_16k_ffg_ctypical_0p90v_0p90v_85c.lib   
+set lib_sram_16k_ffg_ctypical_0p99v_125c $sram_16k_path/sram_16k_ffg_ctypical_0p99v_0p99v_125c.lib  
+set lib_sram_16k_ssg_cworstt_0p81v_m40c  $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_m40c.lib  
+set lib_sram_16k_ssg_cworstt_0p81v_0c    $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_0c.lib     
+set lib_sram_16k_ssg_cworstt_0p81v_125c  $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.lib  
+set lib_sram_16k_tt_ctypical_0p81v_0c    $sram_16k_path/sram_16k_tt_ctypical_0p81v_0p81v_0c.lib   
+set lib_sram_16k_tt_ctypical_0p90v_25c   $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.lib
+set lib_sram_16k_tt_ctypical_0p90v_85c   $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.lib
+set lib_sram_16k_tt_ctypical_0p90v_125c  $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_125c.lib
+
+set db_sram_16k_ffg_cbestt_0p99v_0c     $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_0c.db    
+set db_sram_16k_ffg_cbestt_0p99v_125c   $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_125c.db  
+set db_sram_16k_ffg_cbestt_0p99v_m40c   $sram_16k_path/sram_16k_ffg_cbestt_0p99v_0p99v_m40c.db  
+set db_sram_16k_ffg_ctypical_0p90v_85c  $sram_16k_path/sram_16k_ffg_ctypical_0p90v_0p90v_85c.db   
+set db_sram_16k_ffg_ctypical_0p99v_125c $sram_16k_path/sram_16k_ffg_ctypical_0p99v_0p99v_125c.db  
+set db_sram_16k_ssg_cworstt_0p81v_m40c  $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_m40c.db  
+set db_sram_16k_ssg_cworstt_0p81v_0c    $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_0c.db     
+set db_sram_16k_ssg_cworstt_0p81v_125c  $sram_16k_path/sram_16k_ssg_cworstt_0p81v_0p81v_125c.db  
+set db_sram_16k_tt_ctypical_0p81v_0c    $sram_16k_path/sram_16k_tt_ctypical_0p81v_0p81v_0c.db   
+set db_sram_16k_tt_ctypical_0p90v_25c   $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_25c.db
+set db_sram_16k_tt_ctypical_0p90v_85c   $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_85c.db
+set db_sram_16k_tt_ctypical_0p90v_125c  $sram_16k_path/sram_16k_tt_ctypical_0p90v_0p90v_125c.db
 
 # ROM Files (using arm Compiler)
 set rom_path                        $env(SOCLABS_PROJECT_DIR)/memories/bootrom
 set rom_via_lef_file                $rom_path/rom_via.lef       
 set rom_via_gds_file                $rom_path/rom_via.gds2
-set rom_via_lib_file_ss_0p81v_125c  $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.lib
-set rom_via_lib_file_tt_0p90v_25c   $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
-set rom_via_lib_file_ff_0p99v_m40c  $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.lib
-set rom_via_db_file_ss_0p81v_125c   $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.db
-set rom_via_db_file_tt_0p90v_25c    $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
-set rom_via_db_file_ff_0p99v_m40c   $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db
+set lib_rom_ffg_cbestt_0p99v_0c     $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_0c.lib    
+set lib_rom_ffg_cbestt_0p99v_125c   $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_125c.lib  
+set lib_rom_ffg_cbestt_0p99v_m40c   $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.lib  
+set lib_rom_ffg_ctypical_0p90v_85c  $rom_path/rom_via_ffg_ctypical_0p90v_0p90v_85c.lib   
+set lib_rom_ffg_ctypical_0p99v_125c $rom_path/rom_via_ffg_ctypical_0p99v_0p99v_125c.lib  
+set lib_rom_ssg_cworstt_0p81v_m40c  $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_m40c.lib  
+set lib_rom_ssg_cworstt_0p81v_0c    $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_0c.lib     
+set lib_rom_ssg_cworstt_0p81v_125c  $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.lib  
+set lib_rom_tt_ctypical_0p81v_0c    $rom_path/rom_via_tt_ctypical_0p81v_0p81v_0c.lib   
+set lib_rom_tt_ctypical_0p90v_25c   $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.lib
+set lib_rom_tt_ctypical_0p90v_85c   $rom_path/rom_via_tt_ctypical_0p90v_0p90v_85c.lib
+set lib_rom_tt_ctypical_0p90v_125c  $rom_path/rom_via_tt_ctypical_0p90v_0p90v_125c.lib
+
+set db_rom_ffg_cbestt_0p99v_0c     $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_0c.db    
+set db_rom_ffg_cbestt_0p99v_125c   $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_125c.db  
+set db_rom_ffg_cbestt_0p99v_m40c   $rom_path/rom_via_ffg_cbestt_0p99v_0p99v_m40c.db  
+set db_rom_ffg_ctypical_0p90v_85c  $rom_path/rom_via_ffg_ctypical_0p90v_0p90v_85c.db   
+set db_rom_ffg_ctypical_0p99v_125c $rom_path/rom_via_ffg_ctypical_0p99v_0p99v_125c.db  
+set db_rom_ssg_cworstt_0p81v_m40c  $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_m40c.db  
+set db_rom_ssg_cworstt_0p81v_0c    $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_0c.db     
+set db_rom_ssg_cworstt_0p81v_125c  $rom_path/rom_via_ssg_cworstt_0p81v_0p81v_125c.db  
+set db_rom_tt_ctypical_0p81v_0c    $rom_path/rom_via_tt_ctypical_0p81v_0p81v_0c.db   
+set db_rom_tt_ctypical_0p90v_25c   $rom_path/rom_via_tt_ctypical_0p90v_0p90v_25c.db
+set db_rom_tt_ctypical_0p90v_85c   $rom_path/rom_via_tt_ctypical_0p90v_0p90v_85c.db
+set db_rom_tt_ctypical_0p90v_125c  $rom_path/rom_via_tt_ctypical_0p90v_0p90v_125c.db
 
 # Synopsys PLL files
 set Synopsys_PLL_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro
@@ -134,85 +198,224 @@ set Synopsys_VM_db_file     $Synopsys_VM_dir/db/mr74140_wc_vmin_125c.db
 set Synopsys_VM_gds_file    $Synopsys_VM_dir/gdsii/mr74140_v1r1.gds
 
 # Create standard cell fusion library
-create_fusion_lib -dbs [list $standard_cell_db_file_ss_0p81v_125C $standard_cell_db_file_tt_0p90v_25C $standard_cell_db_file_ff_0p99v_m40C]  -lefs [list $cln28ht_lef_file $standard_cell_lef_file] -technology $cln28ht_tech_file cln28ht
+create_fusion_lib -dbs [list \
+    $db_base_svt_c35_ffg_cbestt_min_0p99v_0c \
+    $db_base_svt_c35_ffg_cbestt_min_0p99v_125c \
+    $db_base_svt_c35_ffg_cbestt_min_0p99v_m40c \
+    $db_base_svt_c35_ffg_ctypical_max_0p90v_85c \
+    $db_base_svt_c35_ffg_ctypical_max_0p99v_125c \
+    $db_base_svt_c35_ssg_cworstt_max_0p81v_0c \
+    $db_base_svt_c35_ssg_cworstt_max_0p81v_125c \
+    $db_base_svt_c35_ssg_cworstt_max_0p81v_m40c \
+    $db_base_svt_c35_ssg_cworstt_max_0p90v_0c \
+    $db_base_svt_c35_ssg_cworstt_max_0p90v_125c \
+    $db_base_svt_c35_ssg_cworstt_max_0p90v_m40c \
+    $db_base_svt_c35_tt_ctypical_max_0p81v_0c \
+    $db_base_svt_c35_tt_ctypical_max_0p90v_0c \
+    $db_base_svt_c35_tt_ctypical_max_0p90v_125c \
+    $db_base_svt_c35_tt_ctypical_max_0p90v_25c \
+    $db_base_svt_c35_tt_ctypical_max_0p90v_85c ] \
+     -lefs [list $cln28ht_lef_file $standard_cell_lef_file] -technology $cln28ht_tech_file cln28ht
 save_fusion_lib cln28ht
 close_fusion_lib cln28ht
 
 # Create Power Management Kit fusion library
-create_fusion_lib -dbs [list $pmk_db_file_ss_0p81v_125C $pmk_db_file_tt_0p90v_25C $pmk_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $pmk_lef_file] -technology $cln28ht_tech_file cln28ht_pmk
+create_fusion_lib -dbs [list \
+    $db_pmk_svt_c35_ffg_cbestt_min_0p99v_0c \
+    $db_pmk_svt_c35_ffg_cbestt_min_0p99v_125c \
+    $db_pmk_svt_c35_ffg_cbestt_min_0p99v_m40c \
+    $db_pmk_svt_c35_ffg_ctypical_max_0p90v_85c \
+    $db_pmk_svt_c35_ffg_ctypical_max_0p99v_125c \
+    $db_pmk_svt_c35_ssg_cworstt_max_0p81v_0c \
+    $db_pmk_svt_c35_ssg_cworstt_max_0p81v_125c \
+    $db_pmk_svt_c35_ssg_cworstt_max_0p81v_m40c \
+    $db_pmk_svt_c35_ssg_cworstt_max_0p90v_0c \
+    $db_pmk_svt_c35_ssg_cworstt_max_0p90v_125c \
+    $db_pmk_svt_c35_ssg_cworstt_max_0p90v_m40c \
+    $db_pmk_svt_c35_tt_ctypical_max_0p81v_0c \
+    $db_pmk_svt_c35_tt_ctypical_max_0p90v_0c \
+    $db_pmk_svt_c35_tt_ctypical_max_0p90v_125c \
+    $db_pmk_svt_c35_tt_ctypical_max_0p90v_25c \
+    $db_pmk_svt_c35_tt_ctypical_max_0p90v_85c ] \
+     -lefs [list $cln28ht_lef_file $pmk_lef_file] -technology $cln28ht_tech_file cln28ht_pmk
 save_fusion_lib cln28ht_pmk
 close_fusion_lib cln28ht_pmk
 
 # Create Retention fusion library
-create_fusion_lib -dbs [list $ret_db_file_ss_0p81v_125C $ret_db_file_tt_0p90v_25C $ret_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $ret_lef_file] -technology $cln28ht_tech_file cln28ht_ret
+create_fusion_lib -dbs [list \
+    $db_ret_c35_ffg_cbestt_min_0p99v_0c \
+    $db_ret_c35_ffg_cbestt_min_0p99v_125c \
+    $db_ret_c35_ffg_cbestt_min_0p99v_m40c \
+    $db_ret_c35_ffg_ctypical_max_0p90v_85c \
+    $db_ret_c35_ffg_ctypical_max_0p99v_125c \
+    $db_ret_c35_ssg_cworstt_max_0p81v_0c \
+    $db_ret_c35_ssg_cworstt_max_0p81v_125c \
+    $db_ret_c35_ssg_cworstt_max_0p81v_m40c \
+    $db_ret_c35_ssg_cworstt_max_0p90v_0c \
+    $db_ret_c35_ssg_cworstt_max_0p90v_125c \
+    $db_ret_c35_ssg_cworstt_max_0p90v_m40c \
+    $db_ret_c35_tt_ctypical_max_0p81v_0c \
+    $db_ret_c35_tt_ctypical_max_0p90v_0c \
+    $db_ret_c35_tt_ctypical_max_0p90v_125c \
+    $db_ret_c35_tt_ctypical_max_0p90v_25c \
+    $db_ret_c35_tt_ctypical_max_0p90v_85c ] \
+     -lefs [list $cln28ht_lef_file $ret_lef_file] -technology $cln28ht_tech_file cln28ht_ret
 save_fusion_lib cln28ht_ret
 close_fusion_lib cln28ht_ret
 
+# Create High Performance Kit fusion library
+create_fusion_lib -dbs [list \
+    $db_hpk_c35_ffg_cbestt_min_0p99v_0c \
+    $db_hpk_c35_ffg_cbestt_min_0p99v_125c \
+    $db_hpk_c35_ffg_cbestt_min_0p99v_m40c \
+    $db_hpk_c35_ffg_ctypical_max_0p90v_85c \
+    $db_hpk_c35_ffg_ctypical_max_0p99v_125c \
+    $db_hpk_c35_ssg_cworstt_max_0p81v_0c \
+    $db_hpk_c35_ssg_cworstt_max_0p81v_125c \
+    $db_hpk_c35_ssg_cworstt_max_0p81v_m40c \
+    $db_hpk_c35_ssg_cworstt_max_0p90v_0c \
+    $db_hpk_c35_ssg_cworstt_max_0p90v_125c \
+    $db_hpk_c35_ssg_cworstt_max_0p90v_m40c \
+    $db_hpk_c35_tt_ctypical_max_0p81v_0c \
+    $db_hpk_c35_tt_ctypical_max_0p90v_0c \
+    $db_hpk_c35_tt_ctypical_max_0p90v_125c \
+    $db_hpk_c35_tt_ctypical_max_0p90v_25c \
+    $db_hpk_c35_tt_ctypical_max_0p90v_85c ] \
+     -lefs [list $cln28ht_lef_file $hpc_lef_file] -technology $cln28ht_tech_file cln28ht_hpk
+save_fusion_lib cln28ht_hpk
+close_fusion_lib cln28ht_hpk
+
+
 # 16K SRAM
-read_lib $sram_16k_lib_file_ss_0p81v_125c 
-write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_125c
+read_lib $lib_sram_16k_ffg_cbestt_0p99v_0c 
+write_lib -output $db_sram_16k_ffg_cbestt_0p99v_0c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_0c
+close_lib -all
+
+read_lib $lib_sram_16k_ffg_cbestt_0p99v_125c 
+write_lib -output $db_sram_16k_ffg_cbestt_0p99v_125c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_125c
+close_lib -all
+
+read_lib $lib_sram_16k_ffg_cbestt_0p99v_m40c 
+write_lib -output $db_sram_16k_ffg_cbestt_0p99v_m40c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_m40c
 close_lib -all
 
-read_lib $sram_16k_lib_file_tt_0p90v_25c 
-write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_25c
+read_lib $lib_sram_16k_ffg_ctypical_0p90v_85c 
+write_lib -output $db_sram_16k_ffg_ctypical_0p90v_85c -format db SRAM_16K_ffg_ctypical_0p90v_0p90v_85c
 close_lib -all
 
-read_lib $sram_16k_lib_file_ff_0p99v_m40c 
-write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db SRAM_16K_ffg_cbestt_0p99v_0p99v_m40c
+read_lib $lib_sram_16k_ffg_ctypical_0p99v_125c 
+write_lib -output $db_sram_16k_ffg_ctypical_0p99v_125c -format db SRAM_16K_ffg_ctypical_0p99v_0p99v_125c
 close_lib -all
 
-create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_tt_0p90v_25c $sram_16k_db_file_ff_0p99v_m40c] -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
+read_lib $lib_sram_16k_ssg_cworstt_0p81v_m40c 
+write_lib -output $db_sram_16k_ssg_cworstt_0p81v_m40c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_m40c
+close_lib -all
+
+read_lib $lib_sram_16k_ssg_cworstt_0p81v_0c 
+write_lib -output $db_sram_16k_ssg_cworstt_0p81v_0c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_0c
+close_lib -all
+
+read_lib $lib_sram_16k_ssg_cworstt_0p81v_125c 
+write_lib -output $db_sram_16k_ssg_cworstt_0p81v_125c -format db SRAM_16K_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
+
+read_lib $lib_sram_16k_tt_ctypical_0p81v_0c 
+write_lib -output $db_sram_16k_tt_ctypical_0p81v_0c -format db SRAM_16K_tt_ctypical_0p81v_0p81v_0c
+close_lib -all
+
+read_lib $lib_sram_16k_tt_ctypical_0p90v_25c 
+write_lib -output $db_sram_16k_tt_ctypical_0p90v_25c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_25c
+close_lib -all
+
+read_lib $lib_sram_16k_tt_ctypical_0p90v_85c 
+write_lib -output $db_sram_16k_tt_ctypical_0p90v_85c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_85c
+close_lib -all
+
+read_lib $lib_sram_16k_tt_ctypical_0p90v_125c 
+write_lib -output $db_sram_16k_tt_ctypical_0p90v_125c -format db SRAM_16K_tt_ctypical_0p90v_0p90v_125c
+close_lib -all
+
+create_fusion_lib -dbs [list \
+    $db_sram_16k_ffg_cbestt_0p99v_0c \
+    $db_sram_16k_ffg_cbestt_0p99v_125c \
+    $db_sram_16k_ffg_cbestt_0p99v_m40c \
+    $db_sram_16k_ffg_ctypical_0p90v_85c \
+    $db_sram_16k_ffg_ctypical_0p99v_125c \
+    $db_sram_16k_ssg_cworstt_0p81v_m40c \
+    $db_sram_16k_ssg_cworstt_0p81v_0c \
+    $db_sram_16k_ssg_cworstt_0p81v_125c \
+    $db_sram_16k_tt_ctypical_0p81v_0c \
+    $db_sram_16k_tt_ctypical_0p90v_25c \
+    $db_sram_16k_tt_ctypical_0p90v_85c \
+    $db_sram_16k_tt_ctypical_0p90v_125c ] \
+     -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
 save_fusion_lib sram_16k
 close_fusion_lib sram_16k
 
-# 32K SRAM
-read_lib $sram_32k_lib_file_ss_0p81v_125c 
-write_lib -output $sram_32k_db_file_ss_0p81v_125c -format db SRAM_32K_ssg_cworstt_0p81v_0p81v_125c
+
+# Boot ROM
+read_lib $lib_rom_ffg_cbestt_0p99v_0c 
+write_lib -output $db_rom_ffg_cbestt_0p99v_0c -format db rom_via_ffg_cbestt_0p99v_0p99v_0c
 close_lib -all
 
-read_lib $sram_32k_lib_file_tt_0p90v_25c 
-write_lib -output $sram_32k_db_file_tt_0p90v_25c -format db SRAM_32K_tt_ctypical_0p90v_0p90v_25c
+read_lib $lib_rom_ffg_cbestt_0p99v_125c 
+write_lib -output $db_rom_ffg_cbestt_0p99v_125c -format db rom_via_ffg_cbestt_0p99v_0p99v_125c
 close_lib -all
 
-read_lib $sram_32k_lib_file_ff_0p99v_m40c 
-write_lib -output $sram_32k_db_file_ff_0p99v_m40c -format db SRAM_32K_ffg_cbestt_0p99v_0p99v_m40c
+read_lib $lib_rom_ffg_cbestt_0p99v_m40c 
+write_lib -output $db_rom_ffg_cbestt_0p99v_m40c -format db rom_via_ffg_cbestt_0p99v_0p99v_m40c
 close_lib -all
 
-create_fusion_lib -dbs [list $sram_32k_db_file_ss_0p81v_125c $sram_32k_db_file_tt_0p90v_25c $sram_32k_db_file_ff_0p99v_m40c] -lefs $sram_32k_lef_file -technology $cln28ht_tech_file sram_32k
-save_fusion_lib sram_32k
-close_fusion_lib sram_32k
+read_lib $lib_rom_ffg_ctypical_0p90v_85c 
+write_lib -output $db_rom_ffg_ctypical_0p90v_85c -format db rom_via_ffg_ctypical_0p90v_0p90v_85c
+close_lib -all
 
-# 64K SRAM
-read_lib $sram_64k_lib_file_ss_0p81v_125c 
-write_lib -output $sram_64k_db_file_ss_0p81v_125c -format db SRAM_64K_ssg_cworstt_0p81v_0p81v_125c
+read_lib $lib_rom_ffg_ctypical_0p99v_125c 
+write_lib -output $db_rom_ffg_ctypical_0p99v_125c -format db rom_via_ffg_ctypical_0p99v_0p99v_125c
 close_lib -all
 
-read_lib $sram_64k_lib_file_tt_0p90v_25c 
-write_lib -output $sram_64k_db_file_tt_0p90v_25c -format db SRAM_64K_tt_ctypical_0p90v_0p90v_25c
+read_lib $lib_rom_ssg_cworstt_0p81v_m40c 
+write_lib -output $db_rom_ssg_cworstt_0p81v_m40c -format db rom_via_ssg_cworstt_0p81v_0p81v_m40c
 close_lib -all
 
-read_lib $sram_64k_lib_file_ff_0p99v_m40c 
-write_lib -output $sram_64k_db_file_ff_0p99v_m40c -format db SRAM_64K_ffg_cbestt_0p99v_0p99v_m40c
+read_lib $lib_rom_ssg_cworstt_0p81v_0c 
+write_lib -output $db_rom_ssg_cworstt_0p81v_0c -format db rom_via_ssg_cworstt_0p81v_0p81v_0c
 close_lib -all
 
-create_fusion_lib -dbs [list $sram_64k_db_file_ss_0p81v_125c $sram_64k_db_file_tt_0p90v_25c $sram_64k_db_file_ff_0p99v_m40c] -lefs $sram_64k_lef_file -technology $cln28ht_tech_file sram_64k
-save_fusion_lib sram_64k
-close_fusion_lib sram_64k
+read_lib $lib_rom_ssg_cworstt_0p81v_125c 
+write_lib -output $db_rom_ssg_cworstt_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
 
-# Boot ROM
-read_lib $rom_via_lib_file_ss_0p81v_125c 
-write_lib -output $rom_via_db_file_ss_0p81v_125c -format db rom_via_ssg_cworstt_0p81v_0p81v_125c
+read_lib $lib_rom_tt_ctypical_0p81v_0c 
+write_lib -output $db_rom_tt_ctypical_0p81v_0c -format db rom_via_tt_ctypical_0p81v_0p81v_0c
+close_lib -all
+
+read_lib $lib_rom_tt_ctypical_0p90v_25c 
+write_lib -output $db_rom_tt_ctypical_0p90v_25c -format db rom_via_tt_ctypical_0p90v_0p90v_25c
 close_lib -all
 
-read_lib $rom_via_lib_file_tt_0p90v_25c 
-write_lib -output $rom_via_db_file_tt_0p90v_25c -format db rom_via_tt_ctypical_0p90v_0p90v_25c
+read_lib $lib_rom_tt_ctypical_0p90v_85c 
+write_lib -output $db_rom_tt_ctypical_0p90v_85c -format db rom_via_tt_ctypical_0p90v_0p90v_85c
 close_lib -all
 
-read_lib $rom_via_lib_file_ff_0p99v_m40c 
-write_lib -output $rom_via_db_file_ff_0p99v_m40c -format db rom_via_ffg_cbestt_0p99v_0p99v_m40c
+read_lib $lib_rom_tt_ctypical_0p90v_125c 
+write_lib -output $db_rom_tt_ctypical_0p90v_125c -format db rom_via_tt_ctypical_0p90v_0p90v_125c
 close_lib -all
 
-create_fusion_lib -dbs [list $rom_via_db_file_ss_0p81v_125c $rom_via_db_file_tt_0p90v_25c $rom_via_db_file_ff_0p99v_m40c] -lefs $rom_via_lef_file -technology $cln28ht_tech_file rom_via
+create_fusion_lib -dbs [list \
+    $db_rom_ffg_cbestt_0p99v_0c \
+    $db_rom_ffg_cbestt_0p99v_125c \
+    $db_rom_ffg_cbestt_0p99v_m40c \
+    $db_rom_ffg_ctypical_0p90v_85c \
+    $db_rom_ffg_ctypical_0p99v_125c \
+    $db_rom_ssg_cworstt_0p81v_m40c \
+    $db_rom_ssg_cworstt_0p81v_0c \
+    $db_rom_ssg_cworstt_0p81v_125c \
+    $db_rom_tt_ctypical_0p81v_0c \
+    $db_rom_tt_ctypical_0p90v_25c \
+    $db_rom_tt_ctypical_0p90v_85c \
+    $db_rom_tt_ctypical_0p90v_125c ] \
+     -lefs $rom_via_lef_file -technology $cln28ht_tech_file rom_via
 save_fusion_lib rom_via
 close_fusion_lib rom_via
 
@@ -256,7 +459,4 @@ create_fusion_lib -lefs $pad_lef_file -technology $cln28ht_tech_file pad_lib
 save_fusion_lib pad_lib
 close_fusion_lib pad_lib
 
-create_fusion_lib -lefs $bump_lef_file -technology $cln28ht_tech_file bump_lib
-save_fusion_lib bump_lib
-close_fusion_lib bump_lib
 exit
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/constraints.sdc b/ASIC/TSMC28nm/constraints.sdc
index 024c31d325ac47a1df9732abb51f387806af9eb9..4f3e58217bee80d8b9f168dd64ae9878d0725650 100644
--- a/ASIC/TSMC28nm/constraints.sdc
+++ b/ASIC/TSMC28nm/constraints.sdc
@@ -16,13 +16,16 @@ set SWDCLK "swdclk";
 set_units -time ns;
 
 set_units -capacitance pF;
-set EXTCLK_PERIOD 4.16667;
+set EXTCLK_PERIOD 4.16667; #240MHz Frequency
 set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
 set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
 set INTER_CLOCK_UNCERTAINTY 0.1
 
 create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
+set_clock_transition [expr $clock_max_transition_factor * $EXTCLK_PERIOD] [get_clocks $EXTCLK]
+
 create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
+set_clock_transition [expr $clock_max_transition_factor * $SWDCLK_PERIOD] [get_clocks $SWDCLK]
 
 set_clock_uncertainty $CLK_ERROR [get_clocks $EXTCLK]
 set_clock_uncertainty $CLK_ERROR [get_clocks $SWDCLK]
@@ -67,5 +70,7 @@ set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P0]
 set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P1]
 set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.1 [get_ports SWDIO]
 
+set_max_transition [expr $max_transition_factor * $EXTCLK_PERIOD] nanosoc_chip_pads
+
 set_max_capacitance 3 [all_outputs]
 set_max_fanout 10 [all_inputs]
diff --git a/ASIC/TSMC28nm/constraints_hold.sdc b/ASIC/TSMC28nm/constraints_hold.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..bda1f919fcd97e44a4c68149968b0c05380b97f1
--- /dev/null
+++ b/ASIC/TSMC28nm/constraints_hold.sdc
@@ -0,0 +1,15 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Constraints for Synthesis 
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set max_transition_factor           0.2;
+set clock_max_transition_factor     0.2;
+
+source ../../../constraints.sdc
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/constraints_setup.sdc b/ASIC/TSMC28nm/constraints_setup.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..7ac5319ad71233f022d8deed541ce5bf0a465efe
--- /dev/null
+++ b/ASIC/TSMC28nm/constraints_setup.sdc
@@ -0,0 +1,15 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Constraints for Synthesis 
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set max_transition_factor           0.303;
+set clock_max_transition_factor     0.303;
+
+source ../../../constraints.sdc
\ No newline at end of file
diff --git a/ASIC/TSMC28nm/sram_16k.spec b/ASIC/TSMC28nm/sram_16k.spec
index 2480f23b63d90c0b1548a1f5da5bd66fb1945328..ecd06aca1016b07792fda1c0bfe1bb97fc719ddf 100644
--- a/ASIC/TSMC28nm/sram_16k.spec
+++ b/ASIC/TSMC28nm/sram_16k.spec
@@ -1,4 +1,4 @@
-# user spec file, compiler sram_sp_hde_hvt_mvt, version r0p0
+# user spec file, compiler sram_sp_hde_2_svt_mvt, version r0p0
 
 EOL_guardband = 0
 activity_factor = 10
@@ -9,7 +9,7 @@ bmux = off
 bus_notation = on
 check_instname = on
 compiler_type = sp
-corners = ffg_cbestt_0p99v_0p99v_125c,ffg_cbestt_0p99v_0p99v_m40c,ssg_cworstt_0p81v_0p81v_125c,ssg_cworstt_0p81v_0p81v_m40c,tt_ctypical_0p90v_0p90v_85c
+corners = ffg_cbestt_0p99v_0p99v_0c,ffg_cbestt_0p99v_0p99v_125c,ffg_cbestt_0p99v_0p99v_m40c,ffg_ctypical_0p90v_0p90v_85c,ffg_ctypical_0p99v_0p99v_125c,ssg_cworstt_0p81v_0p81v_0c,ssg_cworstt_0p81v_0p81v_125c,ssg_cworstt_0p81v_0p81v_m40c,tt_ctypical_0p81v_0p81v_0c,tt_ctypical_0p90v_0p90v_125c,tt_ctypical_0p90v_0p90v_25c,tt_ctypical_0p90v_0p90v_85c
 cust_comment = 
 diodes = on
 drive = 6
diff --git a/ASIC/TSMC65nm/44pin/Synopsys_FC/makefile b/ASIC/TSMC65nm/44pin/Synopsys_FC/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b3a66182212a7a8b3e32e2492a6556211ecc4711
--- /dev/null
+++ b/ASIC/TSMC65nm/44pin/Synopsys_FC/makefile
@@ -0,0 +1,10 @@
+LIB_DIR	:= ./libs
+WORK_DIR := ./work
+REPORTS_DIR :=  $(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports
+LOG_DIR := $(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/logs
+
+
+gen_fusion_libs:
+	@mkdir -p $(LIB_DIR)
+	@(cd $(LIB_DIR); \
+	lc_shell;)
diff --git a/ASIC/TSMC65nm/44pin/Synopsys_FC/scripts/synopsys_library_setup.tcl b/ASIC/TSMC65nm/44pin/Synopsys_FC/scripts/synopsys_library_setup.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a312e7eb6c183d547fef5fec1955a26de2699981
--- /dev/null
+++ b/ASIC/TSMC65nm/44pin/Synopsys_FC/scripts/synopsys_library_setup.tcl
@@ -0,0 +1,98 @@
+## Paths Please Edit for your system
+set cln65lp_tech_path           /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/stclib/12-track/tcbn65lpbwp12t-set/tcbn65lpbwp12t_200b_FE/TSMCHOME/digital/Back_End
+set standard_cell_base_path     /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_rvt/r0p0
+set io_base_path                /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital
+set pmk_base_path               /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/sc9mcpp96c_pmk_svt_c24/r2p0
+set ret_base_path               /research/AAA/phys_ip_library/arm/tsmc/cln16fcll001/sc9mcpp96c_rklo_lvt_svt_c20_c24/r1p0
+
+# Technology files
+set cln65lp_tech_file       $cln65lp_tech_path/milkyway/tcbn65lpbwp12t_200a/techfiles/tsmcn65_9lmT2.tf
+set cln65lp_lef_file        $cln65lp_tech_path/lef/tcbn65lpbwp12t_140b/lef/tcbn65lpbwp12t_9lmT2.lef
+
+# Standard Cell libraries
+set standard_cell_lef_file                  $standard_cell_base_path/lef/sc12_cln65lp_base_rvt.lef
+set standard_cell_gds_file                  $standard_cell_base_path/gds2/sc12_cln65lp_base_rvt.gds2
+set standard_cell_db_file_ss_0p72v_125C     $standard_cell_base_path/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
+set standard_cell_db_file_tt_0p80v_25C      $standard_cell_base_path/db/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db
+set standard_cell_db_file_ff_0p88v_m40C     $standard_cell_base_path/db/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.db
+set standard_cell_antenna_file              $standard_cell_base_path/milkyway/9m_2xa1xd3xe2z_utrdl/sc9mcpp96c_cln16fcll001_base_svt_c24_antenna.clf
+
+# Arm IO Library
+set io_lef_file                         $io_base_path/Back_End/lef/tpdn65lpnv2od3_140b/mt_2/9lm/lef/tpdn65lpnv2od3_9lm.lef
+set io_gds_file                         $io_base_path/gds2/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_9m_2xa1xd3xe2z_fc.gds2
+set io_db_file_ss_0p72v_125C            $io_base_path/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/tpdn65lpnv2od3wc.db
+set io_db_file_tt_0p80v_25C             $io_base_path/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/tpdn65lpnv2od3tc.db
+set io_db_file_ff_0p88v_m40C            $io_base_path/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/tpdn65lpnv2od3bc.db
+set io_antenna_file                     $io_base_path/milkyway/9m_2xa1xd3xe2z_fc/io_gppr_cln16fcll001_t18_mv08_fs18_rvt_dr_antenna.clf
+
+# 32K SRAM PATHS
+set SRAM_32K_PATH            $env(SOCLABS_PROJECT_DIR)/memories/sram_32k
+set SRAM_32K_lef_file        $SRAM_32K_PATH/sram_32k.lef
+set SRAM_32K_gds_file        $SRAM_32K_PATH/sram_32k.gds2
+set SRAM_32K_lib_file_ss     $SRAM_32K_PATH/sram_32k_ssgnp_0p72v_0p72v_125c.lib
+set SRAM_32K_lib_file_tt     $SRAM_32K_PATH/sram_32k_tt_0p80v_0p80v_25c.lib
+set SRAM_32K_lib_file_ff     $SRAM_32K_PATH/sram_32k_ffgnp_0p88v_0p88v_m40c.lib
+set SRAM_32K_db_file_ss      $SRAM_32K_PATH/sram_32k_ssgnp_0p72v_0p72v_125c.db
+set SRAM_32K_db_file_tt      $SRAM_32K_PATH/sram_32k_tt_0p80v_0p80v_25c.db
+set SRAM_32K_db_file_ff      $SRAM_32K_PATH/sram_32k_ffgnp_0p88v_0p88v_m40c.db
+
+# ROM PATHS
+set ROM_VIA_PATH            $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+set ROM_VIA_lef_file        $ROM_VIA_PATH/rom_via.lef
+set ROM_VIA_gds_file        $ROM_VIA_PATH/rom_via.gds2
+set ROM_VIA_lib_file_ss     $ROM_VIA_PATH/rom_via_ssgnp_0p72v_0p72v_125c.lib
+set ROM_VIA_lib_file_tt     $ROM_VIA_PATH/rom_via_tt_0p80v_0p80v_25c.lib
+set ROM_VIA_lib_file_ff     $ROM_VIA_PATH/rom_via_ffgnp_0p88v_0p88v_m40c.lib
+set ROM_VIA_db_file_ss      $ROM_VIA_PATH/rom_via_ssgnp_0p72v_0p72v_125c.db
+set ROM_VIA_db_file_tt      $ROM_VIA_PATH/rom_via_tt_0p80v_0p80v_25c.db
+set ROM_VIA_db_file_ff      $ROM_VIA_PATH/rom_via_ffgnp_0p88v_0p88v_m40c.db
+
+# 32K SRAMs
+read_lib $SRAM_32K_lib_file_ss
+write_lib -output $SRAM_32K_db_file_ss -format db sram_32k_ssgnp_0p72v_0p72v_125c
+close_lib -all
+
+read_lib $SRAM_32K_lib_file_tt 
+write_lib -output $SRAM_32K_db_file_tt -format db sram_32k_tt_0p80v_0p80v_25c
+close_lib -all
+
+read_lib $SRAM_32K_lib_file_ff 
+write_lib -output $SRAM_32K_db_file_ff -format db sram_32k_ffgnp_0p88v_0p88v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $SRAM_32K_db_file_ss $SRAM_32K_db_file_tt $SRAM_32K_db_file_ff] -lefs $SRAM_32K_lef_file -technology $cln16fcll_tech_file SRAM_32K
+save_fusion_lib SRAM_32K
+close_fusion_lib SRAM_32K
+
+# ROM VIA 
+read_lib $ROM_VIA_lib_file_ss
+write_lib -output $ROM_VIA_db_file_ss -format db rom_via_ssgnp_0p72v_0p72v_125c
+close_lib -all
+
+read_lib $ROM_VIA_lib_file_tt 
+write_lib -output $ROM_VIA_db_file_tt -format db rom_via_tt_0p80v_0p80v_25c
+close_lib -all
+
+read_lib $ROM_VIA_lib_file_ff 
+write_lib -output $ROM_VIA_db_file_ff -format db rom_via_ffgnp_0p88v_0p88v_m40c
+close_lib -all
+
+create_fusion_lib -dbs [list $ROM_VIA_db_file_ss $ROM_VIA_db_file_tt $ROM_VIA_db_file_ff] -lefs $ROM_VIA_lef_file -technology $cln16fcll_tech_file ROM_VIA
+save_fusion_lib ROM_VIA
+close_fusion_lib ROM_VIA
+
+
+
+# Create standard cell fusion library
+create_fusion_lib -dbs [list $standard_cell_db_file_ss_0p72v_125C $standard_cell_db_file_tt_0p80v_25C $standard_cell_db_file_ff_0p88v_m40C]  -lefs [list $cln65lp_lef_file $standard_cell_lef_file] -technology $cln65lp_tech_file cln65lp
+save_fusion_lib cln65lp
+close_fusion_lib cln65lp
+
+# Create Arm IO Library 
+create_fusion_lib -dbs [list $io_db_file_ss_0p72v_125C $io_db_file_tt_0p80v_25C $io_db_file_ff_0p88v_m40C]  -lefs $io_lef_file -technology $cln65lp_tech_file io_lib
+
+save_fusion_lib io_lib
+close_fusion_lib io_lib
+
+
+exit
\ No newline at end of file