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SoCLabs
NanoSoC Tech
Commits
9959a7d1
Commit
9959a7d1
authored
1 year ago
by
dam1n19
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Initial system-level wiring
parent
22c4d4d4
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1 merge request
!1
changed imem to rom to allow initial program loading, updated bootloader code...
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system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+5
-4
5 additions, 4 deletions
...soc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
system/nanosoc_system/verilog/nanosoc_system.v
+1091
-0
1091 additions, 0 deletions
system/nanosoc_system/verilog/nanosoc_system.v
with
1096 additions
and
4 deletions
system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+
5
−
4
View file @
9959a7d1
...
@@ -21,6 +21,7 @@ module nanosoc_ss_systemctrl #(
...
@@ -21,6 +21,7 @@ module nanosoc_ss_systemctrl #(
parameter
CLKGATE_PRESENT
=
0
parameter
CLKGATE_PRESENT
=
0
)(
)(
// Free-running and Crystal Clock Output
// Free-running and Crystal Clock Output
input
wire
SYS_CLK
,
// System Input Clock
output
wire
SYS_FCLK
,
// Free-running system clock
output
wire
SYS_FCLK
,
// Free-running system clock
output
wire
SYS_XTALCLK_OUT
,
// Crystal Clock Output
output
wire
SYS_XTALCLK_OUT
,
// Crystal Clock Output
...
@@ -96,7 +97,7 @@ module nanosoc_ss_systemctrl #(
...
@@ -96,7 +97,7 @@ module nanosoc_ss_systemctrl #(
// CPU power/reset control
// CPU power/reset control
output
wire
SYS_REMAP_CTRL
,
// REMAP control bit
output
wire
SYS_REMAP_CTRL
,
// REMAP control bit
output
wire
SYS_WDOGRESETREQ
,
// Watchdog reset request
output
wire
SYS_WDOGRESETREQ
,
// Watchdog reset request
output
wire
CPU_0
_LOCKUPRESET
,
// System Controller cfg - reset if lockup
output
wire
SYS
_LOCKUPRESET
,
// System Controller cfg - reset if lockup
// System Reset Request Signals
// System Reset Request Signals
output
wire
SYS_SYSRESETREQ
,
// System Request from System Managers
output
wire
SYS_SYSRESETREQ
,
// System Request from System Managers
...
@@ -152,7 +153,7 @@ module nanosoc_ss_systemctrl #(
...
@@ -152,7 +153,7 @@ module nanosoc_ss_systemctrl #(
.
SLEEPING
(
CPU_0_SLEEPING
),
.
SLEEPING
(
CPU_0_SLEEPING
),
.
SLEEPDEEP
(
CPU_0_SLEEPDEEP
),
.
SLEEPDEEP
(
CPU_0_SLEEPDEEP
),
.
LOCKUP
(
CPU_0_LOCKUP
),
.
LOCKUP
(
CPU_0_LOCKUP
),
.
LOCKUPRESET
(
CPU_0
_LOCKUPRESET
),
.
LOCKUPRESET
(
SYS
_LOCKUPRESET
),
.
SYSRESETREQ
(
SYS_PRMURESETREQ
),
.
SYSRESETREQ
(
SYS_PRMURESETREQ
),
.
DBGRESETREQ
(
SYS_PMUDBGRESETREQ
),
.
DBGRESETREQ
(
SYS_PMUDBGRESETREQ
),
.
CGBYPASS
(
SYS_TESTMODE
),
.
CGBYPASS
(
SYS_TESTMODE
),
...
@@ -271,7 +272,7 @@ module nanosoc_ss_systemctrl #(
...
@@ -271,7 +272,7 @@ module nanosoc_ss_systemctrl #(
.
exp12_prdata
(
DMAC_1_PRDATA
),
.
exp12_prdata
(
DMAC_1_PRDATA
),
.
exp12_pready
(
DMAC_1_PREADY
),
.
exp12_pready
(
DMAC_1_PREADY
),
.
exp12_pslverr
(
DMAC_1_PSLVERR
),
.
exp12_pslverr
(
DMAC_1_PSLVERR
),
.
exp13_prdata
(
{
APB_
ADDR
_W
{
1'b0
}}
),
.
exp13_prdata
(
{
APB_
DATA
_W
{
1'b0
}}
),
.
exp13_pready
(
1'b1
),
.
exp13_pready
(
1'b1
),
.
exp13_pslverr
(
1'b1
),
.
exp13_pslverr
(
1'b1
),
.
exp14_prdata
(
USRT_PRDATA
),
.
exp14_prdata
(
USRT_PRDATA
),
...
@@ -293,7 +294,7 @@ module nanosoc_ss_systemctrl #(
...
@@ -293,7 +294,7 @@ module nanosoc_ss_systemctrl #(
.
SYSRESETREQ
(
SYS_SYSRESETREQ
),
.
SYSRESETREQ
(
SYS_SYSRESETREQ
),
.
WDOGRESETREQ
(
SYS_WDOGRESETREQ
),
.
WDOGRESETREQ
(
SYS_WDOGRESETREQ
),
.
LOCKUP
(
CPU_0_LOCKUP
),
.
LOCKUP
(
CPU_0_LOCKUP
),
.
LOCKUPRESET
(
CPU_0
_LOCKUPRESET
),
.
LOCKUPRESET
(
SYS
_LOCKUPRESET
),
.
PMUENABLE
(
SYS_PMUENABLE
),
.
PMUENABLE
(
SYS_PMUENABLE
),
// IO signaling
// IO signaling
...
...
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system/nanosoc_system/verilog/nanosoc_system.v
+
1091
−
0
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9959a7d1
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