nanosoc_system.v

//-----------------------------------------------------------------------------
// NanoSoC System Integration Level
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------

module nanosoc_system #(
    // System Parameters
    parameter    SYS_ADDR_W           = 32,  // System Address Width
    parameter    SYS_DATA_W           = 32,  // System Data Width
    
    // Widths of System Peripheral APB Subsystem
    parameter    APB_ADDR_W           = 12,  // APB Peripheral Address Width
    parameter    APB_DATA_W           = 32,  // APB Peripheral Data Width
    
    // Bootrom 0 Parameters
    parameter    BOOTROM_ADDR_W       = 10,          // Size of Bootrom (Based on Address Width) - Default 1KB
    
    // IMEM 0 Parameters
    parameter    IMEM_RAM_ADDR_W      = 14,          // Width of IMEM RAM Address - Default 16KB
    parameter    IMEM_RAM_DATA_W      = 32,          // Width of IMEM RAM Data Bus - Default 32 bits
    parameter    IMEM_RAM_FPGA_IMG    = "image.hex", // Image to Preload into SRAM
    
    // DMEM 0 Parameters
    parameter    DMEM_RAM_ADDR_W      = 14,          // Width of IMEM RAM Address - Default 16KB
    parameter    DMEM_RAM_DATA_W      = 32,          // Width of IMEM RAM Data Bus - Default 32 bits
    
    // Expansion SRAM Low Parameters
    parameter    EXPRAM_L_RAM_ADDR_W  = 14,          // Width of IMEM RAM Address - Default 16KB
    parameter    EXPRAM_L_RAM_DATA_W  = 32,          // Width of IMEM RAM Data Bus - Default 32 bits
    
    // Expansion SRAM High Parameters
    parameter    EXPRAM_H_RAM_ADDR_W  = 14,          // Width of IMEM RAM Address - Default 16KB
    parameter    EXPRAM_H_RAM_DATA_W  = 32,          // Width of IMEM RAM Data Bus - Default 32 bits
    
    // CPU Parameters
    parameter CLKGATE_PRESENT         = 0,
    parameter BE                      = 0,   // 1: Big endian 0: little endian
    parameter BKPT                    = 4,   // Number of breakpoint comparators
    parameter DBG                     = 1,   // Debug configuration
    parameter NUMIRQ                  = 32,  // NUM of IRQ
    parameter SMUL                    = 0,   // Multiplier configuration
    parameter SYST                    = 1,   // SysTick
    parameter WIC                     = 1,   // Wake-up interrupt controller support
    parameter WICLINES                = 34,  // Supported WIC lines
    parameter WPT                     = 2,   // Number of DWT comparators
    parameter RESET_ALL_REGS          = 0,   // Do not reset all registers
    parameter INCLUDE_JTAG            = 0,   // Do not Include JTAG feature
      
    // DMA Parameters  
    parameter    DMAC_0_CHANNEL_NUM   = 2,   // DMAC 0 Number of DMA Channels 
    parameter    DMAC_1_CHANNEL_NUM   = 2,   // DMAC 1 Number of DMA Channels
      
    // SoCDebug Parameters  
    parameter         PROMPT_CHAR     = "]",
    parameter integer FT1248_WIDTH	  = 1, // FTDI Interface 1,2,4 width supported
    parameter integer FT1248_CLKON	  = 1, // FTDI clock always on - else quiet when no access
    
    // Address of System ROM Table
    parameter    SYSTABLE_BASE        = 32'hF000_0000   // Base Address of System ROM Table
) (
    // Free-running and Crystal Clock Output
    input  wire                     SYS_CLK,              // System Input Clock
    output wire                     SYS_XTALCLK_OUT,      // Crystal Clock Output