Used new FPGA SRAM wrapper and passed ROM Table address to top of subsystem

.gitmodules

...nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v

...osoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v

...em/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v

...anosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v

...anosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v

...em/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v

system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v

system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v

...soc_regions/systable/verilog/nanosoc_coresight_systable.v

...anosoc_regions/systable/verilog/nanosoc_region_systable.v

system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v

system/slcore_m0_tech

system/slcorem0_tech