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Commit 22c4d4d4 authored by dam1n19's avatar dam1n19
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Used new FPGA SRAM wrapper and passed ROM Table address to top of subsystem

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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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.gitmodules
+ 3
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View file @ 22c4d4d4
[submodule "system/socdebug_tech"] [submodule "system/socdebug_tech"]
path = system/socdebug_tech path = system/socdebug_tech
url = https://git.soton.ac.uk/soclabs/socdebug_tech.git url = https://git.soton.ac.uk/soclabs/socdebug_tech.git
[submodule "system/slcore_m0_tech"]
path = system/slcore_m0_tech
url = https://git.soton.ac.uk/soclabs/slcore_m0_tech.git
[submodule "system/sldma230_tech"] [submodule "system/sldma230_tech"]
path = system/sldma230_tech path = system/sldma230_tech
url = https://git.soton.ac.uk/soclabs/sldma230_tech.git url = https://git.soton.ac.uk/soclabs/sldma230_tech.git
[submodule "system/slcorem0_tech"]
path = system/slcorem0_tech
url = https://git.soton.ac.uk/soclabs/slcorem0_tech.git
system/nanosoc_regions/bootrom_0/verilog/nanosoc_ahb_bootrom.v → system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
+ 2
− 2
View file @ 22c4d4d4
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// NanoSoC AHB to Bootrom Interface // NanoSoC CPU 0 Bootrom
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org) // Copyright � 2021-3, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module nanosoc_ahb_bootrom #( module nanosoc_bootrom_cpu_0 #(
parameter AW = 10 // Address width parameter AW = 10 // Address width
)( )(
input wire HCLK, // Clock input wire HCLK, // Clock
......
system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
+ 2
− 2
View file @ 22c4d4d4
...@@ -34,9 +34,9 @@ module nanosoc_region_bootrom_0 #( ...@@ -34,9 +34,9 @@ module nanosoc_region_bootrom_0 #(
output wire [SYS_DATA_W-1:0] HRDATA output wire [SYS_DATA_W-1:0] HRDATA
); );
nanosoc_ahb_bootrom #( nanosoc_bootrom_cpu_0 #(
.AW (BOOTROM_ADDR_W) .AW (BOOTROM_ADDR_W)
) u_ahb_bootloader ( ) u_bootrom_cpu_0 (
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
.HSEL (HSEL), .HSEL (HSEL),
......
system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
+ 6
− 35
View file @ 22c4d4d4
...@@ -34,16 +34,10 @@ module nanosoc_region_dmem_0 #( ...@@ -34,16 +34,10 @@ module nanosoc_region_dmem_0 #(
output wire [SYS_DATA_W-1:0] HRDATA output wire [SYS_DATA_W-1:0] HRDATA
); );
wire [DMEM_RAM_ADDR_W-3:0] addr; // SRAM Instantiation
wire [DMEM_RAM_DATA_W-1:0] wdata; sl_ahb_sram #(
wire [DMEM_RAM_DATA_W-1:0] rdata; .RAM_ADDR_W (DMEM_RAM_ADDR_W)
wire [3:0] wen; ) u_dmem_0 (
wire cs;
// AHB to SRAM bridge
cmsdk_ahb_to_sram #(
.AW (DMEM_RAM_ADDR_W)
) u_ahb_to_sdmem (
// AHB Inputs // AHB Inputs
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
...@@ -58,30 +52,7 @@ module nanosoc_region_dmem_0 #( ...@@ -58,30 +52,7 @@ module nanosoc_region_dmem_0 #(
// AHB Outputs // AHB Outputs
.HREADYOUT (HREADYOUT), .HREADYOUT (HREADYOUT),
.HRDATA (HRDATA), .HRDATA (HRDATA),
.HRESP (HRESP), .HRESP (HRESP)
// SRAM input
.SRAMRDATA (rdata),
// SRAM Outputs
.SRAMADDR (addr),
.SRAMWDATA (wdata),
.SRAMWEN (wen),
.SRAMCS (cs)
); );
// SRAM model
cmsdk_fpga_sram #(
.AW (DMEM_RAM_ADDR_W)
) u_dmem_0 (
// SRAM Inputs
.CLK (HCLK),
.ADDR (addr),
.WDATA (wdata),
.WREN (wen),
.CS (cs),
// SRAM Output
.RDATA (rdata)
);
endmodule endmodule
\ No newline at end of file
system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
+ 5
− 35
View file @ 22c4d4d4
...@@ -35,16 +35,10 @@ module nanosoc_region_expram_h #( ...@@ -35,16 +35,10 @@ module nanosoc_region_expram_h #(
output wire [SYS_DATA_W-1:0] HRDATA output wire [SYS_DATA_W-1:0] HRDATA
); );
wire [EXPRAM_H_RAM_ADDR_W-3:0] addr;
wire [EXPRAM_H_RAM_DATA_W-1:0] wdata;
wire [EXPRAM_H_RAM_DATA_W-1:0] rdata;
wire [3:0] wen;
wire cs;
// AHB to SRAM bridge // AHB to SRAM bridge
cmsdk_ahb_to_sram #( sl_ahb_sram #(
.AW (EXPRAM_H_RAM_ADDR_W) .RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W)
) u_ahb_to_sram8 ( ) u_expram_h (
// AHB Inputs // AHB Inputs
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
...@@ -59,31 +53,7 @@ module nanosoc_region_expram_h #( ...@@ -59,31 +53,7 @@ module nanosoc_region_expram_h #(
// AHB Outputs // AHB Outputs
.HREADYOUT (HREADYOUT), .HREADYOUT (HREADYOUT),
.HRDATA (HRDATA), .HRDATA (HRDATA),
.HRESP (HRESP), .HRESP (HRESP)
// SRAM input
.SRAMRDATA (rdata),
// SRAM Outputs
.SRAMADDR (addr),
.SRAMWDATA (wdata),
.SRAMWEN (wen),
.SRAMCS (cs)
);
// SRAM model
cmsdk_fpga_sram #(
.AW (EXPRAM_H_RAM_ADDR_W)
) u_expram_h (
// SRAM Inputs
.CLK (HCLK),
.ADDR (addr),
.WDATA (wdata),
.WREN (wen),
.CS (cs),
// SRAM Output
.RDATA (rdata)
); );
endmodule endmodule
\ No newline at end of file
system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
+ 5
− 35
View file @ 22c4d4d4
...@@ -35,16 +35,10 @@ module nanosoc_region_expram_l #( ...@@ -35,16 +35,10 @@ module nanosoc_region_expram_l #(
output wire [SYS_DATA_W-1:0] HRDATA output wire [SYS_DATA_W-1:0] HRDATA
); );
wire [EXPRAM_L_RAM_ADDR_W-3:0] addr; // SRAM Instantiation
wire [EXPRAM_L_RAM_DATA_W-1:0] wdata; sl_ahb_sram #(
wire [EXPRAM_L_RAM_DATA_W-1:0] rdata; .RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W)
wire [3:0] wen; ) u_expram_l (
wire cs;
// AHB to SRAM bridge
cmsdk_ahb_to_sram #(
.AW (EXPRAM_L_RAM_ADDR_W)
) u_ahb_to_sram8 (
// AHB Inputs // AHB Inputs
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
...@@ -59,31 +53,7 @@ module nanosoc_region_expram_l #( ...@@ -59,31 +53,7 @@ module nanosoc_region_expram_l #(
// AHB Outputs // AHB Outputs
.HREADYOUT (HREADYOUT), .HREADYOUT (HREADYOUT),
.HRDATA (HRDATA), .HRDATA (HRDATA),
.HRESP (HRESP), .HRESP (HRESP)
// SRAM input
.SRAMRDATA (rdata),
// SRAM Outputs
.SRAMADDR (addr),
.SRAMWDATA (wdata),
.SRAMWEN (wen),
.SRAMCS (cs)
);
// SRAM model
cmsdk_fpga_sram #(
.AW (EXPRAM_L_RAM_ADDR_W)
) u_expram_l (
// SRAM Inputs
.CLK (HCLK),
.ADDR (addr),
.WDATA (wdata),
.WREN (wen),
.CS (cs),
// SRAM Output
.RDATA (rdata)
); );
endmodule endmodule
\ No newline at end of file
system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+ 6
− 36
View file @ 22c4d4d4
...@@ -36,16 +36,11 @@ module nanosoc_region_imem_0 #( ...@@ -36,16 +36,11 @@ module nanosoc_region_imem_0 #(
output wire [SYS_DATA_W-1:0] HRDATA output wire [SYS_DATA_W-1:0] HRDATA
); );
wire [IMEM_RAM_ADDR_W-3:0] addr; // SRAM Instantiation
wire [IMEM_RAM_DATA_W-1:0] wdata; sl_ahb_sram #(
wire [IMEM_RAM_DATA_W-1:0] rdata; .RAM_ADDR_W (IMEM_RAM_ADDR_W),
wire [3:0] wen; .FILENAME (IMEM_RAM_FPGA_IMG)
wire cs; ) u_imem_0 (
// AHB to SRAM bridge
cmsdk_ahb_to_sram #(
.AW (IMEM_RAM_ADDR_W)
) u_ahb_to_simem (
// AHB Inputs // AHB Inputs
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
...@@ -60,32 +55,7 @@ module nanosoc_region_imem_0 #( ...@@ -60,32 +55,7 @@ module nanosoc_region_imem_0 #(
// AHB Outputs // AHB Outputs
.HREADYOUT (HREADYOUT), .HREADYOUT (HREADYOUT),
.HRDATA (HRDATA), .HRDATA (HRDATA),
.HRESP (HRESP), .HRESP (HRESP)
// SRAM input
.SRAMRDATA (rdata),
// SRAM Outputs
.SRAMADDR (addr),
.SRAMWDATA (wdata),
.SRAMWEN (wen),
.SRAMCS (cs)
);
// SRAM model
cmsdk_fpga_sram #(
.AW (IMEM_RAM_ADDR_W),
.filename(IMEM_RAM_FPGA_IMG)
) u_imem_0 (
// SRAM Inputs
.CLK (HCLK),
.ADDR (addr),
.WDATA (wdata),
.WREN (wen),
.CS (cs),
// SRAM Output
.RDATA (rdata)
); );
endmodule endmodule
\ No newline at end of file
system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+ 10
− 6
View file @ 22c4d4d4
...@@ -105,9 +105,11 @@ module nanosoc_region_sysio #( ...@@ -105,9 +105,11 @@ module nanosoc_region_sysio #(
output wire [15:0] p1_altfunc // GPIO 1 alternate function (pin mux) output wire [15:0] p1_altfunc // GPIO 1 alternate function (pin mux)
); );
// Sysctrl base address
localparam BASEADDR_APBSS = 32'h4000_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
localparam BASEADDR_SYSCTRL = 32'h4001_f000; // Sysctrl peripheral basse address
localparam BE = 0; localparam BE = 0;
// ------------------------------------------------------------ // ------------------------------------------------------------
...@@ -142,8 +144,10 @@ module nanosoc_region_sysio #( ...@@ -142,8 +144,10 @@ module nanosoc_region_sysio #(
// AHB address decode // AHB address decode
nanosoc_sysio_decode #( nanosoc_sysio_decode #(
.BASEADDR_APBSS (BASEADDR_APBSS),
.BASEADDR_GPIO0 (BASEADDR_GPIO0), .BASEADDR_GPIO0 (BASEADDR_GPIO0),
.BASEADDR_GPIO1 (BASEADDR_GPIO1) .BASEADDR_GPIO1 (BASEADDR_GPIO1),
.BASEADDR_SYSCTRL (BASEADDR_SYSCTRL)
) u_addr_decode ( ) u_addr_decode (
// System Address // System Address
.hsel (HSEL), .hsel (HSEL),
...@@ -161,7 +165,7 @@ module nanosoc_region_sysio #( ...@@ -161,7 +165,7 @@ module nanosoc_region_sysio #(
.PORT1_ENABLE (1), // GPIO Port 0 .PORT1_ENABLE (1), // GPIO Port 0
.PORT2_ENABLE (1), // GPIO Port 1 .PORT2_ENABLE (1), // GPIO Port 1
.PORT3_ENABLE (1), // SYS control .PORT3_ENABLE (1), // SYS control
.PORT4_ENABLE (1), // default .PORT4_ENABLE (1), // Default
.PORT5_ENABLE (0), .PORT5_ENABLE (0),
.PORT6_ENABLE (0), .PORT6_ENABLE (0),
.PORT7_ENABLE (0), .PORT7_ENABLE (0),
...@@ -272,7 +276,7 @@ module nanosoc_region_sysio #( ...@@ -272,7 +276,7 @@ module nanosoc_region_sysio #(
.ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO .ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
.BE (BE) .BE (BE)
) )
u_ahb_gpio_0 ( u_nanosoc_gpio_0 (
// AHB Inputs // AHB Inputs
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
...@@ -305,7 +309,7 @@ module nanosoc_region_sysio #( ...@@ -305,7 +309,7 @@ module nanosoc_region_sysio #(
.ALTERNATE_FUNC_MASK (16'h002A), // pin muxing for Port #1 .ALTERNATE_FUNC_MASK (16'h002A), // pin muxing for Port #1
.ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO .ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
.BE (BE) .BE (BE)
) u_ahb_gpio_1 ( ) u_nanosoc_gpio_1 (
// AHB Inputs // AHB Inputs
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
......
system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+ 5
− 3
View file @ 22c4d4d4
...@@ -40,11 +40,13 @@ ...@@ -40,11 +40,13 @@
module nanosoc_sysio_decode #( module nanosoc_sysio_decode #(
parameter SYS_ADDR_W = 32, parameter SYS_ADDR_W = 32,
// APB Subsystem peripheral base address
parameter BASEADDR_APBSS = 32'h4000_0000,
// GPIO0 peripheral base address // GPIO0 peripheral base address
parameter BASEADDR_GPIO0 = 32'h4001_0000, parameter BASEADDR_GPIO0 = 32'h4001_0000,
// GPIO1 peripheral base address // GPIO1 peripheral base address
parameter BASEADDR_GPIO1 = 32'h4001_1000, parameter BASEADDR_GPIO1 = 32'h4001_1000,
// GPIO1 peripheral base address // Sysctrl base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000 parameter BASEADDR_SYSCTRL = 32'h4001_f000
)( )(
// System Address // System Address
...@@ -66,13 +68,13 @@ module nanosoc_sysio_decode #( ...@@ -66,13 +68,13 @@ module nanosoc_sysio_decode #(
// 0x40010000 - 0x40010FFF : AHB peripherals (GPIO0) // 0x40010000 - 0x40010FFF : AHB peripherals (GPIO0)
// 0x40011000 - 0x40011FFF : AHB peripherals (GPIO1) // 0x40011000 - 0x40011FFF : AHB peripherals (GPIO1)
// 0x4001F000 - 0x4001FFFF : AHB peripherals (SYS control) // 0x4001F000 - 0x4001FFFF : AHB peripherals (SYS control)
// 0xF0000000 - 0xF0000FFF : System ROM Table
// ---------------------------------------------------------- // ----------------------------------------------------------
// Peripheral Selection decode logic // Peripheral Selection decode logic
// ---------------------------------------------------------- // ----------------------------------------------------------
assign apbsys_hsel = hsel & (haddr[31:16]==16'h4000); // 0x40000000 assign apbsys_hsel = hsel & (haddr[31:16]==
BASEADDR_APBSS[31:16]); // 0x40000000
assign gpio0_hsel = hsel & (haddr[31:12]== assign gpio0_hsel = hsel & (haddr[31:12]==
BASEADDR_GPIO0[31:12]); // 0x40010000 BASEADDR_GPIO0[31:12]); // 0x40010000
assign gpio1_hsel = hsel & (haddr[31:12]== assign gpio1_hsel = hsel & (haddr[31:12]==
......
system/nanosoc_regions/systable/verilog/nanosoc_ahb_cs_rom_table.v → system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
+ 1
− 1
View file @ 22c4d4d4
...@@ -74,7 +74,7 @@ ...@@ -74,7 +74,7 @@
// ECOREVNUM bus should be easily identifiable and modifiable. // ECOREVNUM bus should be easily identifiable and modifiable.
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module nanosoc_ahb_cs_rom_table module nanosoc_coresight_systable
#( #(
// ------------------------------------------------------------ // ------------------------------------------------------------
// ROM Table BASE Address // ROM Table BASE Address
......
system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
+ 1
− 1
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...@@ -38,7 +38,7 @@ module nanosoc_region_systable #( ...@@ -38,7 +38,7 @@ module nanosoc_region_systable #(
// ------------------------------- // -------------------------------
// System ROM Table // System ROM Table
// ------------------------------- // -------------------------------
nanosoc_ahb_cs_rom_table #( nanosoc_coresight_systable #(
.BASE (SYSTABLE_BASE), .BASE (SYSTABLE_BASE),
// Entry 0 = Cortex-M0 Processor // Entry 0 = Cortex-M0 Processor
.ENTRY0BASEADDR (32'hE00FF000), .ENTRY0BASEADDR (32'hE00FF000),
......
system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+ 18
− 14
View file @ 22c4d4d4
...@@ -28,6 +28,9 @@ module nanosoc_ss_cpu #( ...@@ -28,6 +28,9 @@ module nanosoc_ss_cpu #(
parameter RESET_ALL_REGS = 0, // Do not reset all registers parameter RESET_ALL_REGS = 0, // Do not reset all registers
parameter INCLUDE_JTAG = 0, // Do not Include JTAG feature parameter INCLUDE_JTAG = 0, // Do not Include JTAG feature
// ROM Table Base Address
parameter [31:0] ROMTABLE_BASE = 32'hE00FF003, // Defaultly Points to Core ROM Table
// Bootrom 0 Parameters // Bootrom 0 Parameters
parameter BOOTROM_ADDR_W = 10, // Size of Bootrom (Based on Address Width) - Default 1KB parameter BOOTROM_ADDR_W = 10, // Size of Bootrom (Based on Address Width) - Default 1KB
...@@ -143,8 +146,9 @@ module nanosoc_ss_cpu #( ...@@ -143,8 +146,9 @@ module nanosoc_ss_cpu #(
.SYST (SYST), // SysTick .SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support .WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines .WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT) // Number of DWT comparators .WPT (WPT), // Number of DWT comparators
) u_manager_cpu_0 ( .ROMTABLE_BASE (ROMTABLE_BASE)
) u_cpu_0 (
// System Input Clocks and Resets // System Input Clocks and Resets
.SYS_FCLK(SYS_FCLK), .SYS_FCLK(SYS_FCLK),
.SYS_SYSRESETn(SYS_SYSRESETn), .SYS_SYSRESETn(SYS_SYSRESETn),
......
slcore_m0_tech @ 0e036061
Compare 0e036061...0e036061
Subproject commit 0e036061823074e2fe41fc7ea83d58367ea3b524
slcorem0_tech @ 3fbedbfb
Subproject commit 3fbedbfb068d360194d1d4b879e5a1eb28930d85
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