From 22c4d4d4130c6f5a4507ca2ea9a74b6680760918 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Mon, 19 Jun 2023 15:36:56 +0100
Subject: [PATCH] Used new FPGA SRAM wrapper and passed ROM Table address to
top of subsystem
---
.gitmodules | 6 +--
..._ahb_bootrom.v => nanosoc_bootrom_cpu_0.v} | 4 +-
.../verilog/nanosoc_region_bootrom_0.v | 4 +-
.../dmem_0/verilog/nanosoc_region_dmem_0.v | 41 +++---------------
.../verilog/nanosoc_region_expram_h.v | 40 +++---------------
.../verilog/nanosoc_region_expram_l.v | 40 +++---------------
.../imem_0/verilog/nanosoc_region_imem_0.v | 42 +++----------------
.../sysio/verilog/nanosoc_region_sysio.v | 16 ++++---
.../sysio/verilog/nanosoc_sysio_decode.v | 8 ++--
...m_table.v => nanosoc_coresight_systable.v} | 2 +-
.../verilog/nanosoc_region_systable.v | 2 +-
.../cpu/verilog/nanosoc_ss_cpu.v | 32 +++++++-------
system/slcore_m0_tech | 1 -
system/slcorem0_tech | 1 +
14 files changed, 65 insertions(+), 174 deletions(-)
rename system/nanosoc_regions/bootrom_0/verilog/{nanosoc_ahb_bootrom.v => nanosoc_bootrom_cpu_0.v} (94%)
rename system/nanosoc_regions/systable/verilog/{nanosoc_ahb_cs_rom_table.v => nanosoc_coresight_systable.v} (99%)
delete mode 160000 system/slcore_m0_tech
create mode 160000 system/slcorem0_tech
diff --git a/.gitmodules b/.gitmodules
index 3c95adc..63ccd3e 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +1,9 @@
[submodule "system/socdebug_tech"]
path = system/socdebug_tech
url = https://git.soton.ac.uk/soclabs/socdebug_tech.git
-[submodule "system/slcore_m0_tech"]
- path = system/slcore_m0_tech
- url = https://git.soton.ac.uk/soclabs/slcore_m0_tech.git
[submodule "system/sldma230_tech"]
path = system/sldma230_tech
url = https://git.soton.ac.uk/soclabs/sldma230_tech.git
+[submodule "system/slcorem0_tech"]
+ path = system/slcorem0_tech
+ url = https://git.soton.ac.uk/soclabs/slcorem0_tech.git
diff --git a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_ahb_bootrom.v b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
similarity index 94%
rename from system/nanosoc_regions/bootrom_0/verilog/nanosoc_ahb_bootrom.v
rename to system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
index 7518659..c4efcb0 100644
--- a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_ahb_bootrom.v
+++ b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// NanoSoC AHB to Bootrom Interface
+// NanoSoC CPU 0 Bootrom
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -9,7 +9,7 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module nanosoc_ahb_bootrom #(
+module nanosoc_bootrom_cpu_0 #(
parameter AW = 10 // Address width
)(
input wire HCLK, // Clock
diff --git a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
index c7a519a..fd393c9 100644
--- a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
+++ b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
@@ -34,9 +34,9 @@ module nanosoc_region_bootrom_0 #(
output wire [SYS_DATA_W-1:0] HRDATA
);
- nanosoc_ahb_bootrom #(
+ nanosoc_bootrom_cpu_0 #(
.AW (BOOTROM_ADDR_W)
- ) u_ahb_bootloader (
+ ) u_bootrom_cpu_0 (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
diff --git a/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v b/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
index 74c23dd..56dfdfc 100644
--- a/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
+++ b/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
@@ -33,17 +33,11 @@ module nanosoc_region_dmem_0 #(
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA
);
-
- wire [DMEM_RAM_ADDR_W-3:0] addr;
- wire [DMEM_RAM_DATA_W-1:0] wdata;
- wire [DMEM_RAM_DATA_W-1:0] rdata;
- wire [3:0] wen;
- wire cs;
- // AHB to SRAM bridge
- cmsdk_ahb_to_sram #(
- .AW (DMEM_RAM_ADDR_W)
- ) u_ahb_to_sdmem (
+ // SRAM Instantiation
+ sl_ahb_sram #(
+ .RAM_ADDR_W (DMEM_RAM_ADDR_W)
+ ) u_dmem_0 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -58,30 +52,7 @@ module nanosoc_region_dmem_0 #(
// AHB Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA),
- .HRESP (HRESP),
-
- // SRAM input
- .SRAMRDATA (rdata),
-
- // SRAM Outputs
- .SRAMADDR (addr),
- .SRAMWDATA (wdata),
- .SRAMWEN (wen),
- .SRAMCS (cs)
- );
-
- // SRAM model
- cmsdk_fpga_sram #(
- .AW (DMEM_RAM_ADDR_W)
- ) u_dmem_0 (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr),
- .WDATA (wdata),
- .WREN (wen),
- .CS (cs),
-
- // SRAM Output
- .RDATA (rdata)
+ .HRESP (HRESP)
);
+
endmodule
\ No newline at end of file
diff --git a/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v b/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
index 97ac03b..c93b82f 100644
--- a/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
+++ b/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
@@ -34,22 +34,16 @@ module nanosoc_region_expram_h #(
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA
);
-
- wire [EXPRAM_H_RAM_ADDR_W-3:0] addr;
- wire [EXPRAM_H_RAM_DATA_W-1:0] wdata;
- wire [EXPRAM_H_RAM_DATA_W-1:0] rdata;
- wire [3:0] wen;
- wire cs;
// AHB to SRAM bridge
- cmsdk_ahb_to_sram #(
- .AW (EXPRAM_H_RAM_ADDR_W)
- ) u_ahb_to_sram8 (
+ sl_ahb_sram #(
+ .RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W)
+ ) u_expram_h (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
- .HADDR (HADDR[EXPRAM_H_RAM_ADDR_W-1:0]),
+ .HADDR (HADDR [EXPRAM_H_RAM_ADDR_W-1:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
@@ -59,31 +53,7 @@ module nanosoc_region_expram_h #(
// AHB Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA),
- .HRESP (HRESP),
-
- // SRAM input
- .SRAMRDATA (rdata),
-
- // SRAM Outputs
- .SRAMADDR (addr),
- .SRAMWDATA (wdata),
- .SRAMWEN (wen),
- .SRAMCS (cs)
+ .HRESP (HRESP)
);
-
- // SRAM model
- cmsdk_fpga_sram #(
- .AW (EXPRAM_H_RAM_ADDR_W)
- ) u_expram_h (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr),
- .WDATA (wdata),
- .WREN (wen),
- .CS (cs),
-
- // SRAM Output
- .RDATA (rdata)
- );
endmodule
\ No newline at end of file
diff --git a/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v b/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
index 53ba0c7..5e43f89 100644
--- a/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
+++ b/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
@@ -34,17 +34,11 @@ module nanosoc_region_expram_l #(
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA
);
-
- wire [EXPRAM_L_RAM_ADDR_W-3:0] addr;
- wire [EXPRAM_L_RAM_DATA_W-1:0] wdata;
- wire [EXPRAM_L_RAM_DATA_W-1:0] rdata;
- wire [3:0] wen;
- wire cs;
- // AHB to SRAM bridge
- cmsdk_ahb_to_sram #(
- .AW (EXPRAM_L_RAM_ADDR_W)
- ) u_ahb_to_sram8 (
+ // SRAM Instantiation
+ sl_ahb_sram #(
+ .RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W)
+ ) u_expram_l (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -59,31 +53,7 @@ module nanosoc_region_expram_l #(
// AHB Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA),
- .HRESP (HRESP),
-
- // SRAM input
- .SRAMRDATA (rdata),
-
- // SRAM Outputs
- .SRAMADDR (addr),
- .SRAMWDATA (wdata),
- .SRAMWEN (wen),
- .SRAMCS (cs)
+ .HRESP (HRESP)
);
-
- // SRAM model
- cmsdk_fpga_sram #(
- .AW (EXPRAM_L_RAM_ADDR_W)
- ) u_expram_l (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr),
- .WDATA (wdata),
- .WREN (wen),
- .CS (cs),
-
- // SRAM Output
- .RDATA (rdata)
- );
endmodule
\ No newline at end of file
diff --git a/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v b/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
index 16f2b7f..38f887e 100644
--- a/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+++ b/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
@@ -35,17 +35,12 @@ module nanosoc_region_imem_0 #(
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA
);
-
- wire [IMEM_RAM_ADDR_W-3:0] addr;
- wire [IMEM_RAM_DATA_W-1:0] wdata;
- wire [IMEM_RAM_DATA_W-1:0] rdata;
- wire [3:0] wen;
- wire cs;
- // AHB to SRAM bridge
- cmsdk_ahb_to_sram #(
- .AW (IMEM_RAM_ADDR_W)
- ) u_ahb_to_simem (
+ // SRAM Instantiation
+ sl_ahb_sram #(
+ .RAM_ADDR_W (IMEM_RAM_ADDR_W),
+ .FILENAME (IMEM_RAM_FPGA_IMG)
+ ) u_imem_0 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -60,32 +55,7 @@ module nanosoc_region_imem_0 #(
// AHB Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA),
- .HRESP (HRESP),
-
- // SRAM input
- .SRAMRDATA (rdata),
-
- // SRAM Outputs
- .SRAMADDR (addr),
- .SRAMWDATA (wdata),
- .SRAMWEN (wen),
- .SRAMCS (cs)
- );
-
- // SRAM model
- cmsdk_fpga_sram #(
- .AW (IMEM_RAM_ADDR_W),
- .filename(IMEM_RAM_FPGA_IMG)
- ) u_imem_0 (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr),
- .WDATA (wdata),
- .WREN (wen),
- .CS (cs),
-
- // SRAM Output
- .RDATA (rdata)
+ .HRESP (HRESP)
);
endmodule
\ No newline at end of file
diff --git a/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index f3bbc4b..9d0750d 100644
--- a/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -15,7 +15,7 @@ module nanosoc_region_sysio #(
parameter SYS_ADDR_W=32, // System Address Width
parameter SYS_DATA_W=32, // System Data Width
parameter APB_ADDR_W=12, // APB Peripheral Address Width
- parameter APB_DATA_W=32 // APB Peripheral Data Width
+ parameter APB_DATA_W=32 // APB Peripheral Data Width
)(
input wire FCLK, // Free-running system clock
input wire PORESETn, // Power-On-Reset reset (active-low)
@@ -105,9 +105,11 @@ module nanosoc_region_sysio #(
output wire [15:0] p1_altfunc // GPIO 1 alternate function (pin mux)
);
-
+ // Sysctrl base address
+ localparam BASEADDR_APBSS = 32'h4000_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
+ localparam BASEADDR_SYSCTRL = 32'h4001_f000; // Sysctrl peripheral basse address
localparam BE = 0;
// ------------------------------------------------------------
@@ -142,8 +144,10 @@ module nanosoc_region_sysio #(
// AHB address decode
nanosoc_sysio_decode #(
+ .BASEADDR_APBSS (BASEADDR_APBSS),
.BASEADDR_GPIO0 (BASEADDR_GPIO0),
- .BASEADDR_GPIO1 (BASEADDR_GPIO1)
+ .BASEADDR_GPIO1 (BASEADDR_GPIO1),
+ .BASEADDR_SYSCTRL (BASEADDR_SYSCTRL)
) u_addr_decode (
// System Address
.hsel (HSEL),
@@ -161,7 +165,7 @@ module nanosoc_region_sysio #(
.PORT1_ENABLE (1), // GPIO Port 0
.PORT2_ENABLE (1), // GPIO Port 1
.PORT3_ENABLE (1), // SYS control
- .PORT4_ENABLE (1), // default
+ .PORT4_ENABLE (1), // Default
.PORT5_ENABLE (0),
.PORT6_ENABLE (0),
.PORT7_ENABLE (0),
@@ -272,7 +276,7 @@ module nanosoc_region_sysio #(
.ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
.BE (BE)
)
- u_ahb_gpio_0 (
+ u_nanosoc_gpio_0 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -305,7 +309,7 @@ module nanosoc_region_sysio #(
.ALTERNATE_FUNC_MASK (16'h002A), // pin muxing for Port #1
.ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
.BE (BE)
- ) u_ahb_gpio_1 (
+ ) u_nanosoc_gpio_1 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
diff --git a/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v b/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
index 609839a..2b8f6ad 100644
--- a/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+++ b/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
@@ -40,11 +40,13 @@
module nanosoc_sysio_decode #(
parameter SYS_ADDR_W = 32,
+ // APB Subsystem peripheral base address
+ parameter BASEADDR_APBSS = 32'h4000_0000,
// GPIO0 peripheral base address
parameter BASEADDR_GPIO0 = 32'h4001_0000,
// GPIO1 peripheral base address
parameter BASEADDR_GPIO1 = 32'h4001_1000,
- // GPIO1 peripheral base address
+ // Sysctrl base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000
)(
// System Address
@@ -66,13 +68,13 @@ module nanosoc_sysio_decode #(
// 0x40010000 - 0x40010FFF : AHB peripherals (GPIO0)
// 0x40011000 - 0x40011FFF : AHB peripherals (GPIO1)
// 0x4001F000 - 0x4001FFFF : AHB peripherals (SYS control)
- // 0xF0000000 - 0xF0000FFF : System ROM Table
// ----------------------------------------------------------
// Peripheral Selection decode logic
// ----------------------------------------------------------
- assign apbsys_hsel = hsel & (haddr[31:16]==16'h4000); // 0x40000000
+ assign apbsys_hsel = hsel & (haddr[31:16]==
+ BASEADDR_APBSS[31:16]); // 0x40000000
assign gpio0_hsel = hsel & (haddr[31:12]==
BASEADDR_GPIO0[31:12]); // 0x40010000
assign gpio1_hsel = hsel & (haddr[31:12]==
diff --git a/system/nanosoc_regions/systable/verilog/nanosoc_ahb_cs_rom_table.v b/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
similarity index 99%
rename from system/nanosoc_regions/systable/verilog/nanosoc_ahb_cs_rom_table.v
rename to system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
index f6345a2..900136b 100644
--- a/system/nanosoc_regions/systable/verilog/nanosoc_ahb_cs_rom_table.v
+++ b/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
@@ -74,7 +74,7 @@
// ECOREVNUM bus should be easily identifiable and modifiable.
//-----------------------------------------------------------------------------
-module nanosoc_ahb_cs_rom_table
+module nanosoc_coresight_systable
#(
// ------------------------------------------------------------
// ROM Table BASE Address
diff --git a/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v b/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
index 36b9f63..9fe8ae7 100644
--- a/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
+++ b/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
@@ -38,7 +38,7 @@ module nanosoc_region_systable #(
// -------------------------------
// System ROM Table
// -------------------------------
- nanosoc_ahb_cs_rom_table #(
+ nanosoc_coresight_systable #(
.BASE (SYSTABLE_BASE),
// Entry 0 = Cortex-M0 Processor
.ENTRY0BASEADDR (32'hE00FF000),
diff --git a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
index b50f230..e41f96a 100644
--- a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+++ b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
@@ -28,8 +28,11 @@ module nanosoc_ss_cpu #(
parameter RESET_ALL_REGS = 0, // Do not reset all registers
parameter INCLUDE_JTAG = 0, // Do not Include JTAG feature
+ // ROM Table Base Address
+ parameter [31:0] ROMTABLE_BASE = 32'hE00FF003, // Defaultly Points to Core ROM Table
+
// Bootrom 0 Parameters
- parameter BOOTROM_ADDR_W = 10, // Size of Bootrom (Based on Address Width) - Default 1KB
+ parameter BOOTROM_ADDR_W = 10, // Size of Bootrom (Based on Address Width) - Default 1KB
// IMEM 0 Parameters
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
@@ -132,19 +135,20 @@ module nanosoc_ss_cpu #(
// CPU Core 0 Instantiation
// -------------------------------
slcorem0 #(
- .ACG (CLKGATE_PRESENT), // Architectural clock gating
- .BE (BE), // Big-endian
- .BKPT (BKPT), // Number of breakpoint comparators
- .DBG (DBG), // Debug configuration
- .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
- .NUMIRQ (NUMIRQ), // Number of Interrupts
- .RAR (RESET_ALL_REGS), // Reset All Registers
- .SMUL (SMUL), // Multiplier configuration
- .SYST (SYST), // SysTick
- .WIC (WIC), // Wake-up interrupt controller support
- .WICLINES (WICLINES), // Supported WIC lines
- .WPT (WPT) // Number of DWT comparators
- ) u_manager_cpu_0 (
+ .ACG (CLKGATE_PRESENT), // Architectural clock gating
+ .BE (BE), // Big-endian
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
+ .NUMIRQ (NUMIRQ), // Number of Interrupts
+ .RAR (RESET_ALL_REGS), // Reset All Registers
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT), // Number of DWT comparators
+ .ROMTABLE_BASE (ROMTABLE_BASE)
+ ) u_cpu_0 (
// System Input Clocks and Resets
.SYS_FCLK(SYS_FCLK),
.SYS_SYSRESETn(SYS_SYSRESETn),
diff --git a/system/slcore_m0_tech b/system/slcore_m0_tech
deleted file mode 160000
index 0e03606..0000000
--- a/system/slcore_m0_tech
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0e036061823074e2fe41fc7ea83d58367ea3b524
diff --git a/system/slcorem0_tech b/system/slcorem0_tech
new file mode 160000
index 0000000..3fbedbf
--- /dev/null
+++ b/system/slcorem0_tech
@@ -0,0 +1 @@
+Subproject commit 3fbedbfb068d360194d1d4b879e5a1eb28930d85
--
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