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Commit 437bacbc authored by dam1n19's avatar dam1n19
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SOC1-167: Removed compiled files from repo and created python-based bootrom... 

SOC1-167: Removed compiled files from repo and created python-based bootrom generation script to allow for compilation of new bootrom before simulation
parent 77ce3e16
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.gitignore
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− 5
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......@@ -8,11 +8,11 @@
/software/*/*.o
# Compile Test Code Removal
/system/testcodes/*/*.elf
/system/testcodes/*/*.ELF
/system/testcodes/*/*.hex
/system/testcodes/*/*.lst
/system/testcodes/*/*.o
system/testcodes/*/*.elf
system/testcodes/*/*.ELF
system/testcodes/*/*.hex
system/testcodes/*/*.lst
system/testcodes/*/*.o
# Bootrom removal
/system/src/bootrom/verilog/*
......
system/aes/aes128_tests/makefile
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......@@ -32,7 +32,7 @@
CPU_PRODUCT = CORTEX_M0
# Shared software directory
SOFTWARE_DIR = ../../../../software
SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
......
system/makefile
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......@@ -80,6 +80,10 @@ else
MEM_INIT :=
endif
# Bootrom Parameters:
BOOTROM_ADDRW ?= 8
BOOTROM_HEX ?= $(NANOSOC_TECH_DIR)/system/testcodes/bootloader/bootloader.hex
ADP_PATH := $(shell realpath $(ADP_FILE))
ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
......@@ -191,22 +195,10 @@ run_xm : code compile_xm
@if [ ! -d $(SIM_DIR)/logs ] ; then \
mkdir $(SIM_DIR)/logs; \
fi
# Bootrom generation
ifneq ($(BOOTROM_GEN),)
# Create directories for bootrom for this simulation
mkdir -p $(SIM_DIR)/bootrom/hex/
mkdir -p $(SIM_DIR)/bootrom/verilog/
mkdir -p $(SIM_DIR)/bootrom/bintxt/
# Copy bootrom hex to simulaiton directory
cp $(TESTCODES_DIR)/bootloader/bootloader.hex $(SIM_DIR)/bootrom/hex/
endif
@echo run > $(SIM_DIR)/run.tcl.tmp
@echo exit >> $(SIM_DIR)/run.tcl.tmp
@mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
ifneq ($(BOOTROM_GEN),)
cp -r $(SIM_DIR)/bootrom $(PROJ_SYS_DIR)
endif
# @make verify
# Run simulation in interactive mode
......@@ -308,6 +300,9 @@ bootrom:
fi ;\
fi ;\
cp $(BOOTLOADER).hex $(SIM_DIR)/$(BOOTLOADER).hex ;\
mkdir -p $(PROJ_SYS_DIR)/bootrom/verilog/ ;\
mkdir -p $(PROJ_SYS_DIR)/bootrom/bintxt/ ;\
python3 bootrom_gen.py -a $(BOOTROM_ADDRW) -i $(BOOTLOADER).hex -v $(PROJ_SYS_DIR)/bootrom/verilog/bootrom.v -b $(PROJ_SYS_DIR)/bootrom/bintxt/bootrom.bintxt ;\
cd $(SIM_DIR) )
# Compile test code
......
system/testcodes/apb_mux_tests/makefile
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......@@ -32,7 +32,7 @@
CPU_PRODUCT = CORTEX_M0PLUS
# Shared software directory
SOFTWARE_DIR = ../../../../software
SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
......
system/testcodes/bootloader/bootloader.ELF deleted 100644 → 0
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system/testcodes/bootloader/bootloader.hex deleted 100644 → 0
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system/testcodes/bootloader/bootloader.lst deleted 100644 → 0
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system/testcodes/bootloader/bootloader.o deleted 100644 → 0
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system/testcodes/bootloader/bootrom_gen.py 0 → 100755
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#!/usr/bin/env python3
#------------------------------------------------------------------------------------
# Verilog and Binary Bootrom Generation Script
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
# Copyright (c) 2023, SoC Labs (www.soclabs.org)
#------------------------------------------------------------------------------------
import argparse
import math
from string import Template
from datetime import datetime
v_template_head = f"""//------------------------------------------------------------------------------------
// Auto-generated synthesizable Bootrom
//
// Generated from bootrom_gen.py
//
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
// Date: $date
// Copyright (c) 2021-3, SoC Labs (www.soclabs.org)
//------------------------------------------------------------------------------------
module bootrom (
input wire CLK,
input wire EN,
input wire [$address_width:2] ADDR,
output reg [31:0] RDATA );
reg [$address_width:2] addr_r;
always @(posedge CLK) if (EN) addr_r <= ADDR;
always @(addr_r)
case(addr_r[$address_width:2])
"""
v_template_foot = """ default : RDATA <=32'h0;
endcase
endmodule"""
def bootrom_gen(args):
# Extract Data from Parsed Arguments
input_hex = args.input_hex
address_width = args.address_width
output_verilog = args.verilog_output
output_binary = args.binary_output
# Create Binary and Verilog Outputs
print(f"Generating Bootrom {input_hex}")
bootrom_verilog, bootrom_binary = output_construct(input_hex, address_width)
# Write Out Verilog File
f_verilog = open(output_verilog, "w")
f_verilog.write(bootrom_verilog)
f_verilog.close()
# Write Out Binary File
f_binary = open(output_binary, "w")
f_binary.write(bootrom_binary)
f_binary.close()
def output_construct(input_hex, address_width):
# Read in Hex File
f = open(input_hex, "r")
hex_bytes = f.readlines()
f.close()
# Number of bytes expected depending on address_width
address_bytes = 1 << (address_width + 2)
# Fill hex_bytes with zeros for addresses than aren't in the hex file
while (len(hex_bytes) < address_bytes): hex_bytes.append("00")
hex_words = math.ceil(len(hex_bytes)/4)
hex_data = []
# Combine bytes into words
for i in range(hex_words):
temp_hex_word= f"{hex_bytes[i*4+3].rstrip()}{hex_bytes[(i*4)+2].rstrip()}{hex_bytes[(i*4)+1].rstrip()}{hex_bytes[(i*4)].rstrip()}"
hex_data.append(int(temp_hex_word, 16))
# Get Date and Time to put in Generated Header
date_str = datetime.today().strftime('%Y-%m-%d %H:%M:%S')
# Generate Verilog Header from Template
temp_bootrom_obj = Template(v_template_head)
temp_verilog = temp_bootrom_obj.substitute(
address_width=address_width+1,
date=date_str
)
bootrom_verilog = temp_verilog
bootrom_binary = ""
# Append Hex Data to File
for i, word in enumerate(hex_data):
if address_width > 8:
temp_verilog = f""" {address_width:d}'h{i:03x} : RDATA <= 32'h{word:08x}; // 0x{i*4:04x}\n"""
else:
temp_verilog = f""" {address_width:d}'h{i:02x} : RDATA <= 32'h{word:08x}; // 0x{i*4:04x}\n"""
temp_binary = f"""{word:032b}\n"""
bootrom_verilog += temp_verilog
bootrom_binary += temp_binary
# Append footer to Verilog file
bootrom_verilog += v_template_foot
return bootrom_verilog, bootrom_binary
if __name__ == "__main__":
# Capture Arguments from Command Line
parser = argparse.ArgumentParser(description='Generates NanoSoC CPU Bootrom File')
parser.add_argument("-i", "--input_hex", type=str, help="Input Hex File to Generate Bootrom from")
parser.add_argument("-a", "--address_width", type=int, help="Address Width (In 32bit Words) of Bootrom")
parser.add_argument("-v", "--verilog_output", type=str, help="Output Bootrom verilog file")
parser.add_argument("-b", "--binary_output", type=str, help="Output Bootrom binary file")
args = parser.parse_args()
bootrom_gen(args)
\ No newline at end of file
system/testcodes/bootloader/makefile
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......@@ -6,7 +6,7 @@
#//
#// David Flynn (d.w.flynn@soton.ac.uk)
#//
#// Copyright 2021-3, SoC Labs (www.soclabs.org)
#// Copyright � 2021-3, SoC Labs (www.soclabs.org)
#//-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
......@@ -43,7 +43,7 @@
CPU_PRODUCT = CORTEX_M0
# Shared software directory
SOFTWARE_DIR = ../../../../software
SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
......
system/testcodes/bootloader/startup_CMSDK_CM0.o deleted 100644 → 0
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system/testcodes/debug_tests/makefile
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......@@ -32,7 +32,7 @@
CPU_PRODUCT = CORTEX_M0
# Shared software directory
SOFTWARE_DIR = ../../../../software
SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
GENERIC_DIR = ../generic
......
system/testcodes/default_slaves_tests/makefile
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......@@ -32,7 +32,7 @@ CPU_PRODUCT = CORTEX_M0PLUS
# Shared software directory
# Shared software directory
SOFTWARE_DIR = ../../../../software
SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
......
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system/testcodes/dhry/makefile
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......@@ -32,7 +32,7 @@ CPU_PRODUCT = CORTEX_M0PLUS
# Shared software directory
# Shared software directory
SOFTWARE_DIR = ../../../../software
SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
......
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