chip level CLK and TEST pins (replace XTAL1, XTAL2)

.../targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl

...argets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl

...argets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl

fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl

...rgets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl

nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v

nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v

verif/cocotb/test_adp.py

verif/tb/verilog/nanosoc_tb.v