chip level CLK and TEST pins (replace XTAL1, XTAL2)
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- fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl 2 additions, 2 deletions.../targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
- fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl 1 addition, 1 deletion...argets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
- fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl 1 addition, 1 deletion...argets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
- fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl 1 addition, 1 deletionfpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
- fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl 1 addition, 1 deletion...rgets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
- nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v 12 additions, 12 deletionsnanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
- nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v 20 additions, 20 deletionsnanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
- verif/cocotb/test_adp.py 6 additions, 6 deletionsverif/cocotb/test_adp.py
- verif/tb/verilog/nanosoc_tb.v 15 additions, 15 deletionsverif/tb/verilog/nanosoc_tb.v
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