From 33cd9cfd6ebcd32b66a85ce2a1c78575e0ec401e Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Thu, 21 Sep 2023 08:31:01 +0100
Subject: [PATCH] chip level CLK and TEST pins (replace XTAL1, XTAL2)

---
 .../vivado_script/2021_1/nanosoc_design.tcl   |  4 +-
 .../vivado_script/2021_1/nanosoc_design.tcl   |  2 +-
 .../vivado_script/2021_1/nanosoc_design.tcl   |  2 +-
 .../vivado_script/2021_1/nanosoc_design.tcl   |  2 +-
 .../vivado_script/2021_1/nanosoc_design.tcl   |  2 +-
 .../nanosoc_chip/chip/verilog/nanosoc_chip.v  | 24 +++++------
 .../pads/glib/verilog/nanosoc_chip_pads.v     | 40 +++++++++----------
 verif/cocotb/test_adp.py                      | 12 +++---
 verif/tb/verilog/nanosoc_tb.v                 | 30 +++++++-------
 9 files changed, 59 insertions(+), 59 deletions(-)

diff --git a/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
index 105a5b2..0364263 100644
--- a/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
@@ -559,7 +559,7 @@ proc create_root_design { parentCell } {
   set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
 
   # Create port connections
-  connect_bd_net -net EXT_CLK_1 [get_bd_ports EXT_CLK] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i]
+  connect_bd_net -net EXT_CLK_1 [get_bd_ports EXT_CLK] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i]
   connect_bd_net -net UART_RX_1 [get_bd_ports UART_RX] [get_bd_pins cmsdk_socket/UART_RX]
   connect_bd_net -net cmsdk_socket_UART_TX [get_bd_ports UART_TX] [get_bd_pins cmsdk_socket/UART_TX]
   connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
@@ -616,4 +616,4 @@ proc available_tcl_procs { } {
    puts "##################################################################"
 }
 
-available_tcl_procs
\ No newline at end of file
+available_tcl_procs
diff --git a/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
index ac6bf09..9fe056c 100644
--- a/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
@@ -1111,7 +1111,7 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
   connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
   connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
   connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
 
   # Create address segments
   assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
diff --git a/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
index ac6bf09..9fe056c 100644
--- a/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
@@ -1111,7 +1111,7 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
   connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
   connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
   connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
 
   # Create address segments
   assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
diff --git a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
index 8342d0d..61dd3da 100644
--- a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
@@ -601,7 +601,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
   connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
   connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
 
   # Create address segments
   assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
diff --git a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
index ac6bf09..9fe056c 100644
--- a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
@@ -1111,7 +1111,7 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
   connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
   connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
   connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
 
   # Create address segments
   assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
diff --git a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 028beac..9081da4 100644
--- a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -19,8 +19,9 @@ module nanosoc_chip #(
   inout  wire          VDD,
   inout  wire          VSS,
 `endif
-  input  wire          xtal_clk_i,
-  output wire          xtal_clk_o,
+  input  wire          clk_i,
+//  output wire          xtal_clk_o,
+  input  wire          test_i,
   input  wire          nrst_i,
   input  wire  [15:0]  p0_i, // level-shifted input from pad
   output wire  [15:0]  p0_o, // output port drive
@@ -30,11 +31,11 @@ module nanosoc_chip #(
   output wire  [15:0]  p1_o, // output port drive
   output wire  [15:0]  p1_e, // active high output drive enable (pad tech dependent)
   output wire  [15:0]  p1_z, // active low output drive enable (pad tech dependent)
-  input  wire          swdio_i,
+  input  wire          swdio_i, // alternate test clock control
   output wire          swdio_o,
   output wire          swdio_e,
   output wire          swdio_z,
-  input  wire          swdclk_i
+  input  wire          swdclk_i // alternate test scan enable
 );
 
   //--------------------------
@@ -90,20 +91,19 @@ module nanosoc_chip #(
   // Technology-specific PLL/Frequecy synthesizer would generate
   //   CLK, FCLK (Free running system clock)
   // from
-  //    xtal_clk_i
+  //    clk_i
   
-  assign PLL_CLK    = xtal_clk_i; // Default to no PLL
+  assign PLL_CLK    = clk_i; // Default to no PLL
   
-  assign SYS_SCANENABLE   = 1'b0; 
-  assign SYS_TESTMODE     = 1'b0;   
-  assign SYS_SCANINHCLK   = 1'b0; 
+  assign SYS_SCANENABLE   = test_i & swdio_i; 
+  assign SYS_TESTMODE     = test_i;   
+  assign SYS_SCANINHCLK   = test_i & swdclk_i; 
   
   //--------------------------
   // Clock Wiring
   //--------------------------
   
-  assign SYS_CLK    = (SYS_TESTMODE) ? xtal_clk_i : PLL_CLK;
-  assign xtal_clk_o = SYS_XTALCLK_OUT;
+  assign SYS_CLK    = (SYS_TESTMODE) ? clk_i : PLL_CLK;
   
   //--------------------------
   // SWD Wiring
@@ -205,4 +205,4 @@ module nanosoc_chip #(
       .P1_OUT_EN_MUX(P1_OUT_EN_MUX)
   );
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
index a54aec5..780e03a 100644
--- a/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+++ b/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
@@ -43,20 +43,20 @@ module nanosoc_chip_pads (
   inout  wire          VDD,
   inout  wire          VSS,
 `endif
-  inout  wire          XTAL1, // input
-  inout  wire          XTAL2, // output
+  inout  wire          CLK, // input
+  inout  wire          TEST, // output
   inout  wire          NRST,  // active low reset
   inout  wire  [15:0]  P0,
   inout  wire  [15:0]  P1,
-  inout  wire          SWDIOTMS,
-  inout  wire          SWCLKTCK);
+  inout  wire          SWDIO,
+  inout  wire          SWDCK);
 
 
 //------------------------------------
 // internal wires
 
-  wire          xtal_clk_i;
-  wire          xtal_clk_o;
+  wire          clk_i;
+  wire          test_i;
   wire          nrst_i;
   wire  [15:0]  p0_i; // level-shifted input from pad
   wire  [15:0]  p0_o; // output port drive
@@ -84,8 +84,8 @@ module nanosoc_chip_pads (
   .VDD        (VDD),
   .VSS        (VSS),
 `endif
-  .xtal_clk_i(xtal_clk_i),
-  .xtal_clk_o(xtal_clk_o),
+  .clk_i(clk_i),
+  .test_i(test_i),
   .nrst_i(nrst_i),
   .p0_i(p0_i), // level-shifted input from pad
   .p0_o(p0_o), // output port drive
@@ -136,18 +136,18 @@ PAD_VSS uPAD_VSS_1(
 
 // Clock, Reset and Serial Wire Debug ports
 
-PAD_INOUT8MA_NOE uPAD_XTAL_I (
-   .PAD (XTAL1), 
+PAD_INOUT8MA_NOE uPAD_CLK_I (
+   .PAD (CLK), 
    .O   (tielo),
-   .I   (xtal_clk_i), 
+   .I   (clk_i), 
    .NOE (tiehi)
    );
 
-PAD_INOUT8MA_NOE uPAD_XTAL_O (
-   .PAD (XTAL2), 
-   .O   (xtal_clk_o),
-   .I   ( ), 
-   .NOE (tielo)
+PAD_INOUT8MA_NOE uPAD_XTAL_I (
+   .PAD (TEST), 
+   .O   (tielo),
+   .I   (test_i), 
+   .NOE (tiehi)
    );
 
 PAD_INOUT8MA_NOE uPAD_NRST_I (
@@ -157,15 +157,15 @@ PAD_INOUT8MA_NOE uPAD_NRST_I (
    .NOE (tiehi)
    );
 
-PAD_INOUT8MA_NOE uPAD_SWDIO_I (
-   .PAD (SWDIOTMS), 
+PAD_INOUT8MA_NOE uPAD_SWDIO_IO (
+   .PAD (SWDIO), 
    .O   (swdio_o), 
    .I   (swdio_i),
    .NOE (swdio_z)
    );
 
-PAD_INOUT8MA_NOE uPAD_SWDCLK_I (
-   .PAD (SWCLKTCK), 
+PAD_INOUT8MA_NOE uPAD_SWDCK_I (
+   .PAD (SWDCK), 
    .O   (tielo), 
    .I   (swdclk_i),
    .NOE (tiehi)
diff --git a/verif/cocotb/test_adp.py b/verif/cocotb/test_adp.py
index 43bcbe3..3113dd5 100644
--- a/verif/cocotb/test_adp.py
+++ b/verif/cocotb/test_adp.py
@@ -26,8 +26,8 @@ CLK_PERIOD = (10, "ns")
 def setup_adp(dut):
     logging.getLogger("cocotb.nanosoc_tb.rxd8").setLevel(logging.WARNING)
     logging.getLogger("cocotb.nanosoc_tb.txd8").setLevel(logging.WARNING)
-    adp_sender = AxiStreamSource(AxiStreamBus.from_prefix(dut, "txd8"), dut.XTAL1, dut.NRST, reset_active_level=False)
-    adp_reciever = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rxd8"), dut.XTAL1, dut.NRST, reset_active_level=False)
+    adp_sender = AxiStreamSource(AxiStreamBus.from_prefix(dut, "txd8"), dut.CLK, dut.NRST, reset_active_level=False)
+    adp_reciever = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rxd8"), dut.CLK, dut.NRST, reset_active_level=False)
     driver = ADP(dut, adp_sender, adp_reciever)
     driver.write8(0x00)
     return driver
@@ -36,11 +36,11 @@ def setup_adp(dut):
 @cocotb.coroutine
 async def setup_dut(dut):
     adp_driver = setup_adp(dut)
-    cocotb.start_soon(Clock(dut.XTAL1, *CLK_PERIOD).start())
+    cocotb.start_soon(Clock(dut.CLK, *CLK_PERIOD).start())
     dut.NRST.value = 0
-    await ClockCycles(dut.XTAL1, 2)
+    await ClockCycles(dut.CLK, 2)
     dut.NRST.value = 1
-    await ClockCycles(dut.XTAL1, 2)
+    await ClockCycles(dut.CLK, 2)
     return adp_driver
 
 # Wait for bootcode to finish
@@ -129,7 +129,7 @@ async def test_adp_hello(dut):
     await adp_driver.read_bytes("R 4")
     await adp_driver.monitorModeExit()
     dut.NRST.value = 0
-    await ClockCycles(dut.XTAL1, 2)
+    await ClockCycles(dut.CLK, 2)
     dut.NRST.value = 1
     for i in range(4):
         adp_driver.info(adp_driver.readLine())
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index adf6e25..e16d5b0 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -39,8 +39,8 @@
 
 module nanosoc_tb;
 
-  wire        XTAL1;   // crystal pin 1
-  wire        XTAL2;   // crystal pin 2
+  wire        CLK;   // crystal pin 1
+  wire        TEST;   // crystal pin 2
   wire        NRST;    // active low reset
 
   wire [15:0] P0;      // Port 0
@@ -93,7 +93,7 @@ SROM_Ax32
     .romgen (1)
    )
    u_BOOTROM (
-    .CLK(XTAL1),
+    .CLK(CLK),
     .ADDR(8'h0),
     .SEL(1'b0),
     .RDATA( )
@@ -111,13 +111,13 @@ SROM_Ax32
   .VDD        (VDD),
   .VSS        (VSS),
 `endif
-  .XTAL1      (XTAL1),  // input
-  .XTAL2      (XTAL2),  // output
+  .CLK        (CLK),  // input
+  .TEST       (TEST),  // input
   .NRST       (NRST),   // active low reset
   .P0         (P0),
   .P1         (P1),
-  .SWDIOTMS   (SWDIOTMS),
-  .SWCLKTCK   (SWCLKTCK)
+  .SWDIO      (SWDIOTMS),
+  .SWDCK      (SWCLKTCK)
   );
 
  // --------------------------------------------------------------------------------
@@ -125,7 +125,7 @@ SROM_Ax32
  // --------------------------------------------------------------------------------
  `ifndef COCOTB_SIM
   nanosoc_clkreset u_nanosoc_clkreset(
-  .CLK  (XTAL1),
+  .CLK  (CLK),
   .NRST (NRST)
   );
   `endif
@@ -172,7 +172,7 @@ SROM_Ax32
   // If PCLK is running at slower speed, the UART output will also be slower
   assign PCLK = u_cmsdk_mcu.u_cmsdk_mcu.PCLK;
 `else
-  assign PCLK = XTAL1;
+  assign PCLK = CLK;
 `endif
 
  // --------------------------------------------------------------------------------
@@ -273,7 +273,7 @@ reg baud_clk_del;
   nanosoc_axi_stream_io_8_txd_from_file #(
     .TXDFILENAME(ADP_FILENAME)
   ) u_nanosoc_axi_stream_io_8_txd_from_file (
-    .aclk       (XTAL1),
+    .aclk       (CLK),
     .aresetn    (NRST),
     .txd8_ready (txd8_tready),
     .txd8_valid (txd8_tvalid),
@@ -294,7 +294,7 @@ reg baud_clk_del;
   .ft_miosio_i  (ft_miosio_i),
   .ft_miosio_o  (ft_miosio_o),
   .ft_miosio_z  (ft_miosio_z),
-  .aclk         (XTAL1),
+  .aclk         (CLK),
   .aresetn      (NRST),
   .rxd_tready_o (txd8_tready),
   .rxd_tvalid_i (txd8_tvalid),
@@ -308,7 +308,7 @@ reg baud_clk_del;
   nanosoc_axi_stream_io_8_rxd_to_file#(
     .RXDFILENAME("logs/ft1248_out.log")
   ) u_nanosoc_axi_stream_io_8_rxd_to_file (
-    .aclk         (XTAL1),
+    .aclk         (CLK),
     .aresetn      (NRST),
     .rxd8_ready   (rxd8_tready),
     .rxd8_valid   (rxd8_tvalid),
@@ -319,7 +319,7 @@ reg baud_clk_del;
 nanosoc_track_tb_iostream
   u_nanosoc_track_tb_iostream
   (
-  .aclk         (XTAL1),
+  .aclk         (CLK),
   .aresetn      (NRST),
   .rxd8_ready   (rxd8_tready),
   .rxd8_valid   (rxd8_tvalid),
@@ -340,7 +340,7 @@ nanosoc_ft1248x1_track
   .ft_ssn_i     (ft_ssn_out),
   .ft_miso_i    (ft_miso_in),
   .ft_miosio_i  (ft_miosio_i),
-  .aclk         (XTAL1),
+  .aclk         (CLK),
   .aresetn      (NRST),
   .FTDI_CLK2UART_o      (ft_clk2uart),  // Clock (baud rate)
   .FTDI_OP2UART_o       (ft_rxd2uart),  // Received data to UART capture
@@ -659,7 +659,7 @@ nanosoc_ft1248x1_track
   u_cmsdk_debug_tester
   (
    // Clock and Reset
-   .CLK                                 (XTAL1),
+   .CLK                                 (CLK),
    .PORESETn                            (NRST),
 
    // Command Interface
-- 
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