Changed Filelist to point at Filelist in subrepositories and fixed compile_xm dependencies

flist/nanosoc.flist → flist/nanosoc_ip.flist

 //-----------------------------------------------------------------------------
-// NanoSoC Chip Related IP Filelist
+// NanoSoC IP Filelist
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -16,9 +16,15 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC IP search path    =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+// NanoSoC Chip Pads Level
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
 
+// NanoSoC Chip Level
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+
+// NanoSoC System Level
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_system/verilog/nanosoc_system.v
+
 // NanoSoC Subsystems
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
@@ -27,8 +33,6 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/expansion/verilog/nanosoc_
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
 
-
-
 // Bus Matrix
 +incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
 -y $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
@@ -60,23 +64,12 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/systable/verilog/nanosoc_regi
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_control/verilog/nanosoc_clkctrl.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_control/verilog/nanosoc_pin_mux.v
 
-// NanoSoC System
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_system/verilog/nanosoc_system.v
-
 // SLCore Files
-$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_integration.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_prmu.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_rstctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0_stclkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/slcorem0_tech/src/verilog/slcorem0.v
+-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_ip.flist
 
 // Debug IP
-$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_adp_control.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_ahb.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_ft1248_control.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/socdebug_tech/controller/verilog/socdebug_usrt_control.v
+-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug_controller_ip.flist
 
 // DMAC IP
-$(SOCLABS_NANOSOC_TECH_DIR)/system/sldma230_tech/src/verilog/sldmac230.v
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/sldma230_tech/src/defines
+-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
 

makefile

@@ -178,7 +178,7 @@ all_vcs : compile_vcs bootrom debugtester
 # ------- XM -----------
 
 # Compile RTL
-compile_xm :
+compile_xm : bootrom
 	@echo ADP_FILE
 	@echo $(ADP_OPTIONS)
 	cd $(SIM_DIR); xmprep  +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top nanosoc_tb | tee compile_xm.log

slcorem0_tech @ 5caa43ff

-Subproject commit bc84f48569a2833a67df85c609bc30b081568785
+Subproject commit 5caa43ffdece4f8634e5f95b6110608f1339bc74

sldma230_tech @ 00b54df5

-Subproject commit 0b63e4325cbc6d0ee1e5eff5620e38e14092c79d
+Subproject commit 00b54df54e90032aba15d470c6470523bca93d59

socdebug_tech @ ee1f184e

-Subproject commit ec5a60835a6ed8b44c084f701411914eeda75a4e
+Subproject commit ee1f184e8a7df3e6e461b7a331e88d0fe9be58cd

xmprep.history

+s1(22Jun2023:09:30:49):  xmprep +overwrite -f /home/dam1n19/accelerator-project/flist/project/system.flist -define ADP_FILE="/home/dam1n19/accelerator-project/nanosoc_tech/testcodes/adp_demo/adp.cmd" +define+CORTEX_M0 +define+USE_TARMAC +define+NANOSOC_EXPANSION_REGION +debug -timescale 1ps/1ps -top nanosoc_tb