Skip to content
Snippets Groups Projects
Commit 1f64822d authored by Daniel Newbrook's avatar Daniel Newbrook
Browse files

V1.2 Fix first time build for CA53 and SMC

parent 45ed5dc9
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
flows/makefile.simulate
+ 4
− 4
View file @ 1f64822d
...@@ -14,16 +14,16 @@ ...@@ -14,16 +14,16 @@
MTI_VC_OPTIONS = +acc MTI_VC_OPTIONS = +acc
MTI_VC_OPTIONS += -suppress 2892 MTI_VC_OPTIONS += -suppress 2892
MTI_VC_OPTIONS += -f $(TBENCH_VC) MTI_VC_OPTIONS += -f $(TBENCH_VC)
MTI_VC_OPTIONS += -sv_lib $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi MTI_VC_OPTIONS += -sv_lib $(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
MTI_RUN_OPTIONS = -voptargs=+acc MTI_RUN_OPTIONS = -voptargs=+acc
MTI_RUN_OPTIONS += -sv_lib $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi MTI_RUN_OPTIONS += -sv_lib $(CORTEX_A53_IP_LOGICAL_DIR)/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
# VCS options # VCS options
VCS_OPTIONS = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug -debug_access+all VCS_OPTIONS = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug -debug_access+all
VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
VCS_VC_OPTIONS = -f $(TBENCH_VC) VCS_VC_OPTIONS = -f $(TBENCH_VC)
VCS_OPTIONS += -sverilog $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi.so VCS_OPTIONS += -sverilog $(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/build_x86_64/lib/ca53_tarmac_dpi.so
CA53_TARMAC_EXECUTABLE = $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_32/bin/ca53_tarmac_decode --plain CA53_TARMAC_EXECUTABLE = $(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/build_x86_32/bin/ca53_tarmac_decode --plain
export CA53_TARMAC_EXECUTABLE export CA53_TARMAC_EXECUTABLE
# XM verilog options # XM verilog options
......
makefile
+ 1
− 0
View file @ 1f64822d
...@@ -81,6 +81,7 @@ FPGA_DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_FPGA.flist ...@@ -81,6 +81,7 @@ FPGA_DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_FPGA.flist
# Make variables visible to target shells # Make variables visible to target shells
export ARM_CORTEX_M0_DIR export ARM_CORTEX_M0_DIR
export ARM_CORSTONE_101_DIR export ARM_CORSTONE_101_DIR
export CORTEX_A53_IP_LOGICAL_DIR
export FLIST_INCLUDES export FLIST_INCLUDES
export AMS export AMS
# Location of Defines File # Location of Defines File
......
megasoc.config
+ 1
− 0
View file @ 1f64822d
...@@ -9,4 +9,5 @@ ...@@ -9,4 +9,5 @@
# !!EDIT this to point to the relevant logical directories of IP # !!EDIT this to point to the relevant logical directories of IP
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
CORTEX_A53_IP_LOGICAL_DIR:=/research/AAA/ip_library/Cortex-A53/MP030-r0p4-52rel2/MP030-BU-50000-r0p4-52rel2/cortexa53/logical
megasoc_tech @ d8016f39
Compare bfadf9d8...d8016f39
Subproject commit bfadf9d8b82c799bf6e56b3a447d53c9527f9fd7 Subproject commit d8016f39f22ca4addea6875a96162404473f57b8
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment