diff --git a/flows/makefile.simulate b/flows/makefile.simulate
index 671e4eefc7524ebe099f564d88cd165caeb28a35..b58be8e0fdd93e7f278367ab6bbe342fe78dab8a 100644
--- a/flows/makefile.simulate
+++ b/flows/makefile.simulate
@@ -14,16 +14,16 @@
 MTI_VC_OPTIONS    = +acc
 MTI_VC_OPTIONS    += -suppress 2892
 MTI_VC_OPTIONS    += -f $(TBENCH_VC) 
-MTI_VC_OPTIONS    += -sv_lib $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
+MTI_VC_OPTIONS    += -sv_lib $(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
 MTI_RUN_OPTIONS   = -voptargs=+acc
-MTI_RUN_OPTIONS   += -sv_lib $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
+MTI_RUN_OPTIONS   += -sv_lib $(CORTEX_A53_IP_LOGICAL_DIR)/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi
 
 # VCS options
 VCS_OPTIONS    =  +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug -debug_access+all 
 VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
 VCS_VC_OPTIONS = -f $(TBENCH_VC) 
-VCS_OPTIONS   += -sverilog $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_64/lib/ca53_tarmac_dpi.so
-CA53_TARMAC_EXECUTABLE = $(SOCLABS_MEGASOC_TECH_DIR)/logical/CortexA53_1/logical/ca53univent/build_x86_32/bin/ca53_tarmac_decode --plain 
+VCS_OPTIONS   += -sverilog $(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/build_x86_64/lib/ca53_tarmac_dpi.so
+CA53_TARMAC_EXECUTABLE = $(CORTEX_A53_IP_LOGICAL_DIR)/ca53univent/build_x86_32/bin/ca53_tarmac_decode --plain 
 export CA53_TARMAC_EXECUTABLE
 
 # XM verilog options
diff --git a/makefile b/makefile
index e4bbcf0be4dac86a2742ad5e836b829e48e6f5a1..fed112424a4e5b94c0f39c168ee0fa459e6af3de 100644
--- a/makefile
+++ b/makefile
@@ -81,6 +81,7 @@ FPGA_DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_FPGA.flist
 # Make variables visible to target shells
 export ARM_CORTEX_M0_DIR
 export ARM_CORSTONE_101_DIR
+export CORTEX_A53_IP_LOGICAL_DIR
 export FLIST_INCLUDES
 export AMS
 # Location of Defines File
diff --git a/megasoc.config b/megasoc.config
index 9e4e773beea50916a14d27039bc76e45d0e0df13..5194e188924d519f1b9c3b0f8cf84632c754a21c 100644
--- a/megasoc.config
+++ b/megasoc.config
@@ -9,4 +9,5 @@
 # !!EDIT this to point to the relevant logical directories of IP
 ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
 ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+CORTEX_A53_IP_LOGICAL_DIR:=/research/AAA/ip_library/Cortex-A53/MP030-r0p4-52rel2/MP030-BU-50000-r0p4-52rel2/cortexa53/logical
 
diff --git a/megasoc_tech b/megasoc_tech
index bfadf9d8b82c799bf6e56b3a447d53c9527f9fd7..d8016f39f22ca4addea6875a96162404473f57b8 160000
--- a/megasoc_tech
+++ b/megasoc_tech
@@ -1 +1 @@
-Subproject commit bfadf9d8b82c799bf6e56b3a447d53c9527f9fd7
+Subproject commit d8016f39f22ca4addea6875a96162404473f57b8