V1.1 bootrom verilog and updating FPGA flows
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- flist/project/top_FPGA.flist 35 additions, 0 deletionsflist/project/top_FPGA.flist
- flows/makefile.fpga 1 addition, 1 deletionflows/makefile.fpga
- flows/makefile.software 9 additions, 4 deletionsflows/makefile.software
- fpga/makefile.targets 7 additions, 7 deletionsfpga/makefile.targets
- fpga/targets/arm_mps3/fpga_timing.xdc 2 additions, 2 deletionsfpga/targets/arm_mps3/fpga_timing.xdc
- fpga/targets/arm_mps3/megasoc_design_wrapper.v 22 additions, 9 deletionsfpga/targets/arm_mps3/megasoc_design_wrapper.v
- fpga/targets/haps_sx/fpga_pinmap.xdc 0 additions, 0 deletionsfpga/targets/haps_sx/fpga_pinmap.xdc
- fpga/targets/haps_sx/fpga_timing.xdc 0 additions, 0 deletionsfpga/targets/haps_sx/fpga_timing.xdc
- fpga/targets/haps_sx/megasoc_design_wrapper.v 77 additions, 0 deletionsfpga/targets/haps_sx/megasoc_design_wrapper.v
- megasoc_chip/pads/glib/logical/megasoc_chip_pads.v 13 additions, 1 deletionmegasoc_chip/pads/glib/logical/megasoc_chip_pads.v
- megasoc_tech 1 addition, 1 deletionmegasoc_tech
- verif/testbench/logical/megasoc_tb.sv 1 addition, 1 deletionverif/testbench/logical/megasoc_tb.sv
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