From 45ed5dc9845ca1201eacbcd3c18823c8b59b3933 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Wed, 20 Nov 2024 16:21:35 +0000
Subject: [PATCH] V1.1 bootrom verilog and updating FPGA flows
---
flist/project/top_FPGA.flist | 35 +++++++++
flows/makefile.fpga | 2 +-
flows/makefile.software | 13 +++-
fpga/makefile.targets | 14 ++--
fpga/targets/arm_mps3/fpga_timing.xdc | 4 +-
.../targets/arm_mps3/megasoc_design_wrapper.v | 31 +++++---
fpga/targets/haps_sx/fpga_pinmap.xdc | 0
fpga/targets/haps_sx/fpga_timing.xdc | 0
fpga/targets/haps_sx/megasoc_design_wrapper.v | 77 +++++++++++++++++++
.../pads/glib/logical/megasoc_chip_pads.v | 14 +++-
megasoc_tech | 2 +-
verif/testbench/logical/megasoc_tb.sv | 2 +-
12 files changed, 168 insertions(+), 26 deletions(-)
create mode 100644 flist/project/top_FPGA.flist
create mode 100644 fpga/targets/haps_sx/fpga_pinmap.xdc
create mode 100644 fpga/targets/haps_sx/fpga_timing.xdc
create mode 100644 fpga/targets/haps_sx/megasoc_design_wrapper.v
diff --git a/flist/project/top_FPGA.flist b/flist/project/top_FPGA.flist
new file mode 100644
index 0000000..f06d6c0
--- /dev/null
+++ b/flist/project/top_FPGA.flist
@@ -0,0 +1,35 @@
+//-----------------------------------------------------------------------------
+// Project Top-level Filelist System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// DESIGN_TOP nanosoc_chip
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+
+// ============= System Filelist =========================
+// - Defines RTL
++incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines
+
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+
+// ============= Arm-IP Specific Filelists =========================
+// - MegaSoC Chip IP
+-f $(SOCLABS_MEGASOC_TECH_DIR)/flist/megasoc_tech_BEHAV.flist
+
+$(SOCLABS_PROJECT_DIR)/megasoc_chip/chip/logical/megasoc_chip.v
+
+$(SOCLABS_PROJECT_DIR)/megasoc_system/logical/megasoc_system.v
+
+
diff --git a/flows/makefile.fpga b/flows/makefile.fpga
index cdb86c1..18ff3d2 100644
--- a/flows/makefile.fpga
+++ b/flows/makefile.fpga
@@ -51,7 +51,7 @@ PINMAP_FILE ?= $(TARGET_DIR)/fpga_pinmap.xdc
flist_tcl_megasoc:
@mkdir -p $(TCL_FLIST_DIR)
@(cd $(TCL_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_MEGASOC_DIR)/src ;)
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(FPGA_DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_MEGASOC_DIR)/src ;)
# Environment Variables for Packaging NanoSoC
diff --git a/flows/makefile.software b/flows/makefile.software
index 14599b6..6a1f9a2 100644
--- a/flows/makefile.software
+++ b/flows/makefile.software
@@ -24,7 +24,7 @@ SW_MAKE_OPTIONS = CPU_PRODUCT=CORTEX_M0 TOOL_CHAIN=$(TOOL_CHAIN)
# Bootrom Parameters:
# Boot Loader image
BOOTLOADER ?= bootloader
-BOOTROM_ADDRW ?= 8
+BOOTROM_ADDRW ?= 14
BOOTROM_HEX ?= $(SOCLABS_MEGASOC_TECH_DIR)/software/src/bootloader/$(BOOTLOADER).hex
BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom
@@ -38,7 +38,7 @@ code : testcode bootrom
# Compile bootloader
# Note : The use of ls after compile allows the computing server to sync up
bootrom:
- @cd $(TESTCODES_DIR)/$(BOOTLOADER) ;\
+ @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ;\
echo CD $(TESTCODES_DIR)/$(BOOTLOADER) ;\
$(MAKE) boot_build $(SW_MAKE_OPTIONS) ;\
echo Bootrom Compile done ;\
@@ -52,9 +52,14 @@ bootrom:
if [ ! -e $(TESTCODES_DIR)/../build/$(BOOTLOADER)/bootloader.hex ] ; then \
echo Problem reading hex file ;\
exit 1; \
- else \
- cp $(TESTCODES_DIR)/../build/$(BOOTLOADER)/bootloader.hex $(SIM_DIR)/bootloader.hex ;\
+ # else \
+ # cp $(TESTCODES_DIR)/../build/$(BOOTLOADER)/bootloader.hex $(SIM_DIR)/bootloader.hex ;\
fi ;\
+ mkdir -p $(BOOTROM_BUILD_DIR)/verilog/ ;\
+ mkdir -p $(BOOTROM_BUILD_DIR)/bintxt/ ;\
+ python3 bootrom_gen.py -a $(BOOTROM_ADDRW) -i $(TESTCODES_DIR)/../build/$(BOOTLOADER)/bootloader.hex/SEC_ROM_BOOT_IMG -v $(BOOTROM_BUILD_DIR)/verilog/bootrom.v -b $(BOOTROM_BUILD_DIR)/bintxt/bootrom.bintxt )
+ mkdir -p $(SIM_TOP_DIR)/bootloader
+
# Compile test code
# Note : The use of ls after compile allows the computing server to sync up
diff --git a/fpga/makefile.targets b/fpga/makefile.targets
index 99d49be..192afed 100644
--- a/fpga/makefile.targets
+++ b/fpga/makefile.targets
@@ -14,12 +14,12 @@ ifeq ($(FPGA),mps3)
XILINX_PART := xcku115-flvb1760-1-c
BOARD_NAME := arm_mps3
PLATFORM := bare
-else ifeq ($(FPGA),zcu104)
- XILINX_PART := xczu7ev-ffvc1156-2-e
- BOARD_NAME := pynq_zcu104
- PLATFORM := pynq
-else # Default to MPS3
- XILINX_PART := xcku115-flvb1760-1-c
- BOARD_NAME := arm_mps3
+else ifeq ($(FPGA),haps_sx)
+ XILINX_PART := xcvu19p-fsva3824-2-e
+ BOARD_NAME := haps_sx
+ PLATFORM := bare
+else # Default to HAPS
+ XILINX_PART := xcvu19p-fsva3824-2-e
+ BOARD_NAME := haps_sx
PLATFORM := bare
endif
diff --git a/fpga/targets/arm_mps3/fpga_timing.xdc b/fpga/targets/arm_mps3/fpga_timing.xdc
index 23677a7..32592c5 100644
--- a/fpga/targets/arm_mps3/fpga_timing.xdc
+++ b/fpga/targets/arm_mps3/fpga_timing.xdc
@@ -4,8 +4,8 @@
## ##
##################################################################################
-create_clock -period 100.000 -name CS_TCK -waveform {0.000 50.000} [get_ports CS_TCK]
-create_clock -period 20.000 -name {OSCCLK[1]} -waveform {0.000 10.000} [get_ports {OSCCLK[1]}]
+create_clock -period 1000.000 -name CS_TCK -waveform {0.000 500.000} [get_ports CS_TCK]
+create_clock -period 200.000 -name {OSCCLK[1]} -waveform {0.000 100.000} [get_ports {OSCCLK[1]}]
set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports {UART_RX_F[*]}]
set_input_delay -clock [get_clocks {OSCCLK[1]}] -max -add_delay 15.000 [get_ports {UART_RX_F[*]}]
set_input_delay -clock [get_clocks {OSCCLK[1]}] -min -add_delay 11.000 [get_ports CB_nRST]
diff --git a/fpga/targets/arm_mps3/megasoc_design_wrapper.v b/fpga/targets/arm_mps3/megasoc_design_wrapper.v
index dbcafe4..fee9c9a 100644
--- a/fpga/targets/arm_mps3/megasoc_design_wrapper.v
+++ b/fpga/targets/arm_mps3/megasoc_design_wrapper.v
@@ -266,8 +266,6 @@ BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
// Minimum design tie-offs
assign MMB_IDCLK = 1'b0;
assign EMMC_CLK = 1'b0;
- assign QSPI_nCS = 1'b1;
- assign QSPI_SCLK = 1'b0;
assign IOFPGA_SYSWDT = 1'b0;
assign WDOG_RREQ = 1'b0;
assign SMBM_nWAIT = 1'b1;
@@ -293,16 +291,30 @@ BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
assign CS_TMS = (SWDOEN_0==1'b1) ? SWDO_0 : 1'bz;
assign SWDITMS_0 = CS_TMS;
+
+ wire [3:0] QSPI_IO_e;
+ wire [3:0] QSPI_IO_i;
+ wire [3:0] QSPI_IO_o;
+
+ assign QSPI_D0 = (QSPI_IO_e[0]==1'b1)? QSPI_IO_o[0]:1'bz;
+ assign QSPI_D1 = (QSPI_IO_e[1]==1'b1)? QSPI_IO_o[1]:1'bz;
+ assign QSPI_D2 = (QSPI_IO_e[2]==1'b1)? QSPI_IO_o[2]:1'bz;
+ assign QSPI_D3 = (QSPI_IO_e[3]==1'b1)? QSPI_IO_o[3]:1'bz;
+
+ assign QSPI_IO_i[0] = QSPI_D0;
+ assign QSPI_IO_i[1] = QSPI_D1;
+ assign QSPI_IO_i[2] = QSPI_D2;
+ assign QSPI_IO_i[3] = QSPI_D3;
megasoc_design megasoc_design_i
(.CLK_IN_0(ACLK),
.nRESET_0(nRST),
- .QSPI_IO_e_0(),
- .QSPI_IO_i_0(),
- .QSPI_IO_o_0(),
- .QSPI_SCLK_0(),
- .QSPI_nCS_0(),
+ .QSPI_IO_e_0(QSPI_IO_e),
+ .QSPI_IO_i_0(QSPI_IO_i),
+ .QSPI_IO_o_0(QSPI_IO_o),
+ .QSPI_SCLK_0(QSPI_SCLK),
+ .QSPI_nCS_0(QSPI_nCS),
.UARTRXD_0(1'b0),
.UARTTXD_0(UART_TX_F[1]),
@@ -311,8 +323,9 @@ BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
.SWDITMS_0(SWDITMS_0),
.SWDOEN_0(SWDOEN_0),
.SWDO_0(SWDO_0),
- .TDI_0(),
- .TDO_0(),
+ .TDI_0(CS_TDI),
+ .TDO_0(CS_TDO),
.nTDOEN_0(),
.nTRST_0(CS_nTRST));
+
endmodule
diff --git a/fpga/targets/haps_sx/fpga_pinmap.xdc b/fpga/targets/haps_sx/fpga_pinmap.xdc
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/targets/haps_sx/fpga_timing.xdc b/fpga/targets/haps_sx/fpga_timing.xdc
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/targets/haps_sx/megasoc_design_wrapper.v b/fpga/targets/haps_sx/megasoc_design_wrapper.v
new file mode 100644
index 0000000..e73f249
--- /dev/null
+++ b/fpga/targets/haps_sx/megasoc_design_wrapper.v
@@ -0,0 +1,77 @@
+//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+//Date : Fri Nov 15 14:43:17 2024
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
+//Command : generate_target megasoc_design_wrapper.bd
+//Design : megasoc_design_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module megasoc_design_wrapper
+ (
+ inout wire QSPI_D0,
+ inout wire QSPI_D1,
+ inout wire QSPI_D2,
+ inout wire QSPI_D3,
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+
+ input wire CS_TDI,
+ output wire CS_TDO, // SWV / JTAG TDO
+ inout wire CS_TMS, // SWD I/O / JTAG TMS
+ input wire CS_TCK, // SWD Clk / JTAG TCK
+ input wire CS_nSRST,
+ input wire CS_nTRST,
+ input wire CS_nDET
+
+
+
+ );
+wire SWDITMS_0;
+wire SWDOEN_0;
+wire SWDO_0;
+
+assign CS_TMS = (SWDOEN_0==1'b1) ? SWDO_0 : 1'bz;
+assign SWDITMS_0 = CS_TMS;
+
+wire [3:0] QSPI_IO_e;
+wire [3:0] QSPI_IO_i;
+wire [3:0] QSPI_IO_o;
+
+assign QSPI_D0 = (QSPI_IO_e[0]==1'b1)? QSPI_IO_o[0]:1'bz;
+assign QSPI_D1 = (QSPI_IO_e[1]==1'b1)? QSPI_IO_o[1]:1'bz;
+assign QSPI_D2 = (QSPI_IO_e[2]==1'b1)? QSPI_IO_o[2]:1'bz;
+assign QSPI_D3 = (QSPI_IO_e[3]==1'b1)? QSPI_IO_o[3]:1'bz;
+
+assign QSPI_IO_i[0] = QSPI_D0;
+assign QSPI_IO_i[1] = QSPI_D1;
+assign QSPI_IO_i[2] = QSPI_D2;
+assign QSPI_IO_i[3] = QSPI_D3;
+
+ megasoc_design megasoc_design_i
+ (.CLK_IN_0(CLK_IN_0),
+ .nRESET_0(nRESET_0),
+
+ .QSPI_IO_e_0(QSPI_IO_e),
+ .QSPI_IO_i_0(QSPI_IO_i),
+ .QSPI_IO_o_0(QSPI_IO_o),
+ .QSPI_SCLK_0(QSPI_SCLK),
+ .QSPI_nCS_0(QSPI_nCS),
+
+ .SWCLKTCK_0(CS_TCK),
+ .SWDITMS_0(SWDITMS_0),
+ .SWDOEN_0(SWDOEN_0),
+ .SWDO_0(SWDO_0),
+ .TDI_0(CS_TDI),
+ .TDO_0(CS_TDO),
+
+ .UARTRXD_0(),
+ .UARTTXD_0(),
+ .UARTTXEN_0(),
+
+ .nTDOEN_0(nTDOEN_0),
+ .nTRST_0(CS_nTRST));
+endmodule
diff --git a/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v b/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
index ccd5c19..6dd410f 100644
--- a/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
+++ b/megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
@@ -70,6 +70,7 @@ assign QSPI_IO_i[1] = QSPI_IO[1];
assign QSPI_IO_i[2] = QSPI_IO[2];
assign QSPI_IO_i[3] = QSPI_IO[3];
+assign REF_CLK_XTAL2 = REF_CLK_XTAL1;
megasoc_chip u_megasoc_chip(
.CLK_IN(REF_CLK_XTAL1),
@@ -78,7 +79,18 @@ megasoc_chip u_megasoc_chip(
.QSPI_nCS(QSPI_nCS),
.QSPI_IO_o(QSPI_IO_o),
.QSPI_IO_i(QSPI_IO_i),
- .QSPI_IO_e(QSPI_IO_e)
+ .QSPI_IO_e(QSPI_IO_e),
+ .UARTRXD(),
+ .UARTTXD(),
+ .UARTTXEN(),
+ .nTRST(),
+ .SWCLKTCK(),
+ .SWDITMS(),
+ .TDI(),
+ .TDO(),
+ .nTDOEN(),
+ .SWDO(),
+ .SWDOEN()
);
diff --git a/megasoc_tech b/megasoc_tech
index 1e2cc64..bfadf9d 160000
--- a/megasoc_tech
+++ b/megasoc_tech
@@ -1 +1 @@
-Subproject commit 1e2cc64e3dba67ec4d5f7ddd7f4d4fe0c77fd455
+Subproject commit bfadf9d8b82c799bf6e56b3a447d53c9527f9fd7
diff --git a/verif/testbench/logical/megasoc_tb.sv b/verif/testbench/logical/megasoc_tb.sv
index 2f99bd8..cb592f7 100644
--- a/verif/testbench/logical/megasoc_tb.sv
+++ b/verif/testbench/logical/megasoc_tb.sv
@@ -34,7 +34,7 @@ megasoc_clkreset u_megasoc_clkreset(
`define MEGASOC_SRAM `MEGASOC_TECH_WRAPPER.u_SRAM_wrapper.u_SRAM
initial begin
- $readmemh("bootloader.hex", `MEGASOC_ROM.mem, 32'h0000_0000);
+ //$readmemh("bootloader.hex", `MEGASOC_ROM.mem, 32'h0000_0000);
$readmemh("app_ram.v8-a.hex", `MEGASOC_SRAM.mem, 32'h0000_0000);
#1 $readmemh("app_flash.v8-a.hex", FLASH.I0.memory);
--
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