Reinstate redundant timescale

pads/verilog/PAD_INOUT8MA_NOE.v

@@ -10,6 +10,8 @@
 // Copyright  2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
+`timescale 1ns/1ps
+
 module PAD_INOUT8MA_NOE (
    // Inouts
    PAD,