From 53dca95d66a93333a7e6e8bbbda0696a348da0b5 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Tue, 16 May 2023 16:21:15 +0100
Subject: [PATCH] Reinstate redundant timescale
---
pads/verilog/PAD_INOUT8MA_NOE.v | 2 ++
1 file changed, 2 insertions(+)
diff --git a/pads/verilog/PAD_INOUT8MA_NOE.v b/pads/verilog/PAD_INOUT8MA_NOE.v
index 42123e8..4e8b749 100644
--- a/pads/verilog/PAD_INOUT8MA_NOE.v
+++ b/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -10,6 +10,8 @@
// Copyright � 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
+`timescale 1ns/1ps
+
module PAD_INOUT8MA_NOE (
// Inouts
PAD,
--
GitLab