diff --git a/pads/verilog/PAD_INOUT8MA_NOE.v b/pads/verilog/PAD_INOUT8MA_NOE.v
index 42123e8d7ac8f9b825dadceaba8b8019ea0acf0e..4e8b749562ddc8ec5346c1716a4fc2e2bc41e195 100644
--- a/pads/verilog/PAD_INOUT8MA_NOE.v
+++ b/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -10,6 +10,8 @@
 // Copyright � 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
+`timescale 1ns/1ps
+
 module PAD_INOUT8MA_NOE (
    // Inouts
    PAD,