repair SWD IO mapping, and add clock port waiver to SWDCLK on PMOD interface (f4b36d2b) · Commits · SoCLabs / Cortex M0 Baseline Tech · GitLab

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f4b36d2b

Commit f4b36d2b authored 2 years ago by dwf1m12

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repair SWD IO mapping, and add clock port waiver to SWDCLK on PMOD interface

parent 3af73ae9

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc 1 addition, 0 deletions

...ortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc 2 additions, 0 deletions

...cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v 8 additions, 0 deletions

...clabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v

with 11 additions and 0 deletions

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