From f4b36d2b97315cd24428a1b831d5ef4527669603 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Sat, 3 Sep 2022 09:55:14 +0100
Subject: [PATCH] repair SWD IO mapping, and add clock port waiver to SWDCLK on
PMOD interface
---
.../fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc | 1 +
.../fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc | 2 ++
.../systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v | 8 ++++++++
3 files changed, 11 insertions(+)
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
index ab99a9c..5599cd2 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
@@ -30,3 +30,4 @@ set_property PULLUP true [get_ports PMOD0_5]
set_property PULLUP true [get_ports PMOD0_6]
set_property PULLUP true [get_ports PMOD0_7]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
index 078c270..4a635dd 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
@@ -930,6 +930,8 @@ set_property PULLUP true [get_ports PMOD0_5]
set_property PULLUP true [get_ports PMOD0_6]
set_property PULLUP true [get_ports PMOD0_7]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
index 4af8e69..33e1385 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
@@ -1032,12 +1032,20 @@ cmsdk_ahb_ram
// I/O port pin muxing and tristate
//----------------------------------------
+
assign i_swclktck = swdclk_in;
assign i_swditms = swdio_in;
assign swdio_out = i_swdo;
assign swdio_out_en = i_swdoen;
assign swdio_out_nen = !i_swdoen;
+ assign swdclk_in = swdclk_i;
+ assign swdio_in = swdio_i;
+
+ assign swdio_o = swdio_out;
+ assign swdio_e = swdio_out_en;
+ assign swdio_z = swdio_out_nen;
+
cmsdk_mcu_pin_mux
u_pin_mux (
// UART
--
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