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Commit a32c8bff authored by dwf1m12's avatar dwf1m12
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bootrom generation and prep for IO pads

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom.v 0 → 100644
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module ahb_bootrom #(
// Parameters
parameter AW = 10 // Address width
)
(
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Device select
input wire [AW-1:0] HADDR, // Address
input wire [1:0] HTRANS, // Transfer control
input wire [2:0] HSIZE, // Transfer size
input wire HWRITE, // Write control
input wire [31:0] HWDATA, // Write data - not used
input wire HREADY, // Transfer phase done
output wire HREADYOUT, // Device ready
output wire [31:0] HRDATA, // Read data output
output wire HRESP // Device response (always OKAY)
);
bootrom u_bootrom (
.CLK (HCLK),
.EN (HSEL & HTRANS[1] & HREADY & !HWRITE),
.ADDR (HADDR[AW-1:2]),
.RDATA (HRDATA)
);
assign HREADYOUT = 1'b1;
assign HRESP = 1'b0;
endmodule
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom__mangled.v 0 → 100644
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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v 0 → 100644
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module bootrom (
input wire CLK,
input wire EN,
input wire [9:2] ADDR,
output reg [31:0] RDATA );
reg [9:2] addr_r;
always @(posedge CLK) if (EN) addr_r <= ADDR;
always @(addr_r) case(addr_r[9:2])
8'h000 : RDATA <= 32'h20000368; // 0x0000
8'h001 : RDATA <= 32'h010002d1; // 0x0004
8'h002 : RDATA <= 32'h010002d9; // 0x0008
8'h003 : RDATA <= 32'h010002db; // 0x000c
8'h004 : RDATA <= 32'h00000000; // 0x0010
8'h005 : RDATA <= 32'h00000000; // 0x0014
8'h006 : RDATA <= 32'h00000000; // 0x0018
8'h007 : RDATA <= 32'h00000000; // 0x001c
8'h008 : RDATA <= 32'h00000000; // 0x0020
8'h009 : RDATA <= 32'h00000000; // 0x0024
8'h00a : RDATA <= 32'h00000000; // 0x0028
8'h00b : RDATA <= 32'h010002dd; // 0x002c
8'h00c : RDATA <= 32'h00000000; // 0x0030
8'h00d : RDATA <= 32'h00000000; // 0x0034
8'h00e : RDATA <= 32'h010002df; // 0x0038
8'h00f : RDATA <= 32'h010002e1; // 0x003c
8'h010 : RDATA <= 32'h010002e3; // 0x0040
8'h011 : RDATA <= 32'h010002e3; // 0x0044
8'h012 : RDATA <= 32'h010002e3; // 0x0048
8'h013 : RDATA <= 32'h010002e3; // 0x004c
8'h014 : RDATA <= 32'h010002e3; // 0x0050
8'h015 : RDATA <= 32'h010002e3; // 0x0054
8'h016 : RDATA <= 32'h010002e3; // 0x0058
8'h017 : RDATA <= 32'h010002e3; // 0x005c
8'h018 : RDATA <= 32'h010002e3; // 0x0060
8'h019 : RDATA <= 32'h010002e3; // 0x0064
8'h01a : RDATA <= 32'h010002e3; // 0x0068
8'h01b : RDATA <= 32'h00000000; // 0x006c
8'h01c : RDATA <= 32'h010002e3; // 0x0070
8'h01d : RDATA <= 32'h010002e3; // 0x0074
8'h01e : RDATA <= 32'h010002e3; // 0x0078
8'h01f : RDATA <= 32'h010002e3; // 0x007c
8'h020 : RDATA <= 32'h010002e3; // 0x0080
8'h021 : RDATA <= 32'h010002e3; // 0x0084
8'h022 : RDATA <= 32'h010002e3; // 0x0088
8'h023 : RDATA <= 32'h010002e3; // 0x008c
8'h024 : RDATA <= 32'h010002e3; // 0x0090
8'h025 : RDATA <= 32'h010002e3; // 0x0094
8'h026 : RDATA <= 32'h010002e3; // 0x0098
8'h027 : RDATA <= 32'h010002e3; // 0x009c
8'h028 : RDATA <= 32'h010002e3; // 0x00a0
8'h029 : RDATA <= 32'h010002e3; // 0x00a4
8'h02a : RDATA <= 32'h010002e3; // 0x00a8
8'h02b : RDATA <= 32'h010002e3; // 0x00ac
8'h02c : RDATA <= 32'h010002e3; // 0x00b0
8'h02d : RDATA <= 32'h010002e3; // 0x00b4
8'h02e : RDATA <= 32'h010002e3; // 0x00b8
8'h02f : RDATA <= 32'h010002e3; // 0x00bc
8'h030 : RDATA <= 32'hf802f000; // 0x00c0
8'h031 : RDATA <= 32'hf83ef000; // 0x00c4
8'h032 : RDATA <= 32'hc830a00c; // 0x00c8
8'h033 : RDATA <= 32'h18243808; // 0x00cc
8'h034 : RDATA <= 32'h46a2182d; // 0x00d0
8'h035 : RDATA <= 32'h46ab1e67; // 0x00d4
8'h036 : RDATA <= 32'h465d4654; // 0x00d8
8'h037 : RDATA <= 32'hd10142ac; // 0x00dc
8'h038 : RDATA <= 32'hf830f000; // 0x00e0
8'h039 : RDATA <= 32'h3e0f467e; // 0x00e4
8'h03a : RDATA <= 32'h46b6cc0f; // 0x00e8
8'h03b : RDATA <= 32'h42332601; // 0x00ec
8'h03c : RDATA <= 32'h1afbd000; // 0x00f0
8'h03d : RDATA <= 32'h46ab46a2; // 0x00f4
8'h03e : RDATA <= 32'h47184333; // 0x00f8
8'h03f : RDATA <= 32'h00000278; // 0x00fc
8'h040 : RDATA <= 32'h00000298; // 0x0100
8'h041 : RDATA <= 32'hd3023a10; // 0x0104
8'h042 : RDATA <= 32'hc178c878; // 0x0108
8'h043 : RDATA <= 32'h0752d8fa; // 0x010c
8'h044 : RDATA <= 32'hc830d301; // 0x0110
8'h045 : RDATA <= 32'hd501c130; // 0x0114
8'h046 : RDATA <= 32'h600c6804; // 0x0118
8'h047 : RDATA <= 32'h00004770; // 0x011c
8'h048 : RDATA <= 32'h24002300; // 0x0120
8'h049 : RDATA <= 32'h26002500; // 0x0124
8'h04a : RDATA <= 32'hd3013a10; // 0x0128
8'h04b : RDATA <= 32'hd8fbc178; // 0x012c
8'h04c : RDATA <= 32'hd3000752; // 0x0130
8'h04d : RDATA <= 32'hd500c130; // 0x0134
8'h04e : RDATA <= 32'h4770600b; // 0x0138
8'h04f : RDATA <= 32'hbd1fb51f; // 0x013c
8'h050 : RDATA <= 32'hbd10b510; // 0x0140
8'h051 : RDATA <= 32'hf8e3f000; // 0x0144
8'h052 : RDATA <= 32'hf7ff4611; // 0x0148
8'h053 : RDATA <= 32'hf000fff7; // 0x014c
8'h054 : RDATA <= 32'hf000f84a; // 0x0150
8'h055 : RDATA <= 32'hb403f8fb; // 0x0154
8'h056 : RDATA <= 32'hfff2f7ff; // 0x0158
8'h057 : RDATA <= 32'hf000bc03; // 0x015c
8'h058 : RDATA <= 32'h0000f901; // 0x0160
8'h059 : RDATA <= 32'h68012000; // 0x0164
8'h05a : RDATA <= 32'h6841468d; // 0x0168
8'h05b : RDATA <= 32'h00004708; // 0x016c
8'h05c : RDATA <= 32'h2110483c; // 0x0170
8'h05d : RDATA <= 32'h21416101; // 0x0174
8'h05e : RDATA <= 32'h493b6081; // 0x0178
8'h05f : RDATA <= 32'h61882020; // 0x017c
8'h060 : RDATA <= 32'h49384770; // 0x0180
8'h061 : RDATA <= 32'h07d2684a; // 0x0184
8'h062 : RDATA <= 32'h6008d1fc; // 0x0188
8'h063 : RDATA <= 32'h49354770; // 0x018c
8'h064 : RDATA <= 32'h2b007803; // 0x0190
8'h065 : RDATA <= 32'h684ad006; // 0x0194
8'h066 : RDATA <= 32'hd1fc07d2; // 0x0198
8'h067 : RDATA <= 32'h1c40600b; // 0x019c
8'h068 : RDATA <= 32'hd1f52b00; // 0x01a0
8'h069 : RDATA <= 32'hb5104770; // 0x01a4
8'h06a : RDATA <= 32'h68014830; // 0x01a8
8'h06b : RDATA <= 32'hd0082900; // 0x01ac
8'h06c : RDATA <= 32'h60012100; // 0x01b0
8'h06d : RDATA <= 32'h8f4ff3bf; // 0x01b4
8'h06e : RDATA <= 32'h8f6ff3bf; // 0x01b8
8'h06f : RDATA <= 32'hffd2f7ff; // 0x01bc
8'h070 : RDATA <= 32'h4828bd10; // 0x01c0
8'h071 : RDATA <= 32'h781aa32a; // 0x01c4
8'h072 : RDATA <= 32'hd0062a00; // 0x01c8
8'h073 : RDATA <= 32'h07c96841; // 0x01cc
8'h074 : RDATA <= 32'h6002d1fc; // 0x01d0
8'h075 : RDATA <= 32'h2a001c5b; // 0x01d4
8'h076 : RDATA <= 32'h2104d1f5; // 0x01d8
8'h077 : RDATA <= 32'h07d26842; // 0x01dc
8'h078 : RDATA <= 32'h6001d1fc; // 0x01e0
8'h079 : RDATA <= 32'hb510e7fe; // 0x01e4
8'h07a : RDATA <= 32'h2110481e; // 0x01e8
8'h07b : RDATA <= 32'h21416101; // 0x01ec
8'h07c : RDATA <= 32'h4a1d6081; // 0x01f0
8'h07d : RDATA <= 32'h61912120; // 0x01f4
8'h07e : RDATA <= 32'h781aa326; // 0x01f8
8'h07f : RDATA <= 32'hd0062a00; // 0x01fc
8'h080 : RDATA <= 32'h07c96841; // 0x0200
8'h081 : RDATA <= 32'h6002d1fc; // 0x0204
8'h082 : RDATA <= 32'h2a001c5b; // 0x0208
8'h083 : RDATA <= 32'ha326d1f5; // 0x020c
8'h084 : RDATA <= 32'h2a00781a; // 0x0210
8'h085 : RDATA <= 32'h6841d006; // 0x0214
8'h086 : RDATA <= 32'hd1fc07c9; // 0x0218
8'h087 : RDATA <= 32'h1c5b6002; // 0x021c
8'h088 : RDATA <= 32'hd1f52a00; // 0x0220
8'h089 : RDATA <= 32'h680a4911; // 0x0224
8'h08a : RDATA <= 32'hd0092a00; // 0x0228
8'h08b : RDATA <= 32'h60082000; // 0x022c
8'h08c : RDATA <= 32'h8f4ff3bf; // 0x0230
8'h08d : RDATA <= 32'h8f6ff3bf; // 0x0234
8'h08e : RDATA <= 32'hff94f7ff; // 0x0238
8'h08f : RDATA <= 32'hbd102000; // 0x023c
8'h090 : RDATA <= 32'h781aa30b; // 0x0240
8'h091 : RDATA <= 32'hd0062a00; // 0x0244
8'h092 : RDATA <= 32'h07c96841; // 0x0248
8'h093 : RDATA <= 32'h6002d1fc; // 0x024c
8'h094 : RDATA <= 32'h2a001c5b; // 0x0250
8'h095 : RDATA <= 32'h2204d1f5; // 0x0254
8'h096 : RDATA <= 32'h07c96841; // 0x0258
8'h097 : RDATA <= 32'h6002d1fc; // 0x025c
8'h098 : RDATA <= 32'h0000e7fe; // 0x0260
8'h099 : RDATA <= 32'h40006000; // 0x0264
8'h09a : RDATA <= 32'h40011000; // 0x0268
8'h09b : RDATA <= 32'h4001f000; // 0x026c
8'h09c : RDATA <= 32'h7245202d; // 0x0270
8'h09d : RDATA <= 32'h3a726f72; // 0x0274
8'h09e : RDATA <= 32'h4d455220; // 0x0278
8'h09f : RDATA <= 32'h69205041; // 0x027c
8'h0a0 : RDATA <= 32'h6c612073; // 0x0280
8'h0a1 : RDATA <= 32'h64616572; // 0x0284
8'h0a2 : RDATA <= 32'h6c632079; // 0x0288
8'h0a3 : RDATA <= 32'h0a726165; // 0x028c
8'h0a4 : RDATA <= 32'h00000000; // 0x0290
8'h0a5 : RDATA <= 32'h534d430a; // 0x0294
8'h0a6 : RDATA <= 32'h42204b44; // 0x0298
8'h0a7 : RDATA <= 32'h20746f6f; // 0x029c
8'h0a8 : RDATA <= 32'h64616f4c; // 0x02a0
8'h0a9 : RDATA <= 32'h000a7265; // 0x02a4
8'h0aa : RDATA <= 32'h6f6c202d; // 0x02a8
8'h0ab : RDATA <= 32'h66206461; // 0x02ac
8'h0ac : RDATA <= 32'h6873616c; // 0x02b0
8'h0ad : RDATA <= 32'h0000000a; // 0x02b4
8'h0ae : RDATA <= 32'h48034904; // 0x02b8
8'h0af : RDATA <= 32'h47706008; // 0x02bc
8'h0b0 : RDATA <= 32'h48014902; // 0x02c0
8'h0b1 : RDATA <= 32'h47706008; // 0x02c4
8'h0b2 : RDATA <= 32'h05f5e100; // 0x02c8
8'h0b3 : RDATA <= 32'h20000000; // 0x02cc
8'h0b4 : RDATA <= 32'h47804807; // 0x02d0
8'h0b5 : RDATA <= 32'h47004807; // 0x02d4
8'h0b6 : RDATA <= 32'he7fee7fe; // 0x02d8
8'h0b7 : RDATA <= 32'he7fee7fe; // 0x02dc
8'h0b8 : RDATA <= 32'he7fee7fe; // 0x02e0
8'h0b9 : RDATA <= 32'h49054804; // 0x02e4
8'h0ba : RDATA <= 32'h4b064a05; // 0x02e8
8'h0bb : RDATA <= 32'h00004770; // 0x02ec
8'h0bc : RDATA <= 32'h010002c1; // 0x02f0
8'h0bd : RDATA <= 32'h010000c1; // 0x02f4
8'h0be : RDATA <= 32'h20000068; // 0x02f8
8'h0bf : RDATA <= 32'h20000368; // 0x02fc
8'h0c0 : RDATA <= 32'h20000168; // 0x0300
8'h0c1 : RDATA <= 32'h20000168; // 0x0304
8'h0c2 : RDATA <= 32'h47704770; // 0x0308
8'h0c3 : RDATA <= 32'h46754770; // 0x030c
8'h0c4 : RDATA <= 32'hf824f000; // 0x0310
8'h0c5 : RDATA <= 32'h000546ae; // 0x0314
8'h0c6 : RDATA <= 32'h46534669; // 0x0318
8'h0c7 : RDATA <= 32'h00c008c0; // 0x031c
8'h0c8 : RDATA <= 32'hb0184685; // 0x0320
8'h0c9 : RDATA <= 32'hf7ffb520; // 0x0324
8'h0ca : RDATA <= 32'hbc60ffdd; // 0x0328
8'h0cb : RDATA <= 32'h08492700; // 0x032c
8'h0cc : RDATA <= 32'h260046b6; // 0x0330
8'h0cd : RDATA <= 32'hc5c0c5c0; // 0x0334
8'h0ce : RDATA <= 32'hc5c0c5c0; // 0x0338
8'h0cf : RDATA <= 32'hc5c0c5c0; // 0x033c
8'h0d0 : RDATA <= 32'hc5c0c5c0; // 0x0340
8'h0d1 : RDATA <= 32'h00493d40; // 0x0344
8'h0d2 : RDATA <= 32'h4770468d; // 0x0348
8'h0d3 : RDATA <= 32'h4604b510; // 0x034c
8'h0d4 : RDATA <= 32'h46c046c0; // 0x0350
8'h0d5 : RDATA <= 32'hf7ff4620; // 0x0354
8'h0d6 : RDATA <= 32'hbd10fefe; // 0x0358
8'h0d7 : RDATA <= 32'h47704800; // 0x035c
8'h0d8 : RDATA <= 32'h20000004; // 0x0360
8'h0d9 : RDATA <= 32'h20184901; // 0x0364
8'h0da : RDATA <= 32'he7febeab; // 0x0368
8'h0db : RDATA <= 32'h00020026; // 0x036c
8'h0dc : RDATA <= 32'h00004770; // 0x0370
8'h0dd : RDATA <= 32'h01000394; // 0x0374
8'h0de : RDATA <= 32'h20000000; // 0x0378
8'h0df : RDATA <= 32'h00000004; // 0x037c
8'h0e0 : RDATA <= 32'h01000104; // 0x0380
8'h0e1 : RDATA <= 32'h01000398; // 0x0384
8'h0e2 : RDATA <= 32'h20000004; // 0x0388
8'h0e3 : RDATA <= 32'h00000364; // 0x038c
8'h0e4 : RDATA <= 32'h01000120; // 0x0390
8'h0e5 : RDATA <= 32'h05f5e100; // 0x0394
8'h0e6 : RDATA <= 32'h00000000; // 0x0398
8'h0e7 : RDATA <= 32'h00000000; // 0x039c
8'h0e8 : RDATA <= 32'h00000000; // 0x03a0
8'h0e9 : RDATA <= 32'h00000000; // 0x03a4
8'h0ea : RDATA <= 32'h00000000; // 0x03a8
8'h0eb : RDATA <= 32'h00000000; // 0x03ac
8'h0ec : RDATA <= 32'h00000000; // 0x03b0
8'h0ed : RDATA <= 32'h00000000; // 0x03b4
8'h0ee : RDATA <= 32'h00000000; // 0x03b8
8'h0ef : RDATA <= 32'h00000000; // 0x03bc
8'h0f0 : RDATA <= 32'h00000000; // 0x03c0
8'h0f1 : RDATA <= 32'h00000000; // 0x03c4
8'h0f2 : RDATA <= 32'h00000000; // 0x03c8
8'h0f3 : RDATA <= 32'h00000000; // 0x03cc
8'h0f4 : RDATA <= 32'h00000000; // 0x03d0
8'h0f5 : RDATA <= 32'h00000000; // 0x03d4
8'h0f6 : RDATA <= 32'h00000000; // 0x03d8
8'h0f7 : RDATA <= 32'h00000000; // 0x03dc
8'h0f8 : RDATA <= 32'h00000000; // 0x03e0
8'h0f9 : RDATA <= 32'h00000000; // 0x03e4
8'h0fa : RDATA <= 32'h00000000; // 0x03e8
8'h0fb : RDATA <= 32'h00000000; // 0x03ec
8'h0fc : RDATA <= 32'h00000000; // 0x03f0
8'h0fd : RDATA <= 32'h00000000; // 0x03f4
8'h0fe : RDATA <= 32'h00000000; // 0x03f8
8'h0ff : RDATA <= 32'h00000000; // 0x03fc
default : RDATA <=32'h0;
endcase
endmodule
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GLIB/mem/verilog/SROM_Ax32.v 0 → 100644
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//-----------------------------------------------------------------------------
//
// Synthesizable byte-write addressible R/W (random-access) memory
//
// Synchronous data write, flow-though (non-pipeline registered) read data
//
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright 2021, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module SROM_Ax32
#(parameter ADDRWIDTH = 10,
parameter filename = "rom32.hex",
parameter romgen = 0
)
(input wire CLK,
input wire [ADDRWIDTH-1:0] ADDR, //Address Input
input wire SEL, //Select (active-high)
output wire [31:0] RDATA); //Read Data
localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1;
localparam romgenfile = "rom32_bootmem.v";
// Reg declarations
reg [7:0] rombyte0 [0:MEMDEPTH];
reg [7:0] rombyte1 [0:MEMDEPTH];
reg [7:0] rombyte2 [0:MEMDEPTH];
reg [7:0] rombyte3 [0:MEMDEPTH];
reg [ADDRWIDTH-1:0] addr_r; // registered Address for read access
// optional simulation RAM_INIT option to suppress 'X' initial contents
`ifdef MEM_INIT
reg [7:0] fileimage [((4<<ADDRWIDTH)-1):0];
function [31:0] NoX32; input [31:0] n; NoX32 = (((^n) === 1'bx) ? 32'h0 : n); endfunction
integer fd; // file descriptor for file output
integer i;
initial
begin
for (i=0; i<= MEMDEPTH; i=i+1) begin
rombyte0[i] <= 8'he5;
rombyte1[i] <= 8'he5;
rombyte2[i] <= 8'he5;
rombyte3[i] <= 8'he5;
end
if (filename != "") begin
$readmemh(filename, fileimage);
for (i = 0; i <= MEMDEPTH; i=i+1) begin
rombyte0[i] <= fileimage[(i<<2)+0];
rombyte1[i] <= fileimage[(i<<2)+1];
rombyte2[i] <= fileimage[(i<<2)+2];
rombyte3[i] <= fileimage[(i<<2)+3];
end
end
if (romgen != 0)
begin
fd = $fopen(romgenfile);
if(fd == 0) begin
$display("rom32gen: Error, zero returned in response to $fopen\n");
end
else begin
$display(fd,"rom32gen: Generating output file\n");
$fwrite(fd,"module bootrom (\n");
$fwrite(fd," input wire CLK,\n");
$fwrite(fd," input wire EN,\n");
$fwrite(fd," input wire [%0d:2] ADDR,\n", ADDRWIDTH+1);
$fwrite(fd," output reg [31:0] RDATA );\n");
$fwrite(fd,"reg [%0d:2] addr_r;\n", ADDRWIDTH+1);
$fwrite(fd,"always @(posedge CLK) if (EN) addr_r <= ADDR;\n");
$fwrite(fd,"always @(addr_r)");
$fwrite(fd," case(addr_r[%0d:2]) \n", ADDRWIDTH+1);
for (i = 0; i < 4 << (ADDRWIDTH); i=i+4)
$fwrite(fd," %2d'h%2x : RDATA <= 32'h%8x; // 0x%04x\n", ADDRWIDTH, i>>2, NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}), i );
$fwrite(fd," default : RDATA <=32'h0;\n");
$fwrite(fd," endcase\n");
$fwrite(fd,"endmodule\n");
$fclose(fd);
end
end
end
`endif
// synchonous address and control
always @(posedge CLK) // update on any byte lane read
if (SEL)
addr_r <= ADDR[ADDRWIDTH-1:0];
assign RDATA = {rombyte3[addr_r],rombyte2[addr_r],rombyte1[addr_r],rombyte0[addr_r]};
endmodule
GLIB/pads/verilog/GLIB_PADLIB.v 0 → 100755
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// GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// Revision : $Revision: $
//
// Release Information : $ $
//-----------------------------------------------------------------------------
module PAD_INOUT8MA_NOE (
// Inouts
PAD,
// Outputs
O,
// Inputs
I,
NOE
);
inout PAD;
output I;
input O;
input NOE;
`ifdef BEHAVIORAL_PADS
assign I = PAD;
assign PAD = ~NOE ? O : 1'bz;
`else
bufif1 #2 (PAD, O, ~NOE);
buf #1 (I, PAD);
always @(PAD)
begin
if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
$display("%t ++BUS CONFLICT++ : %m", $realtime);
end
`endif // ifdef BEHAVIORAL_PADS
endmodule // PAD_INOUT8MA_NOE
module PAD_INOUT8MA_OE (
// Inouts
PAD,
// Outputs
O,
// Inputs
I,
OE
);
inout PAD;
output I;
input O;
input OE;
`ifdef BEHAVIORAL_PADS
assign I = PAD;
assign PAD = OE ? O : 1'bz;
`else
bufif1 #2 (PAD, O, OE);
buf #1 (I, PAD);
always @(PAD)
begin
if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
$display("%t ++BUS CONFLICT++ : %m", $realtime);
end
`endif // ifdef BEHAVIORAL_PADS
endmodule // PAD_INOUT8MA_OE
module PAD_VDDIO (
PAD
);
inout PAD;
endmodule // PAD_VDDIO
module PAD_VSSIO (
PAD
);
inout PAD;
endmodule // PAD_VSSSIO
// core logic supply rails (1V0, 0V)
module PAD_VDDSOC (
PAD
);
inout PAD;
endmodule // PAD_VDDSOC
module PAD_VSS (
PAD
);
inout PAD;
endmodule // PAD_VSS
// VDDISOL
module PAD_ANALOG (
PAD
);
inout PAD;
endmodule // PAD_ANALOG
`ifdef TSMC_PADS
// VDDSOC
module PVDD1CDG (
inout wire VDD
);
endmodule // PVDD1CDG
//VDDIO
module PVDD2CDG (
inout wire VDDPST
);
endmodule // PVDD2CDG
module PVDD2POC (
inout wire VDDPST
);
endmodule // PVDD2CDG
module PVSS3CDG (
inout wire VSS
);
endmodule // PVSS3CDG
// VDDISOL
module PVDD1ANA (
inout wire AVDD
);
endmodule // PVDD1ANA
module PCORNER ( ); endmodule
module PFILLER20 ( ); endmodule
module PFILLER1 ( ); endmodule
module PFILLER0005 ( ); endmodule
module PAD60LU ( ); endmodule
`endif
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