diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom.v
new file mode 100644
index 0000000000000000000000000000000000000000..5031a98de8ff274fb846a9bc902ca595037db7ce
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom.v
@@ -0,0 +1,29 @@
+module ahb_bootrom #(
+ // Parameters
+ parameter AW = 10 // Address width
+ )
+ (
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+ input wire HSEL, // Device select
+ input wire [AW-1:0] HADDR, // Address
+ input wire [1:0] HTRANS, // Transfer control
+ input wire [2:0] HSIZE, // Transfer size
+ input wire HWRITE, // Write control
+ input wire [31:0] HWDATA, // Write data - not used
+ input wire HREADY, // Transfer phase done
+ output wire HREADYOUT, // Device ready
+ output wire [31:0] HRDATA, // Read data output
+ output wire HRESP // Device response (always OKAY)
+);
+
+ bootrom u_bootrom (
+ .CLK (HCLK),
+ .EN (HSEL & HTRANS[1] & HREADY & !HWRITE),
+ .ADDR (HADDR[AW-1:2]),
+ .RDATA (HRDATA)
+ );
+ assign HREADYOUT = 1'b1;
+ assign HRESP = 1'b0;
+
+endmodule
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom__mangled.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom__mangled.v
new file mode 100644
index 0000000000000000000000000000000000000000..9a4aedaa14fba2d338448ea0b52d93f845ec95f1
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/ahb_bootrom__mangled.v
@@ -0,0 +1,2381 @@
+//
+// A joint work commissioned on behalf of SoC Labs.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Obfuscated RTL
+//
+// Copyright © 2021, SoC Labs (www.soclabs.org)
+//
+
+/*
+ instances: 0
+ nodes: 1136 (0)
+ node widths: 1220 (0)
+ process: 8 (0)
+ contassign: 1156 (0)
+ ports: 13 (0)
+*/
+
+/* Source file "tokens.v", line 14 */
+module ahb_bootrom__mangled(HCLK, HRESETn, HSEL, HADDR, HTRANS, HSIZE, HWRITE,
+ HWDATA, HREADY, HREADYOUT, HRDATA, HRESP);
+
+ input [9:0] HADDR;
+ input [1:0] HTRANS;
+ input [2:0] HSIZE;
+ input [31:0] HWDATA;
+ output [31:0] HRDATA;
+ input HCLK;
+ input HRESETn;
+ input HSEL;
+ input HWRITE;
+ input HREADY;
+ output HREADYOUT;
+ output HRESP;
+
+ wire Uqpfh7;
+ wire Zqpfh7;
+ wire Erpfh7;
+ wire Jrpfh7;
+ wire Orpfh7;
+ wire Trpfh7;
+ wire Yrpfh7;
+ wire Dspfh7;
+ wire Ispfh7;
+ wire Ospfh7;
+ wire Uspfh7;
+ wire Atpfh7;
+ wire Gtpfh7;
+ wire Mtpfh7;
+ wire Stpfh7;
+ wire Ytpfh7;
+ wire Eupfh7;
+ wire Kupfh7;
+ wire Qupfh7;
+ wire Wupfh7;
+ wire Cvpfh7;
+ wire Ivpfh7;
+ wire Ovpfh7;
+ wire Uvpfh7;
+ wire Awpfh7;
+ wire Gwpfh7;
+ wire Mwpfh7;
+ wire Swpfh7;
+ wire Ywpfh7;
+ wire Expfh7;
+ wire Kxpfh7;
+ wire Qxpfh7;
+ wire Wxpfh7;
+ wire Cypfh7;
+ wire Iypfh7;
+ wire Oypfh7;
+ wire Uypfh7;
+ wire Azpfh7;
+ wire Gzpfh7;
+ wire Mzpfh7;
+ wire Szpfh7;
+ wire Yzpfh7;
+ wire E0qfh7;
+ wire K0qfh7;
+ wire Q0qfh7;
+ wire W0qfh7;
+ wire C1qfh7;
+ wire I1qfh7;
+ wire O1qfh7;
+ wire U1qfh7;
+ wire A2qfh7;
+ wire G2qfh7;
+ wire M2qfh7;
+ wire S2qfh7;
+ wire Y2qfh7;
+ wire E3qfh7;
+ wire K3qfh7;
+ wire Q3qfh7;
+ wire W3qfh7;
+ wire C4qfh7;
+ wire I4qfh7;
+ wire O4qfh7;
+ wire U4qfh7;
+ wire A5qfh7;
+ wire G5qfh7;
+ wire M5qfh7;
+ wire S5qfh7;
+ wire Y5qfh7;
+ wire E6qfh7;
+ wire K6qfh7;
+ wire Q6qfh7;
+ wire W6qfh7;
+ wire C7qfh7;
+ wire I7qfh7;
+ wire O7qfh7;
+ wire U7qfh7;
+ wire A8qfh7;
+ wire G8qfh7;
+ wire M8qfh7;
+ wire S8qfh7;
+ wire Y8qfh7;
+ wire E9qfh7;
+ wire K9qfh7;
+ wire Q9qfh7;
+ wire W9qfh7;
+ wire Caqfh7;
+ wire Iaqfh7;
+ wire Oaqfh7;
+ wire Uaqfh7;
+ wire Abqfh7;
+ wire Gbqfh7;
+ wire Mbqfh7;
+ wire Sbqfh7;
+ wire Ybqfh7;
+ wire Ecqfh7;
+ wire Kcqfh7;
+ wire Qcqfh7;
+ wire Wcqfh7;
+ wire Cdqfh7;
+ wire Idqfh7;
+ wire Odqfh7;
+ wire Udqfh7;
+ wire Aeqfh7;
+ wire Geqfh7;
+ wire Meqfh7;
+ wire Seqfh7;
+ wire Yeqfh7;
+ wire Efqfh7;
+ wire Kfqfh7;
+ wire Qfqfh7;
+ wire Wfqfh7;
+ wire Cgqfh7;
+ wire Igqfh7;
+ wire Ogqfh7;
+ wire Ugqfh7;
+ wire Ahqfh7;
+ wire Ghqfh7;
+ wire Mhqfh7;
+ wire Shqfh7;
+ wire Yhqfh7;
+ wire Eiqfh7;
+ wire Kiqfh7;
+ wire Qiqfh7;
+ wire Wiqfh7;
+ wire Cjqfh7;
+ wire Ijqfh7;
+ wire Ojqfh7;
+ wire Ujqfh7;
+ wire Akqfh7;
+ wire Gkqfh7;
+ wire Mkqfh7;
+ wire Skqfh7;
+ wire Ykqfh7;
+ wire Elqfh7;
+ wire Klqfh7;
+ wire Qlqfh7;
+ wire Wlqfh7;
+ wire Cmqfh7;
+ wire Imqfh7;
+ wire Omqfh7;
+ wire Umqfh7;
+ wire Anqfh7;
+ wire Gnqfh7;
+ wire Mnqfh7;
+ wire Snqfh7;
+ wire Ynqfh7;
+ wire Eoqfh7;
+ wire Koqfh7;
+ wire Qoqfh7;
+ wire Woqfh7;
+ wire Cpqfh7;
+ wire Ipqfh7;
+ wire Opqfh7;
+ wire Upqfh7;
+ wire Aqqfh7;
+ wire Gqqfh7;
+ wire Mqqfh7;
+ wire Sqqfh7;
+ wire Yqqfh7;
+ wire Erqfh7;
+ wire Krqfh7;
+ wire Qrqfh7;
+ wire Wrqfh7;
+ wire Csqfh7;
+ wire Isqfh7;
+ wire Osqfh7;
+ wire Usqfh7;
+ wire Atqfh7;
+ wire Gtqfh7;
+ wire Mtqfh7;
+ wire Stqfh7;
+ wire Ytqfh7;
+ wire Euqfh7;
+ wire Kuqfh7;
+ wire Quqfh7;
+ wire Wuqfh7;
+ wire Cvqfh7;
+ wire Ivqfh7;
+ wire Ovqfh7;
+ wire Uvqfh7;
+ wire Awqfh7;
+ wire Gwqfh7;
+ wire Mwqfh7;
+ wire Swqfh7;
+ wire Ywqfh7;
+ wire Exqfh7;
+ wire Kxqfh7;
+ wire Qxqfh7;
+ wire Wxqfh7;
+ wire Cyqfh7;
+ wire Iyqfh7;
+ wire Oyqfh7;
+ wire Uyqfh7;
+ wire Azqfh7;
+ wire Gzqfh7;
+ wire Mzqfh7;
+ wire Szqfh7;
+ wire Yzqfh7;
+ wire E0rfh7;
+ wire K0rfh7;
+ wire Q0rfh7;
+ wire W0rfh7;
+ wire C1rfh7;
+ wire I1rfh7;
+ wire O1rfh7;
+ wire U1rfh7;
+ wire A2rfh7;
+ wire G2rfh7;
+ wire M2rfh7;
+ wire S2rfh7;
+ wire Y2rfh7;
+ wire E3rfh7;
+ wire K3rfh7;
+ wire Q3rfh7;
+ wire W3rfh7;
+ wire C4rfh7;
+ wire I4rfh7;
+ wire O4rfh7;
+ wire U4rfh7;
+ wire A5rfh7;
+ wire G5rfh7;
+ wire M5rfh7;
+ wire S5rfh7;
+ wire Y5rfh7;
+ wire E6rfh7;
+ wire K6rfh7;
+ wire Q6rfh7;
+ wire W6rfh7;
+ wire C7rfh7;
+ wire I7rfh7;
+ wire O7rfh7;
+ wire U7rfh7;
+ wire A8rfh7;
+ wire G8rfh7;
+ wire M8rfh7;
+ wire S8rfh7;
+ wire Y8rfh7;
+ wire E9rfh7;
+ wire K9rfh7;
+ wire Q9rfh7;
+ wire W9rfh7;
+ wire Carfh7;
+ wire Iarfh7;
+ wire Oarfh7;
+ wire Uarfh7;
+ wire Abrfh7;
+ wire Gbrfh7;
+ wire Mbrfh7;
+ wire Sbrfh7;
+ wire Ybrfh7;
+ wire Ecrfh7;
+ wire Kcrfh7;
+ wire Qcrfh7;
+ wire Wcrfh7;
+ wire Cdrfh7;
+ wire Idrfh7;
+ wire Odrfh7;
+ wire Udrfh7;
+ wire Aerfh7;
+ wire Gerfh7;
+ wire Merfh7;
+ wire Serfh7;
+ wire Yerfh7;
+ wire Efrfh7;
+ wire Kfrfh7;
+ wire Qfrfh7;
+ wire Wfrfh7;
+ wire Cgrfh7;
+ wire Igrfh7;
+ wire Ogrfh7;
+ wire Ugrfh7;
+ wire Ahrfh7;
+ wire Ghrfh7;
+ wire Mhrfh7;
+ wire Shrfh7;
+ wire Yhrfh7;
+ wire Eirfh7;
+ wire Kirfh7;
+ wire Qirfh7;
+ wire Wirfh7;
+ wire Cjrfh7;
+ wire Ijrfh7;
+ wire Ojrfh7;
+ wire Ujrfh7;
+ wire Akrfh7;
+ wire Gkrfh7;
+ wire Mkrfh7;
+ wire Skrfh7;
+ wire Ykrfh7;
+ wire Elrfh7;
+ wire Klrfh7;
+ wire Qlrfh7;
+ wire Wlrfh7;
+ wire Cmrfh7;
+ wire Imrfh7;
+ wire Omrfh7;
+ wire Umrfh7;
+ wire Anrfh7;
+ wire Gnrfh7;
+ wire Mnrfh7;
+ wire Snrfh7;
+ wire Ynrfh7;
+ wire Eorfh7;
+ wire Korfh7;
+ wire Qorfh7;
+ wire Worfh7;
+ wire Cprfh7;
+ wire Iprfh7;
+ wire Oprfh7;
+ wire Uprfh7;
+ wire Aqrfh7;
+ wire Gqrfh7;
+ wire Mqrfh7;
+ wire Sqrfh7;
+ wire Yqrfh7;
+ wire Errfh7;
+ wire Krrfh7;
+ wire Qrrfh7;
+ wire Wrrfh7;
+ wire Csrfh7;
+ wire Isrfh7;
+ wire Osrfh7;
+ wire Usrfh7;
+ wire Atrfh7;
+ wire Gtrfh7;
+ wire Mtrfh7;
+ wire Strfh7;
+ wire Ytrfh7;
+ wire Eurfh7;
+ wire Kurfh7;
+ wire Qurfh7;
+ wire Wurfh7;
+ wire Cvrfh7;
+ wire Ivrfh7;
+ wire Ovrfh7;
+ wire Uvrfh7;
+ wire Awrfh7;
+ wire Gwrfh7;
+ wire Mwrfh7;
+ wire Swrfh7;
+ wire Ywrfh7;
+ wire Exrfh7;
+ wire Kxrfh7;
+ wire Qxrfh7;
+ wire Wxrfh7;
+ wire Cyrfh7;
+ wire Iyrfh7;
+ wire Oyrfh7;
+ wire Uyrfh7;
+ wire Azrfh7;
+ wire Gzrfh7;
+ wire Mzrfh7;
+ wire Szrfh7;
+ wire Yzrfh7;
+ wire E0sfh7;
+ wire K0sfh7;
+ wire Q0sfh7;
+ wire W0sfh7;
+ wire C1sfh7;
+ wire I1sfh7;
+ wire O1sfh7;
+ wire U1sfh7;
+ wire A2sfh7;
+ wire G2sfh7;
+ wire M2sfh7;
+ wire S2sfh7;
+ wire Y2sfh7;
+ wire E3sfh7;
+ wire K3sfh7;
+ wire Q3sfh7;
+ wire W3sfh7;
+ wire C4sfh7;
+ wire I4sfh7;
+ wire O4sfh7;
+ wire U4sfh7;
+ wire A5sfh7;
+ wire G5sfh7;
+ wire M5sfh7;
+ wire S5sfh7;
+ wire Y5sfh7;
+ wire E6sfh7;
+ wire K6sfh7;
+ wire Q6sfh7;
+ wire W6sfh7;
+ wire C7sfh7;
+ wire I7sfh7;
+ wire O7sfh7;
+ wire U7sfh7;
+ wire A8sfh7;
+ wire G8sfh7;
+ wire M8sfh7;
+ wire S8sfh7;
+ wire Y8sfh7;
+ wire E9sfh7;
+ wire K9sfh7;
+ wire Q9sfh7;
+ wire W9sfh7;
+ wire Casfh7;
+ wire Iasfh7;
+ wire Oasfh7;
+ wire Uasfh7;
+ wire Absfh7;
+ wire Gbsfh7;
+ wire Mbsfh7;
+ wire Sbsfh7;
+ wire Ybsfh7;
+ wire Ecsfh7;
+ wire Kcsfh7;
+ wire Qcsfh7;
+ wire Wcsfh7;
+ wire Cdsfh7;
+ wire Idsfh7;
+ wire Odsfh7;
+ wire Udsfh7;
+ wire Aesfh7;
+ wire Gesfh7;
+ wire Mesfh7;
+ wire Sesfh7;
+ wire Yesfh7;
+ wire Efsfh7;
+ wire Kfsfh7;
+ wire Qfsfh7;
+ wire Wfsfh7;
+ wire Cgsfh7;
+ wire Igsfh7;
+ wire Ogsfh7;
+ wire Ugsfh7;
+ wire Ahsfh7;
+ wire Ghsfh7;
+ wire Mhsfh7;
+ wire Shsfh7;
+ wire Yhsfh7;
+ wire Eisfh7;
+ wire Kisfh7;
+ wire Qisfh7;
+ wire Wisfh7;
+ wire Cjsfh7;
+ wire Ijsfh7;
+ wire Ojsfh7;
+ wire Ujsfh7;
+ wire Aksfh7;
+ wire Gksfh7;
+ wire Mksfh7;
+ wire Sksfh7;
+ wire Yksfh7;
+ wire Elsfh7;
+ wire Klsfh7;
+ wire Qlsfh7;
+ wire Wlsfh7;
+ wire Cmsfh7;
+ wire Imsfh7;
+ wire Omsfh7;
+ wire Umsfh7;
+ wire Ansfh7;
+ wire Gnsfh7;
+ wire Mnsfh7;
+ wire Snsfh7;
+ wire Ynsfh7;
+ wire Eosfh7;
+ wire Kosfh7;
+ wire Qosfh7;
+ wire Wosfh7;
+ wire Cpsfh7;
+ wire Ipsfh7;
+ wire Opsfh7;
+ wire Upsfh7;
+ wire Aqsfh7;
+ wire Gqsfh7;
+ wire Mqsfh7;
+ wire Sqsfh7;
+ wire Yqsfh7;
+ wire Ersfh7;
+ wire Krsfh7;
+ wire Qrsfh7;
+ wire Wrsfh7;
+ wire Cssfh7;
+ wire Issfh7;
+ wire Ossfh7;
+ wire Ussfh7;
+ wire Atsfh7;
+ wire Gtsfh7;
+ wire Mtsfh7;
+ wire Stsfh7;
+ wire Ytsfh7;
+ wire Eusfh7;
+ wire Kusfh7;
+ wire Qusfh7;
+ wire Wusfh7;
+ wire Cvsfh7;
+ wire Ivsfh7;
+ wire Ovsfh7;
+ wire Uvsfh7;
+ wire Awsfh7;
+ wire Gwsfh7;
+ wire Mwsfh7;
+ wire Swsfh7;
+ wire Ywsfh7;
+ wire Exsfh7;
+ wire Kxsfh7;
+ wire Qxsfh7;
+ wire Wxsfh7;
+ wire Cysfh7;
+ wire Iysfh7;
+ wire Oysfh7;
+ wire Uysfh7;
+ wire Azsfh7;
+ wire Gzsfh7;
+ wire Mzsfh7;
+ wire Szsfh7;
+ wire Yzsfh7;
+ wire E0tfh7;
+ wire K0tfh7;
+ wire Q0tfh7;
+ wire W0tfh7;
+ wire C1tfh7;
+ wire I1tfh7;
+ wire O1tfh7;
+ wire U1tfh7;
+ wire A2tfh7;
+ wire G2tfh7;
+ wire M2tfh7;
+ wire S2tfh7;
+ wire Y2tfh7;
+ wire E3tfh7;
+ wire K3tfh7;
+ wire Q3tfh7;
+ wire W3tfh7;
+ wire C4tfh7;
+ wire I4tfh7;
+ wire O4tfh7;
+ wire U4tfh7;
+ wire A5tfh7;
+ wire G5tfh7;
+ wire M5tfh7;
+ wire S5tfh7;
+ wire Y5tfh7;
+ wire E6tfh7;
+ wire K6tfh7;
+ wire Q6tfh7;
+ wire W6tfh7;
+ wire C7tfh7;
+ wire I7tfh7;
+ wire O7tfh7;
+ wire U7tfh7;
+ wire A8tfh7;
+ wire G8tfh7;
+ wire M8tfh7;
+ wire S8tfh7;
+ wire Y8tfh7;
+ wire E9tfh7;
+ wire K9tfh7;
+ wire Q9tfh7;
+ wire W9tfh7;
+ wire Catfh7;
+ wire Iatfh7;
+ wire Oatfh7;
+ wire Uatfh7;
+ wire Abtfh7;
+ wire Gbtfh7;
+ wire Mbtfh7;
+ wire Sbtfh7;
+ wire Ybtfh7;
+ wire Ectfh7;
+ wire Kctfh7;
+ wire Qctfh7;
+ wire Wctfh7;
+ wire Cdtfh7;
+ wire Idtfh7;
+ wire Odtfh7;
+ wire Udtfh7;
+ wire Aetfh7;
+ wire Getfh7;
+ wire Metfh7;
+ wire Setfh7;
+ wire Yetfh7;
+ wire Eftfh7;
+ wire Kftfh7;
+ wire Qftfh7;
+ wire Wftfh7;
+ wire Cgtfh7;
+ wire Igtfh7;
+ wire Ogtfh7;
+ wire Ugtfh7;
+ wire Ahtfh7;
+ wire Ghtfh7;
+ wire Mhtfh7;
+ wire Shtfh7;
+ wire Yhtfh7;
+ wire Eitfh7;
+ wire Kitfh7;
+ wire Qitfh7;
+ wire Witfh7;
+ wire Cjtfh7;
+ wire Ijtfh7;
+ wire Ojtfh7;
+ wire Ujtfh7;
+ wire Aktfh7;
+ wire Gktfh7;
+ wire Mktfh7;
+ wire Sktfh7;
+ wire Yktfh7;
+ wire Eltfh7;
+ wire Kltfh7;
+ wire Qltfh7;
+ wire Wltfh7;
+ wire Cmtfh7;
+ wire Imtfh7;
+ wire Omtfh7;
+ wire Umtfh7;
+ wire Antfh7;
+ wire Gntfh7;
+ wire Mntfh7;
+ wire Sntfh7;
+ wire Yntfh7;
+ wire Eotfh7;
+ wire Kotfh7;
+ wire Qotfh7;
+ wire Wotfh7;
+ wire Cptfh7;
+ wire Iptfh7;
+ wire Optfh7;
+ wire Uptfh7;
+ wire Aqtfh7;
+ wire Gqtfh7;
+ wire Mqtfh7;
+ wire Sqtfh7;
+ wire Yqtfh7;
+ wire Ertfh7;
+ wire Krtfh7;
+ wire Qrtfh7;
+ wire Wrtfh7;
+ wire Cstfh7;
+ wire Istfh7;
+ wire Ostfh7;
+ wire Ustfh7;
+ wire Attfh7;
+ wire Gttfh7;
+ wire Mttfh7;
+ wire Sttfh7;
+ wire Yttfh7;
+ wire Eutfh7;
+ wire Kutfh7;
+ wire Qutfh7;
+ wire Wutfh7;
+ wire Cvtfh7;
+ wire Ivtfh7;
+ wire Ovtfh7;
+ wire Uvtfh7;
+ wire Awtfh7;
+ wire Gwtfh7;
+ wire Mwtfh7;
+ wire Swtfh7;
+ wire Ywtfh7;
+ wire Extfh7;
+ wire Kxtfh7;
+ wire Qxtfh7;
+ wire Wxtfh7;
+ wire Cytfh7;
+ wire Iytfh7;
+ wire Oytfh7;
+ wire Uytfh7;
+ wire Aztfh7;
+ wire Gztfh7;
+ wire Mztfh7;
+ wire Sztfh7;
+ wire Yztfh7;
+ wire E0ufh7;
+ wire K0ufh7;
+ wire Q0ufh7;
+ wire W0ufh7;
+ wire C1ufh7;
+ wire I1ufh7;
+ wire O1ufh7;
+ wire U1ufh7;
+ wire A2ufh7;
+ wire G2ufh7;
+ wire M2ufh7;
+ wire S2ufh7;
+ wire Y2ufh7;
+ wire E3ufh7;
+ wire K3ufh7;
+ wire Q3ufh7;
+ wire W3ufh7;
+ wire C4ufh7;
+ wire I4ufh7;
+ wire O4ufh7;
+ wire U4ufh7;
+ wire A5ufh7;
+ wire G5ufh7;
+ wire M5ufh7;
+ wire S5ufh7;
+ wire Y5ufh7;
+ wire E6ufh7;
+ wire K6ufh7;
+ wire Q6ufh7;
+ wire W6ufh7;
+ wire C7ufh7;
+ wire I7ufh7;
+ wire O7ufh7;
+ wire U7ufh7;
+ wire A8ufh7;
+ wire G8ufh7;
+ wire M8ufh7;
+ wire S8ufh7;
+ wire Y8ufh7;
+ wire E9ufh7;
+ wire K9ufh7;
+ wire Q9ufh7;
+ wire W9ufh7;
+ wire Caufh7;
+ wire Iaufh7;
+ wire Oaufh7;
+ wire Uaufh7;
+ wire Abufh7;
+ wire Gbufh7;
+ wire Mbufh7;
+ wire Sbufh7;
+ wire Ybufh7;
+ wire Ecufh7;
+ wire Kcufh7;
+ wire Qcufh7;
+ wire Wcufh7;
+ wire Cdufh7;
+ wire Idufh7;
+ wire Odufh7;
+ wire Udufh7;
+ wire Aeufh7;
+ wire Geufh7;
+ wire Meufh7;
+ wire Seufh7;
+ wire Yeufh7;
+ wire Efufh7;
+ wire Kfufh7;
+ wire Qfufh7;
+ wire Wfufh7;
+ wire Cgufh7;
+ wire Igufh7;
+ wire Ogufh7;
+ wire Ugufh7;
+ wire Ahufh7;
+ wire Ghufh7;
+ wire Mhufh7;
+ wire Shufh7;
+ wire Yhufh7;
+ wire Eiufh7;
+ wire Kiufh7;
+ wire Qiufh7;
+ wire Wiufh7;
+ wire Cjufh7;
+ wire Ijufh7;
+ wire Ojufh7;
+ wire Ujufh7;
+ wire Akufh7;
+ wire Gkufh7;
+ wire Mkufh7;
+ wire Skufh7;
+ wire Ykufh7;
+ wire Elufh7;
+ wire Klufh7;
+ wire Qlufh7;
+ wire Wlufh7;
+ wire Cmufh7;
+ wire Imufh7;
+ wire Omufh7;
+ wire Umufh7;
+ wire Anufh7;
+ wire Gnufh7;
+ wire Mnufh7;
+ wire Snufh7;
+ wire Ynufh7;
+ wire Eoufh7;
+ wire Koufh7;
+ wire Qoufh7;
+ wire Woufh7;
+ wire Cpufh7;
+ wire Ipufh7;
+ wire Opufh7;
+ wire Upufh7;
+ wire Aqufh7;
+ wire Gqufh7;
+ wire Mqufh7;
+ wire Squfh7;
+ wire Yqufh7;
+ wire Erufh7;
+ wire Krufh7;
+ wire Qrufh7;
+ wire Wrufh7;
+ wire Csufh7;
+ wire Isufh7;
+ wire Osufh7;
+ wire Usufh7;
+ wire Atufh7;
+ wire Gtufh7;
+ wire Mtufh7;
+ wire Stufh7;
+ wire Ytufh7;
+ wire Euufh7;
+ wire Kuufh7;
+ wire Quufh7;
+ wire Wuufh7;
+ wire Cvufh7;
+ wire Ivufh7;
+ wire Ovufh7;
+ wire Uvufh7;
+ wire Awufh7;
+ wire Gwufh7;
+ wire Mwufh7;
+ wire Swufh7;
+ wire Ywufh7;
+ wire Exufh7;
+ wire Kxufh7;
+ wire Qxufh7;
+ wire Wxufh7;
+ wire Cyufh7;
+ wire Iyufh7;
+ wire Oyufh7;
+ wire Uyufh7;
+ wire Azufh7;
+ wire Gzufh7;
+ wire Mzufh7;
+ wire Szufh7;
+ wire Yzufh7;
+ wire E0vfh7;
+ wire K0vfh7;
+ wire Q0vfh7;
+ wire W0vfh7;
+ wire C1vfh7;
+ wire I1vfh7;
+ wire O1vfh7;
+ wire U1vfh7;
+ wire A2vfh7;
+ wire G2vfh7;
+ wire M2vfh7;
+ wire S2vfh7;
+ wire Y2vfh7;
+ wire E3vfh7;
+ wire K3vfh7;
+ wire Q3vfh7;
+ wire W3vfh7;
+ wire C4vfh7;
+ wire I4vfh7;
+ wire O4vfh7;
+ wire U4vfh7;
+ wire A5vfh7;
+ wire G5vfh7;
+ wire M5vfh7;
+ wire S5vfh7;
+ wire Y5vfh7;
+ wire E6vfh7;
+ wire K6vfh7;
+ wire Q6vfh7;
+ wire W6vfh7;
+ wire C7vfh7;
+ wire I7vfh7;
+ wire O7vfh7;
+ wire U7vfh7;
+ wire A8vfh7;
+ wire G8vfh7;
+ wire M8vfh7;
+ wire S8vfh7;
+ wire Y8vfh7;
+ wire E9vfh7;
+ wire K9vfh7;
+ wire Q9vfh7;
+ wire W9vfh7;
+ wire Cavfh7;
+ wire Iavfh7;
+ wire Oavfh7;
+ wire Uavfh7;
+ wire Abvfh7;
+ wire Gbvfh7;
+ wire Mbvfh7;
+ wire Sbvfh7;
+ wire Ybvfh7;
+ wire Ecvfh7;
+ wire Kcvfh7;
+ wire Qcvfh7;
+ wire Wcvfh7;
+ wire Cdvfh7;
+ wire Idvfh7;
+ wire Odvfh7;
+ wire Udvfh7;
+ wire Aevfh7;
+ wire Gevfh7;
+ wire Mevfh7;
+ wire Sevfh7;
+ wire Yevfh7;
+ wire Efvfh7;
+ wire Kfvfh7;
+ wire Qfvfh7;
+ wire Wfvfh7;
+ wire Cgvfh7;
+ wire Igvfh7;
+ wire Ogvfh7;
+ wire Ugvfh7;
+ wire Ahvfh7;
+ wire Ghvfh7;
+ wire Mhvfh7;
+ wire Shvfh7;
+ wire Yhvfh7;
+ wire Eivfh7;
+ wire Kivfh7;
+ wire Qivfh7;
+ wire Wivfh7;
+ wire Cjvfh7;
+ wire Ijvfh7;
+ wire Ojvfh7;
+ wire Ujvfh7;
+ wire Akvfh7;
+ wire Gkvfh7;
+ wire Mkvfh7;
+ wire Skvfh7;
+ wire Ykvfh7;
+ wire Elvfh7;
+ wire Klvfh7;
+ wire Qlvfh7;
+ wire Wlvfh7;
+ wire Cmvfh7;
+ wire Imvfh7;
+ wire Omvfh7;
+ wire Umvfh7;
+ wire Anvfh7;
+ wire Gnvfh7;
+ wire Mnvfh7;
+ wire Snvfh7;
+ wire Ynvfh7;
+ wire Eovfh7;
+ wire Kovfh7;
+ wire Qovfh7;
+ wire Wovfh7;
+ wire Cpvfh7;
+ wire Ipvfh7;
+ wire Opvfh7;
+ wire Upvfh7;
+ wire Aqvfh7;
+ wire Gqvfh7;
+ wire Mqvfh7;
+ wire Sqvfh7;
+ wire Yqvfh7;
+ wire Ervfh7;
+ wire Krvfh7;
+ wire Qrvfh7;
+ wire Wrvfh7;
+ wire Csvfh7;
+ wire Isvfh7;
+ wire Osvfh7;
+ wire Usvfh7;
+ wire Atvfh7;
+ wire Gtvfh7;
+ wire Mtvfh7;
+ wire Stvfh7;
+ wire Ytvfh7;
+ wire Euvfh7;
+ wire Kuvfh7;
+ wire Quvfh7;
+ wire Wuvfh7;
+ wire Cvvfh7;
+ wire Ivvfh7;
+ wire Ovvfh7;
+ wire Uvvfh7;
+ wire Awvfh7;
+ wire Gwvfh7;
+ wire Mwvfh7;
+ wire Swvfh7;
+ wire Ywvfh7;
+ wire Exvfh7;
+ wire Kxvfh7;
+ wire Qxvfh7;
+ wire Wxvfh7;
+ wire Cyvfh7;
+ wire Iyvfh7;
+ wire Oyvfh7;
+ wire Uyvfh7;
+ wire Azvfh7;
+ wire Gzvfh7;
+ wire Mzvfh7;
+ wire Szvfh7;
+ wire Yzvfh7;
+ wire E0wfh7;
+ wire K0wfh7;
+ wire Q0wfh7;
+ wire W0wfh7;
+ wire C1wfh7;
+ wire I1wfh7;
+ wire O1wfh7;
+ wire U1wfh7;
+ wire A2wfh7;
+ wire G2wfh7;
+ wire M2wfh7;
+ wire S2wfh7;
+ wire Y2wfh7;
+ wire E3wfh7;
+ wire K3wfh7;
+ wire Q3wfh7;
+ wire W3wfh7;
+ wire C4wfh7;
+ wire I4wfh7;
+ wire O4wfh7;
+ wire U4wfh7;
+ wire A5wfh7;
+ wire G5wfh7;
+ wire M5wfh7;
+ wire S5wfh7;
+ wire Y5wfh7;
+ wire E6wfh7;
+ wire K6wfh7;
+ wire Q6wfh7;
+ wire W6wfh7;
+ wire C7wfh7;
+ wire I7wfh7;
+ wire O7wfh7;
+ wire U7wfh7;
+ wire A8wfh7;
+ wire G8wfh7;
+ wire M8wfh7;
+ wire S8wfh7;
+ wire Y8wfh7;
+ wire E9wfh7;
+ wire K9wfh7;
+ wire Q9wfh7;
+ wire W9wfh7;
+ wire Cawfh7;
+ wire Iawfh7;
+ wire Oawfh7;
+ wire Uawfh7;
+ wire Abwfh7;
+ wire Gbwfh7;
+ wire Mbwfh7;
+ wire Sbwfh7;
+ wire Ybwfh7;
+ wire Ecwfh7;
+ wire Kcwfh7;
+ wire Qcwfh7;
+ wire Wcwfh7;
+ wire Cdwfh7;
+ wire Idwfh7;
+ wire Odwfh7;
+ wire Udwfh7;
+ wire Aewfh7;
+ wire Gewfh7;
+ wire Mewfh7;
+ wire Sewfh7;
+ wire Yewfh7;
+ wire Efwfh7;
+ wire Kfwfh7;
+ wire Qfwfh7;
+ wire Wfwfh7;
+ wire Cgwfh7;
+ wire Igwfh7;
+ wire Ogwfh7;
+ wire Ugwfh7;
+ wire Ahwfh7;
+ wire Ghwfh7;
+ wire Mhwfh7;
+ wire Shwfh7;
+ wire Yhwfh7;
+ wire Eiwfh7;
+ wire Kiwfh7;
+ wire Qiwfh7;
+ wire Wiwfh7;
+ wire Cjwfh7;
+ wire Ijwfh7;
+ wire Ojwfh7;
+ wire Ujwfh7;
+ wire Akwfh7;
+ wire Gkwfh7;
+ wire Mkwfh7;
+ wire Skwfh7;
+ wire Ykwfh7;
+ wire Elwfh7;
+ wire Klwfh7;
+ wire Qlwfh7;
+ wire Wlwfh7;
+ wire Cmwfh7;
+ wire Imwfh7;
+ wire Omwfh7;
+ wire Umwfh7;
+ wire Anwfh7;
+ wire Gnwfh7;
+ wire Mnwfh7;
+ wire Snwfh7;
+ wire Ynwfh7;
+ wire Eowfh7;
+ wire Kowfh7;
+ wire Qowfh7;
+ wire Wowfh7;
+ wire Cpwfh7;
+ wire Ipwfh7;
+ wire Opwfh7;
+ wire Upwfh7;
+ wire Aqwfh7;
+ wire Gqwfh7;
+ wire Mqwfh7;
+ wire Sqwfh7;
+ wire Yqwfh7;
+ wire Erwfh7;
+ wire Krwfh7;
+ wire Qrwfh7;
+ wire Wrwfh7;
+ wire Cswfh7;
+ wire Iswfh7;
+ wire Oswfh7;
+ wire Uswfh7;
+ wire Atwfh7;
+ wire Gtwfh7;
+ wire Mtwfh7;
+ wire Stwfh7;
+ wire Ytwfh7;
+ wire Euwfh7;
+ wire Kuwfh7;
+ wire Quwfh7;
+ wire Wuwfh7;
+ wire Cvwfh7;
+ wire Ivwfh7;
+ wire [9:2] Ovwfh7;
+ reg Fwwfh7;
+ reg Dxwfh7;
+ reg Bywfh7;
+ reg Zywfh7;
+ reg Xzwfh7;
+ reg V0xfh7;
+ reg T1xfh7;
+ reg R2xfh7;
+
+ assign HREADYOUT = 1'b1;
+ assign HRESP = 1'b0;
+ assign Ovwfh7[2] = Fwwfh7;
+ assign Ovwfh7[3] = Dxwfh7;
+ assign Ovwfh7[4] = Bywfh7;
+ assign Ovwfh7[5] = Zywfh7;
+ assign Ovwfh7[6] = Xzwfh7;
+ assign Ovwfh7[7] = V0xfh7;
+ assign Ovwfh7[8] = T1xfh7;
+ assign Ovwfh7[9] = R2xfh7;
+ assign Dspfh7 = (Ispfh7 ? HADDR[2] : Ovwfh7[2]);
+ assign Yrpfh7 = (Ispfh7 ? HADDR[3] : Ovwfh7[3]);
+ assign Trpfh7 = (Ispfh7 ? HADDR[4] : Ovwfh7[4]);
+ assign Orpfh7 = (Ispfh7 ? HADDR[5] : Ovwfh7[5]);
+ assign Jrpfh7 = (Ispfh7 ? HADDR[6] : Ovwfh7[6]);
+ assign Erpfh7 = (Ispfh7 ? HADDR[7] : Ovwfh7[7]);
+ assign Ispfh7 = (!Ospfh7);
+ assign Zqpfh7 = (Ospfh7 ? Ovwfh7[8] : HADDR[8]);
+ assign Uqpfh7 = (Ospfh7 ? Ovwfh7[9] : HADDR[9]);
+ assign Ospfh7 = (~(Uspfh7 & Atpfh7));
+ assign Atpfh7 = (HREADY & Gtpfh7);
+ assign Gtpfh7 = (!HWRITE);
+ assign Uspfh7 = (HTRANS[1] & HSEL);
+ assign HRDATA[9] = (~(Mtpfh7 & Stpfh7));
+ assign Stpfh7 = (Ytpfh7 & Eupfh7);
+ assign Eupfh7 = (Kupfh7 & Qupfh7);
+ assign Kupfh7 = (Wupfh7 & Cvpfh7);
+ assign Ytpfh7 = (Ivpfh7 & Ovpfh7);
+ assign Ivpfh7 = (Uvpfh7 & Awpfh7);
+ assign Mtpfh7 = (Gwpfh7 & Mwpfh7);
+ assign Mwpfh7 = (Swpfh7 & Ywpfh7);
+ assign Swpfh7 = (Expfh7 & Kxpfh7);
+ assign Gwpfh7 = (Qxpfh7 & Wxpfh7);
+ assign Qxpfh7 = (Cypfh7 & Iypfh7);
+ assign HRDATA[8] = (~(Oypfh7 & Uypfh7));
+ assign Uypfh7 = (Azpfh7 & Gzpfh7);
+ assign Gzpfh7 = (Mzpfh7 & Szpfh7);
+ assign Szpfh7 = (Yzpfh7 & E0qfh7);
+ assign Yzpfh7 = (K0qfh7 & Q0qfh7);
+ assign Mzpfh7 = (W0qfh7 & C1qfh7);
+ assign Azpfh7 = (I1qfh7 & O1qfh7);
+ assign I1qfh7 = (U1qfh7 & A2qfh7);
+ assign U1qfh7 = (~(G2qfh7 & M2qfh7));
+ assign Oypfh7 = (S2qfh7 & Y2qfh7);
+ assign Y2qfh7 = (E3qfh7 & K3qfh7);
+ assign K3qfh7 = (Q3qfh7 & W3qfh7);
+ assign E3qfh7 = (C4qfh7 & Expfh7);
+ assign Expfh7 = (I4qfh7 & O4qfh7);
+ assign O4qfh7 = (U4qfh7 & A5qfh7);
+ assign U4qfh7 = (G5qfh7 & M5qfh7);
+ assign I4qfh7 = (S5qfh7 & Y5qfh7);
+ assign S5qfh7 = (E6qfh7 & K6qfh7);
+ assign S2qfh7 = (Q6qfh7 & W6qfh7);
+ assign W6qfh7 = (C7qfh7 & I7qfh7);
+ assign Q6qfh7 = (O7qfh7 & U7qfh7);
+ assign HRDATA[7] = (~(A8qfh7 & G8qfh7));
+ assign G8qfh7 = (M8qfh7 & S8qfh7);
+ assign S8qfh7 = (Y8qfh7 & E9qfh7);
+ assign Y8qfh7 = (K9qfh7 & Q9qfh7);
+ assign M8qfh7 = (Iypfh7 & W9qfh7);
+ assign A8qfh7 = (Caqfh7 & Iaqfh7);
+ assign Iaqfh7 = (Oaqfh7 & Uaqfh7);
+ assign Caqfh7 = (Abqfh7 & Gbqfh7);
+ assign HRDATA[6] = (~(Mbqfh7 & Sbqfh7));
+ assign Sbqfh7 = (Ybqfh7 & Ecqfh7);
+ assign Ecqfh7 = (Kcqfh7 & E6qfh7);
+ assign Kcqfh7 = (Qcqfh7 & Q0qfh7);
+ assign Ybqfh7 = (Wcqfh7 & Cdqfh7);
+ assign Mbqfh7 = (Idqfh7 & Odqfh7);
+ assign Odqfh7 = (Udqfh7 & Aeqfh7);
+ assign Udqfh7 = (Geqfh7 & Meqfh7);
+ assign Idqfh7 = (Seqfh7 & Yeqfh7);
+ assign HRDATA[5] = (~(Efqfh7 & Kfqfh7));
+ assign Kfqfh7 = (Qfqfh7 & Wfqfh7);
+ assign Wfqfh7 = (Cgqfh7 & Igqfh7);
+ assign Cgqfh7 = (Ogqfh7 & Ugqfh7);
+ assign Qfqfh7 = (Ahqfh7 & Ghqfh7);
+ assign Ahqfh7 = (Mhqfh7 & Shqfh7);
+ assign Mhqfh7 = (~(Yhqfh7 & Eiqfh7));
+ assign Efqfh7 = (Kiqfh7 & Qiqfh7);
+ assign Qiqfh7 = (Wiqfh7 & Aeqfh7);
+ assign Wiqfh7 = (Cjqfh7 & Ijqfh7);
+ assign Kiqfh7 = (Ojqfh7 & Ujqfh7);
+ assign Ojqfh7 = (Akqfh7 & Gkqfh7);
+ assign HRDATA[4] = (~(Mkqfh7 & Skqfh7));
+ assign Skqfh7 = (Ykqfh7 & Elqfh7);
+ assign Elqfh7 = (Klqfh7 & Qlqfh7);
+ assign Qlqfh7 = (Wlqfh7 & M5qfh7);
+ assign Klqfh7 = (Q0qfh7 & Cmqfh7);
+ assign Ykqfh7 = (Imqfh7 & Omqfh7);
+ assign Imqfh7 = (K0qfh7 & Qcqfh7);
+ assign Mkqfh7 = (Umqfh7 & Anqfh7);
+ assign Anqfh7 = (Gnqfh7 & Iypfh7);
+ assign Gnqfh7 = (Mnqfh7 & Snqfh7);
+ assign Umqfh7 = (Ynqfh7 & Eoqfh7);
+ assign Ynqfh7 = (Akqfh7 & Koqfh7);
+ assign Akqfh7 = (Qoqfh7 & Woqfh7);
+ assign Woqfh7 = (Cpqfh7 & Ipqfh7);
+ assign Ipqfh7 = (G5qfh7 & Opqfh7);
+ assign Cpqfh7 = (Upqfh7 & Aqqfh7);
+ assign Qoqfh7 = (Gqqfh7 & Mqqfh7);
+ assign Mqqfh7 = (Uaqfh7 & Sqqfh7);
+ assign Gqqfh7 = (Geqfh7 & Yqqfh7);
+ assign Geqfh7 = (Erqfh7 & Krqfh7);
+ assign Krqfh7 = (Qrqfh7 & Wrqfh7);
+ assign Qrqfh7 = (Csqfh7 & Isqfh7);
+ assign Erqfh7 = (Osqfh7 & Usqfh7);
+ assign Osqfh7 = (Atqfh7 & Q3qfh7);
+ assign HRDATA[3] = (~(Gtqfh7 & Mtqfh7));
+ assign Mtqfh7 = (Stqfh7 & Ytqfh7);
+ assign Ytqfh7 = (Euqfh7 & Kuqfh7);
+ assign Kuqfh7 = (Quqfh7 & Wuqfh7);
+ assign Euqfh7 = (Ugqfh7 & Awpfh7);
+ assign Stqfh7 = (Cvqfh7 & Ivqfh7);
+ assign Ivqfh7 = (Ovqfh7 & Upqfh7);
+ assign Ovqfh7 = (~(Uvqfh7 & Awqfh7));
+ assign Cvqfh7 = (Aeqfh7 & Iypfh7);
+ assign Iypfh7 = (Gwqfh7 & Mwqfh7);
+ assign Mwqfh7 = (~(Eiqfh7 & Swqfh7));
+ assign Gwqfh7 = (~(Ywqfh7 & Exqfh7));
+ assign Aeqfh7 = (Kxqfh7 & Qxqfh7);
+ assign Qxqfh7 = (Wxqfh7 & Cyqfh7);
+ assign Cyqfh7 = (Iyqfh7 & Oyqfh7);
+ assign Wxqfh7 = (W0qfh7 & Uyqfh7);
+ assign Kxqfh7 = (Azqfh7 & Gzqfh7);
+ assign Gzqfh7 = (Mzqfh7 & Szqfh7);
+ assign Azqfh7 = (Koqfh7 & Yzqfh7);
+ assign Koqfh7 = (E0rfh7 & K0rfh7);
+ assign K0rfh7 = (Q0rfh7 & W0rfh7);
+ assign E0rfh7 = (Uvpfh7 & C1rfh7);
+ assign Uvpfh7 = (~(I1rfh7 & O1rfh7));
+ assign Gtqfh7 = (U1rfh7 & A2rfh7);
+ assign A2rfh7 = (G2rfh7 & M2rfh7);
+ assign M2rfh7 = (~(S2rfh7 | Y2rfh7));
+ assign G2rfh7 = (E3rfh7 & K3rfh7);
+ assign U1rfh7 = (Q3rfh7 & W3rfh7);
+ assign Q3rfh7 = (C4rfh7 & I4rfh7);
+ assign HRDATA[31] = (~(O4rfh7 & U4rfh7));
+ assign U4rfh7 = (A5rfh7 & G5rfh7);
+ assign G5rfh7 = (A5qfh7 & M5rfh7);
+ assign A5rfh7 = (S5rfh7 & C1rfh7);
+ assign O4rfh7 = (Y5rfh7 & E6rfh7);
+ assign E6rfh7 = (K6rfh7 & Q6rfh7);
+ assign Y5rfh7 = (W6rfh7 & C7rfh7);
+ assign HRDATA[30] = (~(I7rfh7 & O7rfh7));
+ assign O7rfh7 = (U7rfh7 & A8rfh7);
+ assign A8rfh7 = (G8rfh7 & M8rfh7);
+ assign G8rfh7 = (Usqfh7 & C1rfh7);
+ assign U7rfh7 = (S8rfh7 & Y8rfh7);
+ assign I7rfh7 = (E9rfh7 & K9rfh7);
+ assign K9rfh7 = (~(Q9rfh7 | W9rfh7));
+ assign E9rfh7 = (Carfh7 & Iarfh7);
+ assign HRDATA[2] = (~(Oarfh7 & Uarfh7));
+ assign Uarfh7 = (Abrfh7 & Gbrfh7);
+ assign Gbrfh7 = (Mbrfh7 & Sbrfh7);
+ assign Sbrfh7 = (Ybrfh7 & Uyqfh7);
+ assign Ybrfh7 = (~(Ecrfh7 | Kcrfh7));
+ assign Mbrfh7 = (Qupfh7 & Qcqfh7);
+ assign Abrfh7 = (Qcrfh7 & Wcrfh7);
+ assign Wcrfh7 = (C1qfh7 & Cdrfh7);
+ assign Qcrfh7 = (Idrfh7 & Odrfh7);
+ assign Oarfh7 = (Udrfh7 & Aerfh7);
+ assign Aerfh7 = (Gerfh7 & Merfh7);
+ assign Merfh7 = (Serfh7 & Yerfh7);
+ assign Serfh7 = (~(Ywqfh7 & Eiqfh7));
+ assign Gerfh7 = (Wrqfh7 & Efrfh7);
+ assign Efrfh7 = (~(Kfrfh7 & O1rfh7));
+ assign Udrfh7 = (Qfrfh7 & Wfrfh7);
+ assign Wfrfh7 = (Ujqfh7 & O7qfh7);
+ assign Ujqfh7 = (Cgrfh7 & Igrfh7);
+ assign Igrfh7 = (Ogrfh7 & Ugrfh7);
+ assign Ugrfh7 = (Ahrfh7 & Ghrfh7);
+ assign Ahrfh7 = (Mhrfh7 & Wupfh7);
+ assign Ogrfh7 = (Shrfh7 & E6qfh7);
+ assign E6qfh7 = (~(Eiqfh7 & Yhrfh7));
+ assign Shrfh7 = (~(Eirfh7 | Kirfh7));
+ assign Cgrfh7 = (Qirfh7 & Wirfh7);
+ assign Wirfh7 = (Cjrfh7 & Ijrfh7);
+ assign Cjrfh7 = (Ojrfh7 & Ujrfh7);
+ assign Qirfh7 = (~(Akrfh7 | Gkrfh7));
+ assign Qfrfh7 = (Mkrfh7 & I4rfh7);
+ assign I4rfh7 = (Skrfh7 & Ykrfh7);
+ assign Ykrfh7 = (Elrfh7 & Klrfh7);
+ assign Elrfh7 = (Qlrfh7 & Wlrfh7);
+ assign Skrfh7 = (Cmrfh7 & S5rfh7);
+ assign Cmrfh7 = (~(Imrfh7 & Uvqfh7));
+ assign Imrfh7 = (Omrfh7 & Umrfh7);
+ assign HRDATA[29] = (~(Anrfh7 & Gnrfh7));
+ assign Gnrfh7 = (Mnrfh7 & Snrfh7);
+ assign Snrfh7 = (Ynrfh7 & Eorfh7);
+ assign Eorfh7 = (Q9qfh7 & Korfh7);
+ assign Ynrfh7 = (Qorfh7 & K0qfh7);
+ assign Mnrfh7 = (Worfh7 & Cprfh7);
+ assign Cprfh7 = (~(Iprfh7 & Kfrfh7));
+ assign Worfh7 = (Sqqfh7 & Oprfh7);
+ assign Anrfh7 = (Uprfh7 & Aqrfh7);
+ assign Aqrfh7 = (Gqrfh7 & Yzqfh7);
+ assign Yzqfh7 = (C7qfh7 & Mqrfh7);
+ assign Mqrfh7 = (~(Sqrfh7 & Iprfh7));
+ assign C7qfh7 = (Kxpfh7 & Yqrfh7);
+ assign Yqrfh7 = (~(Errfh7 & Krrfh7));
+ assign Kxpfh7 = (Qrrfh7 & Wrrfh7);
+ assign Wrrfh7 = (~(Sqrfh7 & O1rfh7));
+ assign Qrrfh7 = (~(Uvqfh7 & Ywqfh7));
+ assign Gqrfh7 = (Csrfh7 & Isrfh7);
+ assign Isrfh7 = (~(Osrfh7 & Usrfh7));
+ assign Uprfh7 = (Atrfh7 & Gtrfh7);
+ assign Atrfh7 = (Mkrfh7 & Yeqfh7);
+ assign Mkrfh7 = (Mtrfh7 & Strfh7);
+ assign Strfh7 = (Ytrfh7 & Eurfh7);
+ assign Eurfh7 = (Kurfh7 & Qurfh7);
+ assign Qurfh7 = (Wurfh7 & Iyqfh7);
+ assign Kurfh7 = (W0qfh7 & Cvrfh7);
+ assign Ytrfh7 = (Ivrfh7 & Ovrfh7);
+ assign Mtrfh7 = (Uvrfh7 & Awrfh7);
+ assign Awrfh7 = (Gwrfh7 & Mwrfh7);
+ assign Mwrfh7 = (~(Eiqfh7 & Awqfh7));
+ assign Gwrfh7 = (Swrfh7 & Ywrfh7);
+ assign Swrfh7 = (~(Exrfh7 & Kxrfh7));
+ assign Uvrfh7 = (Qxrfh7 & Wxrfh7);
+ assign HRDATA[28] = (~(Cyrfh7 & Iyrfh7));
+ assign Iyrfh7 = (Oyrfh7 & Cvpfh7);
+ assign Cyrfh7 = (Uyrfh7 & W6rfh7);
+ assign W6rfh7 = (Azrfh7 & Gzrfh7);
+ assign Gzrfh7 = (Mzrfh7 & Wurfh7);
+ assign Mzrfh7 = (Korfh7 & Szrfh7);
+ assign Azrfh7 = (Yzrfh7 & E0sfh7);
+ assign Yzrfh7 = (M8rfh7 & Csrfh7);
+ assign M8rfh7 = (K0sfh7 & Q0sfh7);
+ assign Q0sfh7 = (W0sfh7 & C1sfh7);
+ assign C1sfh7 = (Awpfh7 & Q0qfh7);
+ assign W0sfh7 = (I1sfh7 & Csqfh7);
+ assign K0sfh7 = (O1sfh7 & Yqqfh7);
+ assign O1sfh7 = (Cypfh7 & W3qfh7);
+ assign HRDATA[27] = (~(U1sfh7 & A2sfh7));
+ assign A2sfh7 = (G2sfh7 & M2sfh7);
+ assign M2sfh7 = (S2sfh7 & Csqfh7);
+ assign S2sfh7 = (Ujrfh7 & Y2sfh7);
+ assign G2sfh7 = (E3sfh7 & Ijrfh7);
+ assign U1sfh7 = (K3sfh7 & Q3sfh7);
+ assign Q3sfh7 = (W3sfh7 & C4sfh7);
+ assign W3sfh7 = (~(I4sfh7 | O4sfh7));
+ assign I4sfh7 = (!U4sfh7);
+ assign K3sfh7 = (Uyrfh7 & S8rfh7);
+ assign S8rfh7 = (~(A5sfh7 | G5sfh7));
+ assign A5sfh7 = (~(S5rfh7 & M5sfh7));
+ assign Uyrfh7 = (S5sfh7 & Y5sfh7);
+ assign Y5sfh7 = (E6sfh7 & K6sfh7);
+ assign E6sfh7 = (Q6sfh7 & W6sfh7);
+ assign S5sfh7 = (~(C7sfh7 | I7sfh7));
+ assign HRDATA[26] = (~(O7sfh7 & U7sfh7));
+ assign U7sfh7 = (A8sfh7 & G8sfh7);
+ assign G8sfh7 = (M8sfh7 & S8sfh7);
+ assign M8sfh7 = (K6qfh7 & Quqfh7);
+ assign A8sfh7 = (Y8sfh7 & E9sfh7);
+ assign Y8sfh7 = (Q6sfh7 & Szqfh7);
+ assign O7sfh7 = (K9sfh7 & Q9sfh7);
+ assign Q9sfh7 = (~(W9sfh7 | Casfh7));
+ assign W9sfh7 = (~(Iasfh7 & Oasfh7));
+ assign K9sfh7 = (Uasfh7 & Absfh7);
+ assign Uasfh7 = (~(Gbsfh7 | Mbsfh7));
+ assign HRDATA[25] = (~(Sbsfh7 & Ybsfh7));
+ assign Ybsfh7 = (Ecsfh7 & Kcsfh7);
+ assign Kcsfh7 = (Qcsfh7 & Oyrfh7);
+ assign Qcsfh7 = (K9qfh7 & S8sfh7);
+ assign Ecsfh7 = (Wcsfh7 & Cdsfh7);
+ assign Wcsfh7 = (Idsfh7 & Odsfh7);
+ assign Sbsfh7 = (Udsfh7 & Aesfh7);
+ assign Aesfh7 = (Gesfh7 & Iarfh7);
+ assign Iarfh7 = (Mesfh7 & Sesfh7);
+ assign Sesfh7 = (Yesfh7 & Qupfh7);
+ assign Yesfh7 = (Cvpfh7 & Efsfh7);
+ assign Mesfh7 = (~(Mbsfh7 | Casfh7));
+ assign Gesfh7 = (Yeqfh7 & Kfsfh7);
+ assign Udsfh7 = (Qfsfh7 & Wfsfh7);
+ assign Qfsfh7 = (Cgsfh7 & Wxrfh7);
+ assign HRDATA[24] = (~(Igsfh7 & Ogsfh7));
+ assign Ogsfh7 = (Ugsfh7 & Ahsfh7);
+ assign Ahsfh7 = (Ghsfh7 & Mhsfh7);
+ assign Mhsfh7 = (M5sfh7 & Cvpfh7);
+ assign Ghsfh7 = (G5qfh7 & Awpfh7);
+ assign Ugsfh7 = (Shsfh7 & Yhsfh7);
+ assign Yhsfh7 = (Eisfh7 & Oprfh7);
+ assign Shsfh7 = (Yerfh7 & Idrfh7);
+ assign Igsfh7 = (Kisfh7 & Qisfh7);
+ assign Qisfh7 = (Wisfh7 & Cjsfh7);
+ assign Cjsfh7 = (Ijsfh7 & A2qfh7);
+ assign A2qfh7 = (Ojsfh7 | Ujsfh7);
+ assign Wisfh7 = (Gbqfh7 & Aksfh7);
+ assign Gbqfh7 = (Gksfh7 & Mksfh7);
+ assign Gksfh7 = (M5qfh7 & Sksfh7);
+ assign M5qfh7 = (!Ecrfh7);
+ assign Ecrfh7 = (~(Yksfh7 | Elsfh7));
+ assign Yksfh7 = (!Kfrfh7);
+ assign Kisfh7 = (Klsfh7 & Qlsfh7);
+ assign Qlsfh7 = (Cgsfh7 & Absfh7);
+ assign Absfh7 = (Wlsfh7 & Cmsfh7);
+ assign Cmsfh7 = (Imsfh7 & Omsfh7);
+ assign Omsfh7 = (Umsfh7 & Mzqfh7);
+ assign Umsfh7 = (Ogqfh7 & Korfh7);
+ assign Imsfh7 = (Q6rfh7 & Ijrfh7);
+ assign Wlsfh7 = (Ansfh7 & Gnsfh7);
+ assign Gnsfh7 = (Mnsfh7 & C7rfh7);
+ assign Mnsfh7 = (Yqqfh7 & K6rfh7);
+ assign Ansfh7 = (~(Snsfh7 | Ynsfh7));
+ assign Cgsfh7 = (Eosfh7 & Kosfh7);
+ assign Kosfh7 = (Qosfh7 & Q0qfh7);
+ assign Eosfh7 = (Wosfh7 & U4sfh7);
+ assign Klsfh7 = (Cpsfh7 & Ipsfh7);
+ assign HRDATA[23] = (~(Opsfh7 & Upsfh7));
+ assign Upsfh7 = (Aqsfh7 & Gqsfh7);
+ assign Gqsfh7 = (Mqsfh7 & Idsfh7);
+ assign Mqsfh7 = (Sqsfh7 & Klrfh7);
+ assign Aqsfh7 = (Yqsfh7 & Ersfh7);
+ assign Ersfh7 = (~(Krsfh7 & Usrfh7));
+ assign Opsfh7 = (Qrsfh7 & Wrsfh7);
+ assign Wrsfh7 = (Gkqfh7 & Wcqfh7);
+ assign Wcqfh7 = (Cssfh7 & Issfh7);
+ assign Cssfh7 = (W3qfh7 & Mhrfh7);
+ assign Gkqfh7 = (Ossfh7 & Ussfh7);
+ assign Ussfh7 = (Q9qfh7 & Atsfh7);
+ assign Ossfh7 = (Eisfh7 & Gtsfh7);
+ assign Qrsfh7 = (Mtsfh7 & K3rfh7);
+ assign K3rfh7 = (Stsfh7 & Ytsfh7);
+ assign Stsfh7 = (Ojrfh7 & Csqfh7);
+ assign HRDATA[22] = (~(Eusfh7 & Kusfh7));
+ assign Kusfh7 = (Qusfh7 & Wusfh7);
+ assign Wusfh7 = (Cvsfh7 & Ivsfh7);
+ assign Cvsfh7 = (Quqfh7 & Iyqfh7);
+ assign Qusfh7 = (Q6sfh7 & Ovsfh7);
+ assign Eusfh7 = (Uvsfh7 & Awsfh7);
+ assign Awsfh7 = (Gwsfh7 & Wfsfh7);
+ assign Wfsfh7 = (Mwsfh7 & Swsfh7);
+ assign Swsfh7 = (Ywsfh7 & Mzqfh7);
+ assign Ywsfh7 = (Ujrfh7 & W6sfh7);
+ assign Mwsfh7 = (K6rfh7 & Ijrfh7);
+ assign Gwsfh7 = (Issfh7 & Ovrfh7);
+ assign Issfh7 = (Exsfh7 & Kxsfh7);
+ assign Kxsfh7 = (E9qfh7 & Qxsfh7);
+ assign Exsfh7 = (Kfsfh7 & C7rfh7);
+ assign Uvsfh7 = (Wxsfh7 & Cpsfh7);
+ assign HRDATA[21] = (~(Cysfh7 & Iysfh7));
+ assign Iysfh7 = (Oysfh7 & Uysfh7);
+ assign Uysfh7 = (Azsfh7 & Gzsfh7);
+ assign Gzsfh7 = (Mzsfh7 & Quqfh7);
+ assign Mzsfh7 = (Mhrfh7 & M5rfh7);
+ assign Azsfh7 = (Qupfh7 & Atsfh7);
+ assign Oysfh7 = (Szsfh7 & Yzsfh7);
+ assign Yzsfh7 = (E0tfh7 & K0tfh7);
+ assign Szsfh7 = (Oprfh7 & Shqfh7);
+ assign Cysfh7 = (Q0tfh7 & W0tfh7);
+ assign W0tfh7 = (C1tfh7 & I1tfh7);
+ assign I1tfh7 = (Ijrfh7 & Ojrfh7);
+ assign Q0tfh7 = (O1tfh7 & U1tfh7);
+ assign U1tfh7 = (A2tfh7 & Sqsfh7);
+ assign A2tfh7 = (~(G2tfh7 & M2tfh7));
+ assign O1tfh7 = (S2tfh7 & Iasfh7);
+ assign HRDATA[20] = (~(Y2tfh7 & E3tfh7));
+ assign E3tfh7 = (K3tfh7 & Q3tfh7);
+ assign Q3tfh7 = (W3tfh7 & C4tfh7);
+ assign W3tfh7 = (Qcqfh7 & Korfh7);
+ assign K3tfh7 = (I4tfh7 & E9sfh7);
+ assign I4tfh7 = (Q6rfh7 & Qorfh7);
+ assign Y2tfh7 = (O4tfh7 & U4tfh7);
+ assign U4tfh7 = (A5tfh7 & Ipsfh7);
+ assign Ipsfh7 = (G5tfh7 & Snqfh7);
+ assign G5tfh7 = (Upqfh7 & Gtsfh7);
+ assign A5tfh7 = (~(Snsfh7 | M5tfh7));
+ assign O4tfh7 = (S5tfh7 & Y5tfh7);
+ assign S5tfh7 = (E6tfh7 & S2tfh7);
+ assign S2tfh7 = (K6tfh7 & Q6tfh7);
+ assign Q6tfh7 = (W6tfh7 & C7tfh7);
+ assign C7tfh7 = (I7tfh7 & O7tfh7);
+ assign O7tfh7 = (U7tfh7 & W6sfh7);
+ assign I7tfh7 = (A8tfh7 & M5sfh7);
+ assign W6tfh7 = (G8tfh7 & M8tfh7);
+ assign M8tfh7 = (A5qfh7 & Ivsfh7);
+ assign G8tfh7 = (Csqfh7 & Q9qfh7);
+ assign K6tfh7 = (S8tfh7 & Y8tfh7);
+ assign Y8tfh7 = (E9tfh7 & K9tfh7);
+ assign K9tfh7 = (S5rfh7 & Klrfh7);
+ assign E9tfh7 = (~(Q9tfh7 | W9tfh7));
+ assign S8tfh7 = (Catfh7 & Iatfh7);
+ assign Iatfh7 = (Yqsfh7 & Idsfh7);
+ assign Catfh7 = (Oatfh7 & Cpsfh7);
+ assign Cpsfh7 = (Uatfh7 & Abtfh7);
+ assign Abtfh7 = (Gbtfh7 & Mbtfh7);
+ assign Mbtfh7 = (C1rfh7 & Wlrfh7);
+ assign Gbtfh7 = (Sbtfh7 & Ybtfh7);
+ assign Uatfh7 = (Ectfh7 & Kctfh7);
+ assign Kctfh7 = (W3qfh7 & Qctfh7);
+ assign Ectfh7 = (Mtsfh7 & W3rfh7);
+ assign HRDATA[1] = (~(Wctfh7 & Cdtfh7));
+ assign Cdtfh7 = (Idtfh7 & Odtfh7);
+ assign Odtfh7 = (Udtfh7 & Aetfh7);
+ assign Aetfh7 = (Getfh7 & Atsfh7);
+ assign Getfh7 = (Cmqfh7 & W6sfh7);
+ assign Udtfh7 = (Q0qfh7 & Uyqfh7);
+ assign Idtfh7 = (Metfh7 & Setfh7);
+ assign Setfh7 = (Yetfh7 & Isqfh7);
+ assign Yetfh7 = (E0qfh7 & G5qfh7);
+ assign Metfh7 = (Aqqfh7 & Mzqfh7);
+ assign Wctfh7 = (Eftfh7 & Kftfh7);
+ assign Kftfh7 = (Qftfh7 & Wftfh7);
+ assign Wftfh7 = (Cgtfh7 & Ovrfh7);
+ assign Cgtfh7 = (~(Akrfh7 | Igtfh7));
+ assign Qftfh7 = (E9sfh7 & Ywrfh7);
+ assign Eftfh7 = (Ogtfh7 & Ugtfh7);
+ assign Ugtfh7 = (Ahtfh7 & C4rfh7);
+ assign C4rfh7 = (Ghtfh7 & Mhtfh7);
+ assign Mhtfh7 = (Shtfh7 & Yhtfh7);
+ assign Yhtfh7 = (Eitfh7 & Ghrfh7);
+ assign Eitfh7 = (~(Kitfh7 | Kcrfh7));
+ assign Shtfh7 = (Qitfh7 & Snqfh7);
+ assign Qitfh7 = (~(Witfh7 | Cjtfh7));
+ assign Ghtfh7 = (Ijtfh7 & Ojtfh7);
+ assign Ojtfh7 = (Ujtfh7 & Aktfh7);
+ assign Aktfh7 = (~(Uvqfh7 & Yhrfh7));
+ assign Ujtfh7 = (Gktfh7 & Odsfh7);
+ assign Gktfh7 = (~(Sqrfh7 & Mktfh7));
+ assign Ijtfh7 = (Sktfh7 & Yktfh7);
+ assign Sktfh7 = (K6rfh7 & Wrqfh7);
+ assign Ahtfh7 = (~(M5tfh7 | Eltfh7));
+ assign Ogtfh7 = (Kltfh7 & Wxrfh7);
+ assign HRDATA[19] = (~(Qltfh7 & Wltfh7));
+ assign Wltfh7 = (Cmtfh7 & Imtfh7);
+ assign Imtfh7 = (Omtfh7 & C1rfh7);
+ assign Omtfh7 = (Qorfh7 & Umtfh7);
+ assign Cmtfh7 = (Antfh7 & Gntfh7);
+ assign Gntfh7 = (~(Mntfh7 & Sntfh7));
+ assign Sntfh7 = (~(Yntfh7 & Eotfh7));
+ assign Antfh7 = (Kotfh7 & Eisfh7);
+ assign Qltfh7 = (Qotfh7 & Wotfh7);
+ assign Wotfh7 = (Cptfh7 & E6tfh7);
+ assign Cptfh7 = (Iptfh7 & I7qfh7);
+ assign Qotfh7 = (Optfh7 & Uptfh7);
+ assign HRDATA[18] = (~(Aqtfh7 & Gqtfh7));
+ assign Gqtfh7 = (Mqtfh7 & Sqtfh7);
+ assign Sqtfh7 = (Yqtfh7 & Ertfh7);
+ assign Ertfh7 = (A8tfh7 & Iyqfh7);
+ assign Yqtfh7 = (Omqfh7 & C4tfh7);
+ assign Mqtfh7 = (C1tfh7 & Krtfh7);
+ assign Krtfh7 = (Klrfh7 & Oyrfh7);
+ assign C1tfh7 = (Qrtfh7 & K6sfh7);
+ assign Aqtfh7 = (Wrtfh7 & Cstfh7);
+ assign Cstfh7 = (Istfh7 & Ostfh7);
+ assign Ostfh7 = (Yerfh7 & Ustfh7);
+ assign Istfh7 = (Ovpfh7 & Attfh7);
+ assign Ovpfh7 = (Gttfh7 & K6rfh7);
+ assign Gttfh7 = (Ogqfh7 & Cdrfh7);
+ assign Wrtfh7 = (Mttfh7 & Sttfh7);
+ assign Mttfh7 = (Uptfh7 & Uaqfh7);
+ assign Uptfh7 = (Yttfh7 & Eutfh7);
+ assign Eutfh7 = (Kutfh7 & Ijrfh7);
+ assign Kutfh7 = (Qcqfh7 & Cvpfh7);
+ assign Yttfh7 = (W3qfh7 & Odrfh7);
+ assign Odrfh7 = (!Qutfh7);
+ assign HRDATA[17] = (~(Wutfh7 & Cvtfh7));
+ assign Cvtfh7 = (Ivtfh7 & Ovtfh7);
+ assign Ovtfh7 = (Uvtfh7 & Awtfh7);
+ assign Awtfh7 = (Ivsfh7 & W6sfh7);
+ assign Uvtfh7 = (Szqfh7 & C1qfh7);
+ assign Ivtfh7 = (Gwtfh7 & Mwtfh7);
+ assign Mwtfh7 = (Ojrfh7 & Q0rfh7);
+ assign Gwtfh7 = (~(Swtfh7 | Akrfh7));
+ assign Akrfh7 = (~(Ywtfh7 | Extfh7));
+ assign Wutfh7 = (Kxtfh7 & Qxtfh7);
+ assign Qxtfh7 = (Wxtfh7 & Cytfh7);
+ assign Cytfh7 = (~(Iytfh7 | Oytfh7));
+ assign Wxtfh7 = (Uytfh7 & Attfh7);
+ assign Kxtfh7 = (Aztfh7 & Gztfh7);
+ assign Gztfh7 = (Oatfh7 & Wosfh7);
+ assign Wosfh7 = (Mztfh7 & Cdrfh7);
+ assign Mztfh7 = (Sztfh7 & M5rfh7);
+ assign Aztfh7 = (Optfh7 & Y5tfh7);
+ assign Y5tfh7 = (Yztfh7 & E0ufh7);
+ assign E0ufh7 = (K0ufh7 & Mzqfh7);
+ assign K0ufh7 = (Ovsfh7 & Oyqfh7);
+ assign Optfh7 = (Q0ufh7 & W0ufh7);
+ assign W0ufh7 = (C1ufh7 & I1ufh7);
+ assign I1ufh7 = (O1ufh7 & Mhrfh7);
+ assign O1ufh7 = (Wupfh7 & U1ufh7);
+ assign C1ufh7 = (Csqfh7 & Atsfh7);
+ assign Q0ufh7 = (A2ufh7 & G2ufh7);
+ assign G2ufh7 = (M2ufh7 & K6rfh7);
+ assign M2ufh7 = (Csrfh7 & Igqfh7);
+ assign A2ufh7 = (~(C7sfh7 | S2ufh7));
+ assign C7sfh7 = (~(Y2ufh7 & E3ufh7));
+ assign E3ufh7 = (Idsfh7 & W0rfh7);
+ assign Y2ufh7 = (Y5qfh7 & E9sfh7);
+ assign HRDATA[16] = (~(K3ufh7 & Q3ufh7));
+ assign Q3ufh7 = (W3ufh7 & C4ufh7);
+ assign C4ufh7 = (I4ufh7 & O4ufh7);
+ assign O4ufh7 = (Mhrfh7 & Umtfh7);
+ assign I4ufh7 = (Qosfh7 & Atsfh7);
+ assign W3ufh7 = (U4ufh7 & O1qfh7);
+ assign U4ufh7 = (~(O4sfh7 | A5ufh7));
+ assign K3ufh7 = (G5ufh7 & M5ufh7);
+ assign M5ufh7 = (S5ufh7 & Y5ufh7);
+ assign Y5ufh7 = (E6ufh7 & K6ufh7);
+ assign S5ufh7 = (Abqfh7 & Q6ufh7);
+ assign G5ufh7 = (W6ufh7 & C7ufh7);
+ assign C7ufh7 = (Wxsfh7 & I7ufh7);
+ assign Wxsfh7 = (O7ufh7 & U7ufh7);
+ assign U7ufh7 = (A8ufh7 & G8ufh7);
+ assign G8ufh7 = (M8ufh7 & S8ufh7);
+ assign S8ufh7 = (A8tfh7 & Cvpfh7);
+ assign M8ufh7 = (Csqfh7 & Y2sfh7);
+ assign A8ufh7 = (Y8ufh7 & Sqsfh7);
+ assign Y8ufh7 = (Oyrfh7 & E9ufh7);
+ assign O7ufh7 = (K9ufh7 & Q9ufh7);
+ assign Q9ufh7 = (W9ufh7 & Caufh7);
+ assign W9ufh7 = (E9sfh7 & Idsfh7);
+ assign K9ufh7 = (~(Iaufh7 | Oaufh7));
+ assign Iaufh7 = (~(Iasfh7 & Aksfh7));
+ assign W6ufh7 = (Uaufh7 & Sttfh7);
+ assign Sttfh7 = (Abufh7 & Gbufh7);
+ assign Gbufh7 = (Mbufh7 & W0rfh7);
+ assign Mbufh7 = (Ghrfh7 & U1ufh7);
+ assign Abufh7 = (Sbufh7 & Mtsfh7);
+ assign Mtsfh7 = (Ybufh7 & Ecufh7);
+ assign Ecufh7 = (Igqfh7 & Kcufh7);
+ assign Ybufh7 = (Oasfh7 & Csrfh7);
+ assign Sbufh7 = (Qcufh7 & K9qfh7);
+ assign Qcufh7 = (~(Yhrfh7 & Mntfh7));
+ assign HRDATA[15] = (~(Wcufh7 & Cdufh7));
+ assign Cdufh7 = (Idufh7 & Odufh7);
+ assign Odufh7 = (Udufh7 & C1rfh7);
+ assign Udufh7 = (E0tfh7 & Csqfh7);
+ assign Idufh7 = (Aeufh7 & Cjqfh7);
+ assign Aeufh7 = (Y5qfh7 & Klrfh7);
+ assign Wcufh7 = (Geufh7 & Meufh7);
+ assign Meufh7 = (Seufh7 & E0sfh7);
+ assign Seufh7 = (Oaqfh7 & Yqqfh7);
+ assign Oaqfh7 = (Yeufh7 & C7rfh7);
+ assign Yeufh7 = (Usqfh7 & Mzqfh7);
+ assign Geufh7 = (Efufh7 & Kfufh7);
+ assign HRDATA[14] = (~(Qfufh7 & Wfufh7));
+ assign Wfufh7 = (Cgufh7 & Igufh7);
+ assign Igufh7 = (Ogufh7 & U4sfh7);
+ assign Ogufh7 = (Ghrfh7 & Wurfh7);
+ assign Cgufh7 = (Ugufh7 & Abqfh7);
+ assign Abqfh7 = (Ahufh7 & Cjqfh7);
+ assign Ahufh7 = (Szqfh7 & Awpfh7);
+ assign Awpfh7 = (!Kirfh7);
+ assign Kirfh7 = (~(Ghufh7 | Mhufh7));
+ assign Ugufh7 = (U7qfh7 & Idsfh7);
+ assign U7qfh7 = (Shufh7 & Yhufh7);
+ assign Yhufh7 = (Eiufh7 & Kiufh7);
+ assign Kiufh7 = (Qiufh7 & Wiufh7);
+ assign Wiufh7 = (Cjufh7 & Iyqfh7);
+ assign Cjufh7 = (Cvpfh7 & Wuqfh7);
+ assign Cvpfh7 = (!Kitfh7);
+ assign Kitfh7 = (~(Ijufh7 | Ojufh7));
+ assign Eiufh7 = (Ujufh7 & Akufh7);
+ assign Akufh7 = (Qorfh7 & Gkufh7);
+ assign Ujufh7 = (Isqfh7 & Ujrfh7);
+ assign Shufh7 = (Mkufh7 & Skufh7);
+ assign Skufh7 = (Qxrfh7 & Ykufh7);
+ assign Ykufh7 = (Elufh7 & Atqfh7);
+ assign Elufh7 = (Wrqfh7 & Csqfh7);
+ assign Csqfh7 = (~(Klufh7 & Omrfh7));
+ assign Qxrfh7 = (Uaqfh7 & Usqfh7);
+ assign Usqfh7 = (Qlufh7 & Wlufh7);
+ assign Wlufh7 = (Yqsfh7 & Szrfh7);
+ assign Qlufh7 = (Cmufh7 & Uytfh7);
+ assign Mkufh7 = (Imufh7 & Omufh7);
+ assign Omufh7 = (Oasfh7 & Yqqfh7);
+ assign Yqqfh7 = (~(Umufh7 | A5ufh7));
+ assign A5ufh7 = (~(Ijufh7 | Anufh7));
+ assign Umufh7 = (~(Gnufh7 | Mnufh7));
+ assign Imufh7 = (Aksfh7 & C7rfh7);
+ assign Qfufh7 = (Snufh7 & Ynufh7);
+ assign Ynufh7 = (Eoufh7 & Wxrfh7);
+ assign Wxrfh7 = (!Gbsfh7);
+ assign Gbsfh7 = (~(Opqfh7 & W0rfh7));
+ assign Eoufh7 = (~(G5sfh7 | Casfh7));
+ assign Casfh7 = (~(Koufh7 & Qoufh7));
+ assign Qoufh7 = (Woufh7 & Cpufh7);
+ assign Cpufh7 = (Ipufh7 & Ybtfh7);
+ assign Ipufh7 = (Shqfh7 & G5qfh7);
+ assign Woufh7 = (Opufh7 & Sbtfh7);
+ assign Opufh7 = (Idrfh7 & Klrfh7);
+ assign Koufh7 = (Upufh7 & Aqufh7);
+ assign Aqufh7 = (Gqufh7 & Q3qfh7);
+ assign Gqufh7 = (Caufh7 & Mqufh7);
+ assign Upufh7 = (Squfh7 & W3rfh7);
+ assign Squfh7 = (Ytsfh7 & Csrfh7);
+ assign G5sfh7 = (~(Yqufh7 & Erufh7));
+ assign Erufh7 = (Krufh7 & Qrufh7);
+ assign Qrufh7 = (Cdrfh7 & A5qfh7);
+ assign Krufh7 = (Oprfh7 & K9qfh7);
+ assign Yqufh7 = (Wrufh7 & Csufh7);
+ assign Csufh7 = (~(Oaufh7 | Isufh7));
+ assign Oaufh7 = (~(Osufh7 & Usufh7));
+ assign Usufh7 = (Ogqfh7 & Cvrfh7);
+ assign Osufh7 = (Ywrfh7 & W0qfh7);
+ assign Wrufh7 = (~(Atufh7 | S2ufh7));
+ assign S2ufh7 = (~(Gtufh7 & Mtufh7));
+ assign Mtufh7 = (K0qfh7 & Sksfh7);
+ assign Gtufh7 = (Ovrfh7 & Ustfh7);
+ assign Snufh7 = (Stufh7 & Ytufh7);
+ assign HRDATA[13] = (~(Euufh7 & Kuufh7));
+ assign Kuufh7 = (Quufh7 & Wuufh7);
+ assign Wuufh7 = (Cvufh7 & U7tfh7);
+ assign U7tfh7 = (Iyqfh7 & Sksfh7);
+ assign Cvufh7 = (Gkufh7 & Szrfh7);
+ assign Quufh7 = (Ivufh7 & Ovufh7);
+ assign Ovufh7 = (Ybtfh7 & K9qfh7);
+ assign Ivufh7 = (K6rfh7 & K6sfh7);
+ assign K6rfh7 = (Uvufh7 & Cjqfh7);
+ assign Uvufh7 = (Yqsfh7 & Q9qfh7);
+ assign Euufh7 = (Awufh7 & Gwufh7);
+ assign Gwufh7 = (Mwufh7 & Swufh7);
+ assign Swufh7 = (I7qfh7 & Cypfh7);
+ assign I7qfh7 = (Ywufh7 & Exufh7);
+ assign Exufh7 = (E9ufh7 & Y2sfh7);
+ assign Ywufh7 = (I1sfh7 & E0tfh7);
+ assign Mwufh7 = (W3rfh7 & Kfsfh7);
+ assign Kfsfh7 = (!Ynsfh7);
+ assign W3rfh7 = (Kxufh7 & Qxufh7);
+ assign Qxufh7 = (~(Wxufh7 & Usrfh7));
+ assign Kxufh7 = (~(Sqrfh7 & Omrfh7));
+ assign Awufh7 = (Cyufh7 & Iyufh7);
+ assign Iyufh7 = (Oatfh7 & Gtrfh7);
+ assign Gtrfh7 = (Oyufh7 & Uyufh7);
+ assign Uyufh7 = (Azufh7 & Gzufh7);
+ assign Gzufh7 = (Mzufh7 & S8sfh7);
+ assign Mzufh7 = (K6qfh7 & W6sfh7);
+ assign K6qfh7 = (~(Klufh7 & M2qfh7));
+ assign Azufh7 = (Odsfh7 & Shqfh7);
+ assign Oyufh7 = (Szufh7 & Yzufh7);
+ assign Yzufh7 = (E0vfh7 & Aksfh7);
+ assign E0vfh7 = (U4sfh7 & Q6rfh7);
+ assign Q6rfh7 = (!I7sfh7);
+ assign I7sfh7 = (Omrfh7 & K0vfh7);
+ assign Szufh7 = (Carfh7 & E0sfh7);
+ assign E0sfh7 = (Q0vfh7 & W0vfh7);
+ assign W0vfh7 = (C1vfh7 & I1vfh7);
+ assign I1vfh7 = (O1vfh7 & Szqfh7);
+ assign O1vfh7 = (Igqfh7 & Quqfh7);
+ assign C1vfh7 = (U1vfh7 & Cdqfh7);
+ assign Q0vfh7 = (A2vfh7 & G2vfh7);
+ assign G2vfh7 = (Ytsfh7 & Ustfh7);
+ assign A2vfh7 = (~(Isufh7 | Snsfh7));
+ assign Snsfh7 = (~(M2vfh7 & S2vfh7));
+ assign S2vfh7 = (Y2vfh7 & U1ufh7);
+ assign M2vfh7 = (E3vfh7 & Uyqfh7);
+ assign Carfh7 = (K3vfh7 & Q3vfh7);
+ assign Q3vfh7 = (W3vfh7 & C4vfh7);
+ assign C4vfh7 = (O1qfh7 & Ijrfh7);
+ assign O1qfh7 = (Gtsfh7 & I4vfh7);
+ assign I4vfh7 = (O4vfh7 | U4vfh7);
+ assign Gtsfh7 = (O4vfh7 | Elsfh7);
+ assign W3vfh7 = (Eisfh7 & Oyrfh7);
+ assign Eisfh7 = (Gnufh7 | Extfh7);
+ assign K3vfh7 = (A5vfh7 & G5vfh7);
+ assign G5vfh7 = (M5vfh7 & Kotfh7);
+ assign Kotfh7 = (S5vfh7 | Y5vfh7);
+ assign M5vfh7 = (~(O4sfh7 | Qutfh7));
+ assign O4sfh7 = (Klufh7 & E6vfh7);
+ assign A5vfh7 = (Iasfh7 & Y5qfh7);
+ assign Y5qfh7 = (!M5tfh7);
+ assign M5tfh7 = (~(K6vfh7 & Ugqfh7));
+ assign Ugqfh7 = (~(Wxufh7 & Mntfh7));
+ assign K6vfh7 = (~(Eirfh7 | Q6vfh7));
+ assign Eirfh7 = (~(O4vfh7 | W6vfh7));
+ assign Iasfh7 = (E3sfh7 & C7vfh7);
+ assign C7vfh7 = (Isqfh7 & Qlrfh7);
+ assign E3sfh7 = (Q0rfh7 & Aqqfh7);
+ assign Oatfh7 = (I7vfh7 & Ujrfh7);
+ assign I7vfh7 = (W0qfh7 & Efsfh7);
+ assign W0qfh7 = (O7vfh7 | U4vfh7);
+ assign Cyufh7 = (Ytufh7 & Kfufh7);
+ assign Kfufh7 = (U7vfh7 & A8vfh7);
+ assign A8vfh7 = (S5rfh7 & Omqfh7);
+ assign S5rfh7 = (~(G8vfh7 & M8vfh7));
+ assign U7vfh7 = (Oasfh7 & S8vfh7);
+ assign Oasfh7 = (Y8vfh7 & E9vfh7);
+ assign E9vfh7 = (~(Eiqfh7 & K9vfh7));
+ assign Eiqfh7 = (!Ojsfh7);
+ assign Ojsfh7 = (~(Q9vfh7 & Ovwfh7[9]));
+ assign Q9vfh7 = (Ovwfh7[8] & Ovwfh7[7]);
+ assign Y8vfh7 = (~(G8vfh7 & Usrfh7));
+ assign Ytufh7 = (W9vfh7 & Cavfh7);
+ assign Cavfh7 = (Q6sfh7 & Wupfh7);
+ assign W9vfh7 = (Y8rfh7 & E9sfh7);
+ assign E9sfh7 = (Iavfh7 | Oavfh7);
+ assign Y8rfh7 = (K6ufh7 & Uavfh7);
+ assign Uavfh7 = (~(Abvfh7 & E6vfh7));
+ assign HRDATA[12] = (~(Gbvfh7 & Mbvfh7));
+ assign Mbvfh7 = (Sbvfh7 & Ybvfh7);
+ assign Ybvfh7 = (Ecvfh7 & Kcvfh7);
+ assign Kcvfh7 = (Szrfh7 & Wupfh7);
+ assign Ecvfh7 = (E9ufh7 & Ogqfh7);
+ assign Ogqfh7 = (W6vfh7 | Qcvfh7);
+ assign Sbvfh7 = (Wcvfh7 & Ustfh7);
+ assign Ustfh7 = (!Q9tfh7);
+ assign Q9tfh7 = (Wxufh7 & M8vfh7);
+ assign Wcvfh7 = (U1vfh7 & Oprfh7);
+ assign Gbvfh7 = (Cdvfh7 & Idvfh7);
+ assign Idvfh7 = (Odvfh7 & Udvfh7);
+ assign Udvfh7 = (Eoqfh7 & U4sfh7);
+ assign Eoqfh7 = (Aevfh7 & Gevfh7);
+ assign Gevfh7 = (Mevfh7 & Szqfh7);
+ assign Mevfh7 = (Sztfh7 & Qosfh7);
+ assign Aevfh7 = (C4sfh7 & Mzqfh7);
+ assign C4sfh7 = (Sevfh7 & Yevfh7);
+ assign Yevfh7 = (Efvfh7 & E3vfh7);
+ assign Efvfh7 = (E0tfh7 & Uyqfh7);
+ assign Sevfh7 = (Kfvfh7 & Yeqfh7);
+ assign Kfvfh7 = (O7qfh7 & Odsfh7);
+ assign O7qfh7 = (Qfvfh7 & Wfvfh7);
+ assign Wfvfh7 = (Quqfh7 & U1ufh7);
+ assign Qfvfh7 = (Cjqfh7 & Ytsfh7);
+ assign Odvfh7 = (~(Isufh7 | S2rfh7));
+ assign S2rfh7 = (~(Cgvfh7 & Cmufh7));
+ assign Cmufh7 = (Igvfh7 & E6ufh7);
+ assign E6ufh7 = (~(Kxrfh7 & G2qfh7));
+ assign Igvfh7 = (~(Awqfh7 & Mntfh7));
+ assign Cgvfh7 = (Uytfh7 & K6sfh7);
+ assign Uytfh7 = (Ogvfh7 & Ugvfh7);
+ assign Ugvfh7 = (~(Ahvfh7 & Ghvfh7));
+ assign Ghvfh7 = (~(Mhvfh7 & Shvfh7));
+ assign Ogvfh7 = (~(Krsfh7 & Mntfh7));
+ assign Isufh7 = (~(Yhvfh7 & Eivfh7));
+ assign Eivfh7 = (Sqsfh7 & Qrtfh7);
+ assign Qrtfh7 = (~(Yhqfh7 & Errfh7));
+ assign Sqsfh7 = (!Oytfh7);
+ assign Oytfh7 = (~(Kivfh7 | Anufh7));
+ assign Yhvfh7 = (~(Iytfh7 | W9tfh7));
+ assign W9tfh7 = (~(Qivfh7 | Wivfh7));
+ assign Iytfh7 = (Cjvfh7 & M8vfh7);
+ assign Cdvfh7 = (Ijvfh7 & Efufh7);
+ assign Efufh7 = (Ojvfh7 & Ujvfh7);
+ assign Ujvfh7 = (Akvfh7 & Gkvfh7);
+ assign Gkvfh7 = (Q9qfh7 & A5qfh7);
+ assign Akvfh7 = (Ovrfh7 & Gkufh7);
+ assign Ovrfh7 = (Ijufh7 | Mkvfh7);
+ assign Ojvfh7 = (Skvfh7 & Ykvfh7);
+ assign Ykvfh7 = (K6ufh7 & Ywrfh7);
+ assign Ywrfh7 = (~(K9vfh7 & Ahvfh7));
+ assign K6ufh7 = (~(Abvfh7 & O1rfh7));
+ assign Skvfh7 = (Uaqfh7 & Idsfh7);
+ assign Idsfh7 = (Elvfh7 | Qivfh7);
+ assign Ijvfh7 = (~(W9rfh7 | Mbsfh7));
+ assign Mbsfh7 = (~(Klvfh7 & Qlvfh7));
+ assign Qlvfh7 = (Omqfh7 & Mhrfh7);
+ assign Klvfh7 = (Ojrfh7 & Igqfh7);
+ assign W9rfh7 = (~(Cdqfh7 & Q6ufh7));
+ assign Q6ufh7 = (~(Abvfh7 & Iprfh7));
+ assign HRDATA[11] = (~(Wlvfh7 & Cmvfh7));
+ assign Cmvfh7 = (Imvfh7 & Omvfh7);
+ assign Omvfh7 = (Umvfh7 & I1sfh7);
+ assign I1sfh7 = (~(G2qfh7 & Omrfh7));
+ assign Umvfh7 = (E0tfh7 & W6sfh7);
+ assign Imvfh7 = (Anvfh7 & Sbtfh7);
+ assign Sbtfh7 = (~(Gnvfh7 & Errfh7));
+ assign Anvfh7 = (K6sfh7 & E9qfh7);
+ assign E9qfh7 = (~(Errfh7 & Mnvfh7));
+ assign K6sfh7 = (Snvfh7 | Mhufh7);
+ assign Wlvfh7 = (Ynvfh7 & Eovfh7);
+ assign Eovfh7 = (~(Kovfh7 | Atufh7));
+ assign Atufh7 = (!I7ufh7);
+ assign I7ufh7 = (Qovfh7 & Wovfh7);
+ assign Wovfh7 = (C1qfh7 & E0qfh7);
+ assign E0qfh7 = (Cpvfh7 | Ojufh7);
+ assign C1qfh7 = (O7vfh7 | Ipvfh7);
+ assign O7vfh7 = (!Sqrfh7);
+ assign Qovfh7 = (Yerfh7 & Sqqfh7);
+ assign Sqqfh7 = (Ipvfh7 | Opvfh7);
+ assign Yerfh7 = (Elsfh7 | Upvfh7);
+ assign Kovfh7 = (~(Meqfh7 & Cypfh7));
+ assign Cypfh7 = (Aqvfh7 & Gqvfh7);
+ assign Gqvfh7 = (Mqvfh7 & Kcufh7);
+ assign Kcufh7 = (~(M2qfh7 & Sqvfh7));
+ assign Sqvfh7 = (~(Opvfh7 & S5vfh7));
+ assign Mqvfh7 = (Qosfh7 & Umtfh7);
+ assign Umtfh7 = (S5vfh7 | Ipvfh7);
+ assign Qosfh7 = (~(Klufh7 & M2tfh7));
+ assign Aqvfh7 = (Attfh7 & Sztfh7);
+ assign Sztfh7 = (Shvfh7 | Anufh7);
+ assign Attfh7 = (Yqvfh7 & Ervfh7);
+ assign Ervfh7 = (~(G8vfh7 & Mntfh7));
+ assign Yqvfh7 = (Krvfh7 & Qrvfh7);
+ assign Qrvfh7 = (~(Wxufh7 & Ahvfh7));
+ assign Krvfh7 = (~(G2tfh7 & O1rfh7));
+ assign Meqfh7 = (Qiufh7 & E9ufh7);
+ assign Qiufh7 = (Qupfh7 & Qlrfh7);
+ assign Qupfh7 = (~(Wrvfh7 & Usrfh7));
+ assign Ynvfh7 = (Csvfh7 & Stufh7);
+ assign Stufh7 = (Isvfh7 & Osvfh7);
+ assign Osvfh7 = (Usvfh7 & Atvfh7);
+ assign Atvfh7 = (Gtvfh7 & Mzqfh7);
+ assign Mzqfh7 = (Mtvfh7 | Anufh7);
+ assign Gtvfh7 = (Uyqfh7 & Quqfh7);
+ assign Usvfh7 = (C1rfh7 & Cdqfh7);
+ assign Cdqfh7 = (!Cjtfh7);
+ assign Cjtfh7 = (~(Stvfh7 | Anufh7));
+ assign C1rfh7 = (~(Awqfh7 & Exqfh7));
+ assign Isvfh7 = (Ytvfh7 & Euvfh7);
+ assign Euvfh7 = (Ivrfh7 & Odsfh7);
+ assign Odsfh7 = (~(Yhqfh7 & Ahvfh7));
+ assign Ivrfh7 = (Snqfh7 & Upqfh7);
+ assign Upqfh7 = (~(Kuvfh7 & Kxrfh7));
+ assign Snqfh7 = (W6vfh7 | Opvfh7);
+ assign Opvfh7 = (!G2qfh7);
+ assign Ytvfh7 = (~(Ynsfh7 | Qutfh7));
+ assign Qutfh7 = (Wrvfh7 & Exqfh7);
+ assign Ynsfh7 = (~(Yztfh7 & Iptfh7));
+ assign Yztfh7 = (~(Witfh7 | Igtfh7));
+ assign Igtfh7 = (~(Ghufh7 | Mkvfh7));
+ assign Witfh7 = (~(Shvfh7 | Mkvfh7));
+ assign HRDATA[10] = (~(Quvfh7 & Wuvfh7));
+ assign Wuvfh7 = (Cvvfh7 & Ivvfh7);
+ assign Ivvfh7 = (Ovvfh7 & E9ufh7);
+ assign E9ufh7 = (Kivfh7 | Uvvfh7);
+ assign Kivfh7 = (!Wxufh7);
+ assign Wxufh7 = (Awvfh7 & E6vfh7);
+ assign Ovvfh7 = (Isqfh7 & U1ufh7);
+ assign Isqfh7 = (Shvfh7 | Ojufh7);
+ assign Cvvfh7 = (Gwvfh7 & Ytsfh7);
+ assign Gwvfh7 = (Klrfh7 & Shqfh7);
+ assign Quvfh7 = (Mwvfh7 & Swvfh7);
+ assign Swvfh7 = (Ywvfh7 & C4qfh7);
+ assign C4qfh7 = (Exvfh7 & Kxvfh7);
+ assign Kxvfh7 = (Igqfh7 & Omqfh7);
+ assign Omqfh7 = (~(Osrfh7 & Errfh7));
+ assign Igqfh7 = (Ywtfh7 | Mnufh7);
+ assign Exvfh7 = (S8sfh7 & E3vfh7);
+ assign E3vfh7 = (~(Cjvfh7 & Exqfh7));
+ assign S8sfh7 = (~(Klufh7 & Mktfh7));
+ assign Ywvfh7 = (Wxpfh7 & Yqsfh7);
+ assign Yqsfh7 = (Qxvfh7 & Wxvfh7);
+ assign Wxvfh7 = (~(Kxrfh7 & Cyvfh7));
+ assign Qxvfh7 = (~(Usrfh7 & Iyvfh7));
+ assign Iyvfh7 = (~(Ghufh7 & Oyvfh7));
+ assign Wxpfh7 = (Uyvfh7 & Azvfh7);
+ assign Azvfh7 = (Gzvfh7 & Mzvfh7);
+ assign Mzvfh7 = (Szvfh7 & Yzvfh7);
+ assign Yzvfh7 = (Wuqfh7 & Efsfh7);
+ assign Wuqfh7 = (~(Klufh7 & O1rfh7));
+ assign Gzvfh7 = (E0wfh7 & W0rfh7);
+ assign W0rfh7 = (Elsfh7 | Wivfh7);
+ assign E0wfh7 = (Q0qfh7 & Szrfh7);
+ assign Q0qfh7 = (Gnufh7 | U4vfh7);
+ assign Uyvfh7 = (K0wfh7 & Q0wfh7);
+ assign Q0wfh7 = (W0wfh7 & C1wfh7);
+ assign C1wfh7 = (Y2sfh7 & Qlrfh7);
+ assign Qlrfh7 = (U4vfh7 | Upvfh7);
+ assign Y2sfh7 = (Ywtfh7 | Y5vfh7);
+ assign W0wfh7 = (Q3qfh7 & Caufh7);
+ assign Caufh7 = (Qcqfh7 & Oyqfh7);
+ assign Qcqfh7 = (Oyvfh7 | Mhufh7);
+ assign Q3qfh7 = (Qctfh7 & A8tfh7);
+ assign A8tfh7 = (Mtvfh7 | Uvvfh7);
+ assign Qctfh7 = (~(Awqfh7 & Errfh7));
+ assign K0wfh7 = (I1wfh7 & Atqfh7);
+ assign Atqfh7 = (O1wfh7 & U1wfh7);
+ assign U1wfh7 = (A2wfh7 & M5sfh7);
+ assign M5sfh7 = (~(Mntfh7 & G2wfh7));
+ assign G2wfh7 = (~(Mtvfh7 & Yntfh7));
+ assign A2wfh7 = (W6sfh7 & M2wfh7);
+ assign M2wfh7 = (~(Cyvfh7 & O1rfh7));
+ assign W6sfh7 = (Qcvfh7 | Elsfh7);
+ assign O1wfh7 = (S2wfh7 & Y2wfh7);
+ assign Y2wfh7 = (~(Kxrfh7 & Kfrfh7));
+ assign S2wfh7 = (E3wfh7 & Korfh7);
+ assign Korfh7 = (~(G2qfh7 & Mktfh7));
+ assign E3wfh7 = (~(Mnvfh7 & Exqfh7));
+ assign I1wfh7 = (Csrfh7 & W9qfh7);
+ assign W9qfh7 = (K3wfh7 & Q3wfh7);
+ assign Q3wfh7 = (W3wfh7 & C4wfh7);
+ assign C4wfh7 = (I4wfh7 & Quqfh7);
+ assign I4wfh7 = (Cvrfh7 & Wurfh7);
+ assign W3wfh7 = (Ghrfh7 & Uyqfh7);
+ assign Uyqfh7 = (Oyvfh7 | Uvvfh7);
+ assign Ghrfh7 = (~(K9vfh7 & Errfh7));
+ assign K9vfh7 = (!Ijufh7);
+ assign K3wfh7 = (O4wfh7 & U4wfh7);
+ assign U4wfh7 = (Mqufh7 & Opqfh7);
+ assign Opqfh7 = (~(Kfrfh7 & M2qfh7));
+ assign Mqufh7 = (A5wfh7 & Qxsfh7);
+ assign Qxsfh7 = (~(Krsfh7 & Errfh7));
+ assign Krsfh7 = (!Stvfh7);
+ assign A5wfh7 = (Atsfh7 & Wlrfh7);
+ assign Atsfh7 = (Elvfh7 | Elsfh7);
+ assign O4wfh7 = (W3qfh7 & Wrqfh7);
+ assign Wrqfh7 = (S8vfh7 & Y2vfh7);
+ assign Y2vfh7 = (~(G2qfh7 & E6vfh7));
+ assign S8vfh7 = (~(Abvfh7 & Kxrfh7));
+ assign W3qfh7 = (G5wfh7 & Cmqfh7);
+ assign Cmqfh7 = (~(Wrvfh7 & Mntfh7));
+ assign Csrfh7 = (Ghqfh7 & Wlqfh7);
+ assign Ghqfh7 = (~(M5wfh7 & Errfh7));
+ assign Mwvfh7 = (~(Q9rfh7 | Y2rfh7));
+ assign Q9rfh7 = (~(S5wfh7 & Y5wfh7));
+ assign Y5wfh7 = (E0tfh7 & Q9qfh7);
+ assign E0tfh7 = (Cpvfh7 | Mkvfh7);
+ assign S5wfh7 = (C7rfh7 & U1vfh7);
+ assign C7rfh7 = (E6wfh7 & K6wfh7);
+ assign K6wfh7 = (~(Cjvfh7 & Errfh7));
+ assign E6wfh7 = (~(Kfrfh7 & Q6wfh7));
+ assign Q6wfh7 = (~(W6wfh7 & Y5vfh7));
+ assign Kfrfh7 = (Errfh7 & C7wfh7);
+ assign HRDATA[0] = (~(I7wfh7 & O7wfh7));
+ assign O7wfh7 = (U7wfh7 & A8wfh7);
+ assign A8wfh7 = (G8wfh7 & M8wfh7);
+ assign M8wfh7 = (Wlqfh7 & Oyqfh7);
+ assign Oyqfh7 = (S8wfh7 | Uvvfh7);
+ assign Wlqfh7 = (~(G8vfh7 & Exqfh7));
+ assign G8wfh7 = (A5qfh7 & Wlrfh7);
+ assign Wlrfh7 = (Y8wfh7 | Uvvfh7);
+ assign A5qfh7 = (~(Yhqfh7 & Exqfh7));
+ assign U7wfh7 = (E9wfh7 & Aksfh7);
+ assign Aksfh7 = (K9wfh7 & Q9wfh7);
+ assign Q9wfh7 = (~(Kuvfh7 & E6vfh7));
+ assign K9wfh7 = (~(G2qfh7 & O1rfh7));
+ assign G2qfh7 = (~(Mkvfh7 | W9wfh7));
+ assign E9wfh7 = (Cjqfh7 & Q0rfh7);
+ assign Q0rfh7 = (Eotfh7 | Ojufh7);
+ assign Cjqfh7 = (Cawfh7 & Iawfh7);
+ assign Iawfh7 = (~(M2qfh7 & K0vfh7));
+ assign Cawfh7 = (Oawfh7 & K0tfh7);
+ assign K0tfh7 = (~(Mktfh7 & K0vfh7));
+ assign Oawfh7 = (O4vfh7 | W6wfh7);
+ assign I7wfh7 = (Uawfh7 & Abwfh7);
+ assign Abwfh7 = (Gbwfh7 & E3rfh7);
+ assign E3rfh7 = (Mbwfh7 & Sbwfh7);
+ assign Sbwfh7 = (Ybwfh7 & Ijrfh7);
+ assign Ijrfh7 = (Ipvfh7 | Upvfh7);
+ assign Ybwfh7 = (~(Q6vfh7 | Ecwfh7));
+ assign Ecwfh7 = (!Cvrfh7);
+ assign Cvrfh7 = (~(Klufh7 & Iprfh7));
+ assign Q6vfh7 = (~(Cpvfh7 | Oavfh7));
+ assign Cpvfh7 = (!Cjvfh7);
+ assign Cjvfh7 = (Kxrfh7 & Awvfh7);
+ assign Mbwfh7 = (G5wfh7 & Oyrfh7);
+ assign Oyrfh7 = (!Gkrfh7);
+ assign Gkrfh7 = (~(Qivfh7 | Qcvfh7));
+ assign G5wfh7 = (~(Wrvfh7 & Ahvfh7));
+ assign Wrvfh7 = (!S8wfh7);
+ assign Gbwfh7 = (Yktfh7 & Seqfh7);
+ assign Seqfh7 = (Kcwfh7 & Qcwfh7);
+ assign Qcwfh7 = (Wcwfh7 & Cdwfh7);
+ assign Cdwfh7 = (Quqfh7 & Wupfh7);
+ assign Wupfh7 = (Mnufh7 | Upvfh7);
+ assign Quqfh7 = (Ywtfh7 | Ipvfh7);
+ assign Wcwfh7 = (Shqfh7 & Ujrfh7);
+ assign Ujrfh7 = (~(Yhrfh7 & Usrfh7));
+ assign Shqfh7 = (~(Omrfh7 & Cyvfh7));
+ assign Kcwfh7 = (Idwfh7 & Odwfh7);
+ assign Odwfh7 = (Aqqfh7 & Oprfh7);
+ assign Oprfh7 = (Qcvfh7 | Extfh7);
+ assign Qcvfh7 = (!K0vfh7);
+ assign Aqqfh7 = (Yntfh7 | Ojufh7);
+ assign Idwfh7 = (Mksfh7 & Uaqfh7);
+ assign Uaqfh7 = (Udwfh7 & Ijsfh7);
+ assign Ijsfh7 = (~(Aewfh7 & Mntfh7));
+ assign Udwfh7 = (Cdsfh7 & M5rfh7);
+ assign M5rfh7 = (Mtvfh7 | Oavfh7);
+ assign Cdsfh7 = (~(M5wfh7 & Ahvfh7));
+ assign Mksfh7 = (Ywpfh7 & Gewfh7);
+ assign Gewfh7 = (~(Sqrfh7 & E6vfh7));
+ assign Ywpfh7 = (Mewfh7 & Mnqfh7);
+ assign Mnqfh7 = (~(Kcrfh7 | Sewfh7));
+ assign Sewfh7 = (Uvqfh7 & Yewfh7);
+ assign Yewfh7 = (~(Efwfh7 & Kfwfh7));
+ assign Efwfh7 = (Qfwfh7 & Shvfh7);
+ assign Qfwfh7 = (~(Omrfh7 & Umrfh7));
+ assign Kcrfh7 = (Wfwfh7 & Uvqfh7);
+ assign Wfwfh7 = (M2tfh7 & C7wfh7);
+ assign Mewfh7 = (Ijqfh7 & Cgwfh7);
+ assign Cgwfh7 = (~(Sqrfh7 & Kxrfh7));
+ assign Sqrfh7 = (C7wfh7 & Usrfh7);
+ assign Ijqfh7 = (~(Eltfh7 | Igwfh7));
+ assign Igwfh7 = (Ogwfh7 & Uvqfh7);
+ assign Ogwfh7 = (Omrfh7 & C7wfh7);
+ assign Eltfh7 = (~(Ugwfh7 & Ahwfh7));
+ assign Ahwfh7 = (Ghwfh7 & Mhwfh7);
+ assign Mhwfh7 = (~(Shwfh7 & Yhwfh7));
+ assign Yhwfh7 = (~(Eiwfh7 & W6wfh7));
+ assign W6wfh7 = (~(Mktfh7 | M2tfh7));
+ assign Eiwfh7 = (Y5vfh7 & U4vfh7);
+ assign Shwfh7 = (~(Wivfh7 & Elvfh7));
+ assign Ghwfh7 = (~(M8vfh7 & Kiwfh7));
+ assign Kiwfh7 = (~(Qiwfh7 & Wiwfh7));
+ assign Wiwfh7 = (Cjwfh7 & Ijufh7);
+ assign Ijufh7 = (~(Ijwfh7 & Mktfh7));
+ assign Cjwfh7 = (S8wfh7 & Iavfh7);
+ assign S8wfh7 = (~(M2tfh7 & Ijwfh7));
+ assign Qiwfh7 = (Kfwfh7 & Ujsfh7);
+ assign Ujsfh7 = (~(Krrfh7 | Yhqfh7));
+ assign Krrfh7 = (~(Yntfh7 & Shvfh7));
+ assign Shvfh7 = (!Swqfh7);
+ assign Swqfh7 = (~(Mnufh7 | Ojwfh7));
+ assign Kfwfh7 = (Eotfh7 & Mtvfh7);
+ assign Mtvfh7 = (!Yhrfh7);
+ assign Yhrfh7 = (~(Y5vfh7 | Ojwfh7));
+ assign M8vfh7 = (!Mhufh7);
+ assign Ugwfh7 = (Ytsfh7 & Ujwfh7);
+ assign Ujwfh7 = (~(Uvqfh7 & Akwfh7));
+ assign Akwfh7 = (~(Gkwfh7 & Mkwfh7));
+ assign Mkwfh7 = (Skwfh7 & Elsfh7);
+ assign Skwfh7 = (Qivfh7 & W6vfh7);
+ assign Gkwfh7 = (Mhvfh7 & Ykwfh7);
+ assign Ykwfh7 = (~(C7wfh7 & O1rfh7));
+ assign Mhvfh7 = (Snvfh7 & Ghufh7);
+ assign Uvqfh7 = (Elwfh7 & Klwfh7);
+ assign Ytsfh7 = (Qlwfh7 & C4tfh7);
+ assign C4tfh7 = (~(M2tfh7 & K0vfh7));
+ assign K0vfh7 = (C7wfh7 & Ahvfh7);
+ assign Qlwfh7 = (Ovsfh7 & Ivsfh7);
+ assign Ivsfh7 = (~(Aewfh7 & Exqfh7));
+ assign Aewfh7 = (!Oyvfh7);
+ assign Ovsfh7 = (O4vfh7 | Y5vfh7);
+ assign Yktfh7 = (Wlwfh7 & Q6sfh7);
+ assign Q6sfh7 = (~(Mnvfh7 & Mntfh7));
+ assign Mnvfh7 = (!Iavfh7);
+ assign Wlwfh7 = (Ybtfh7 & U1ufh7);
+ assign U1ufh7 = (Gnufh7 | Y5vfh7);
+ assign Y5vfh7 = (!Omrfh7);
+ assign Ybtfh7 = (~(Kuvfh7 & M2tfh7));
+ assign Uawfh7 = (Cmwfh7 & Csvfh7);
+ assign Csvfh7 = (Imwfh7 & Omwfh7);
+ assign Omwfh7 = (Umwfh7 & Anwfh7);
+ assign Anwfh7 = (Q9qfh7 & Cdrfh7);
+ assign Cdrfh7 = (W6vfh7 | Upvfh7);
+ assign Upvfh7 = (!Cyvfh7);
+ assign Cyvfh7 = (Usrfh7 & Umrfh7);
+ assign Q9qfh7 = (Ywtfh7 | W6vfh7);
+ assign Umwfh7 = (Gkufh7 & K0qfh7);
+ assign K0qfh7 = (S5vfh7 | Mnufh7);
+ assign Mnufh7 = (!Mktfh7);
+ assign Mktfh7 = (Gnwfh7 & Ovwfh7[2]);
+ assign S5vfh7 = (!Abvfh7);
+ assign Abvfh7 = (~(Oavfh7 | W9wfh7));
+ assign Gkufh7 = (~(Klufh7 & Kxrfh7));
+ assign Klufh7 = (Exqfh7 & Umrfh7);
+ assign Imwfh7 = (Mnwfh7 & Kltfh7);
+ assign Kltfh7 = (Snwfh7 & Ynwfh7);
+ assign Ynwfh7 = (Eowfh7 & Kowfh7);
+ assign Kowfh7 = (Szvfh7 & Szrfh7);
+ assign Szrfh7 = (Snvfh7 | Anufh7);
+ assign Snvfh7 = (!Osrfh7);
+ assign Szvfh7 = (Iyqfh7 & Mhrfh7);
+ assign Mhrfh7 = (Qowfh7 | Mhufh7);
+ assign Iyqfh7 = (Iavfh7 | Ojufh7);
+ assign Iavfh7 = (~(Ijwfh7 & Omrfh7));
+ assign Omrfh7 = (Wowfh7 & Ovwfh7[3]);
+ assign Wowfh7 = (~(Cpwfh7 | Ovwfh7[6]));
+ assign Eowfh7 = (Klrfh7 & Szqfh7);
+ assign Szqfh7 = (Qowfh7 | Anufh7);
+ assign Klrfh7 = (!Swtfh7);
+ assign Swtfh7 = (~(W6vfh7 | Wivfh7));
+ assign Snwfh7 = (Ipwfh7 & Opwfh7);
+ assign Opwfh7 = (Idrfh7 & U1vfh7);
+ assign U1vfh7 = (Ghufh7 | Anufh7);
+ assign Ghufh7 = (!Gnvfh7);
+ assign Gnvfh7 = (Ijwfh7 & O1rfh7);
+ assign O1rfh7 = (!Extfh7);
+ assign Idrfh7 = (~(Usrfh7 & Upwfh7));
+ assign Upwfh7 = (~(Qowfh7 & Stvfh7));
+ assign Usrfh7 = (!Ojufh7);
+ assign Ojufh7 = (~(Aqwfh7 & Ovwfh7[9]));
+ assign Aqwfh7 = (Ovwfh7[7] & Gqwfh7);
+ assign Ipwfh7 = (Yeqfh7 & U4sfh7);
+ assign U4sfh7 = (~(Yhqfh7 & Mntfh7));
+ assign Yhqfh7 = (Ijwfh7 & M2qfh7);
+ assign Yeqfh7 = (!Y2rfh7);
+ assign Y2rfh7 = (~(Mqwfh7 & Sqwfh7));
+ assign Sqwfh7 = (~(Ahvfh7 & Yqwfh7));
+ assign Yqwfh7 = (~(Stvfh7 & Eotfh7));
+ assign Eotfh7 = (!Awqfh7);
+ assign Awqfh7 = (~(Ipvfh7 | Ojwfh7));
+ assign Ipvfh7 = (!M2tfh7);
+ assign M2tfh7 = (Erwfh7 & Ovwfh7[3]);
+ assign Erwfh7 = (~(Ovwfh7[2] | Ovwfh7[6]));
+ assign Mqwfh7 = (~(M5wfh7 & Mntfh7));
+ assign M5wfh7 = (!Qowfh7);
+ assign Qowfh7 = (~(Ijwfh7 & E6vfh7));
+ assign Mnwfh7 = (Ojrfh7 & Qorfh7);
+ assign Qorfh7 = (Ywtfh7 | Elsfh7);
+ assign Elsfh7 = (!E6vfh7);
+ assign E6vfh7 = (Krwfh7 & Ovwfh7[6]);
+ assign Krwfh7 = (Ovwfh7[2] & Qrwfh7);
+ assign Ywtfh7 = (!Exrfh7);
+ assign Ojrfh7 = (Stvfh7 | Mhufh7);
+ assign Stvfh7 = (~(Kxrfh7 & Ijwfh7));
+ assign Cmwfh7 = (Uaufh7 & E6tfh7);
+ assign E6tfh7 = (Wrwfh7 & K9qfh7);
+ assign K9qfh7 = (O4vfh7 | Qivfh7);
+ assign Qivfh7 = (!Kxrfh7);
+ assign Kxrfh7 = (Cswfh7 & Ovwfh7[6]);
+ assign Cswfh7 = (Cpwfh7 & Qrwfh7);
+ assign Qrwfh7 = (!Ovwfh7[3]);
+ assign O4vfh7 = (!G2tfh7);
+ assign G2tfh7 = (Mntfh7 & C7wfh7);
+ assign Wrwfh7 = (G5qfh7 & Wurfh7);
+ assign Wurfh7 = (~(Exrfh7 & M2qfh7));
+ assign Exrfh7 = (Errfh7 & Umrfh7);
+ assign Errfh7 = (!Uvvfh7);
+ assign Uvvfh7 = (~(Iswfh7 & Ovwfh7[9]));
+ assign Iswfh7 = (Ovwfh7[8] & Klwfh7);
+ assign G5qfh7 = (Elvfh7 | W6vfh7);
+ assign Elvfh7 = (!I1rfh7);
+ assign I1rfh7 = (~(Oswfh7 | Mhufh7));
+ assign Oswfh7 = (!C7wfh7);
+ assign Uaufh7 = (Uswfh7 & Iptfh7);
+ assign Iptfh7 = (Atwfh7 & Gtwfh7);
+ assign Gtwfh7 = (~(Osrfh7 & Mntfh7));
+ assign Mntfh7 = (!Mkvfh7);
+ assign Mkvfh7 = (~(Mtwfh7 & Ovwfh7[8]));
+ assign Mtwfh7 = (~(Klwfh7 | Ovwfh7[9]));
+ assign Osrfh7 = (~(Ojwfh7 | Extfh7));
+ assign Atwfh7 = (~(Ahvfh7 & Stwfh7));
+ assign Stwfh7 = (~(Ytwfh7 & Yntfh7));
+ assign Yntfh7 = (!Ywqfh7);
+ assign Ywqfh7 = (~(Ojwfh7 | U4vfh7));
+ assign U4vfh7 = (!M2qfh7);
+ assign M2qfh7 = (Gnwfh7 & Cpwfh7);
+ assign Gnwfh7 = (~(Ovwfh7[3] | Ovwfh7[6]));
+ assign Ytwfh7 = (Oyvfh7 & Y8wfh7);
+ assign Y8wfh7 = (!G8vfh7);
+ assign G8vfh7 = (~(W6vfh7 | Ojwfh7));
+ assign Ojwfh7 = (!Awvfh7);
+ assign Awvfh7 = (Euwfh7 & Kuwfh7);
+ assign Oyvfh7 = (~(Iprfh7 & Ijwfh7));
+ assign Ijwfh7 = (Ovwfh7[4] & Kuwfh7);
+ assign Kuwfh7 = (!Ovwfh7[5]);
+ assign Ahvfh7 = (!Oavfh7);
+ assign Oavfh7 = (~(Quwfh7 & Ovwfh7[9]));
+ assign Quwfh7 = (Klwfh7 & Gqwfh7);
+ assign Gqwfh7 = (!Ovwfh7[8]);
+ assign Klwfh7 = (!Ovwfh7[7]);
+ assign Uswfh7 = (Efsfh7 & Sksfh7);
+ assign Sksfh7 = (Gnufh7 | W6vfh7);
+ assign W6vfh7 = (!Iprfh7);
+ assign Iprfh7 = (Wuwfh7 & Ovwfh7[6]);
+ assign Wuwfh7 = (Ovwfh7[3] & Cpwfh7);
+ assign Cpwfh7 = (!Ovwfh7[2]);
+ assign Gnufh7 = (!Kuvfh7);
+ assign Kuvfh7 = (Exqfh7 & C7wfh7);
+ assign C7wfh7 = (Ovwfh7[5] & Ovwfh7[4]);
+ assign Exqfh7 = (!Anufh7);
+ assign Anufh7 = (~(Cvwfh7 & Ovwfh7[8]));
+ assign Cvwfh7 = (~(Ovwfh7[7] | Ovwfh7[9]));
+ assign Efsfh7 = (Extfh7 | Wivfh7);
+ assign Wivfh7 = (Mhufh7 | W9wfh7);
+ assign W9wfh7 = (!Umrfh7);
+ assign Umrfh7 = (Ovwfh7[5] & Euwfh7);
+ assign Euwfh7 = (!Ovwfh7[4]);
+ assign Mhufh7 = (~(Elwfh7 & Ovwfh7[7]));
+ assign Elwfh7 = (~(Ovwfh7[8] | Ovwfh7[9]));
+ assign Extfh7 = (~(Ivwfh7 & Ovwfh7[6]));
+ assign Ivwfh7 = (Ovwfh7[3] & Ovwfh7[2]);
+
+ always @(posedge HCLK) Fwwfh7 <= Dspfh7;
+ always @(posedge HCLK) Dxwfh7 <= Yrpfh7;
+ always @(posedge HCLK) Bywfh7 <= Trpfh7;
+ always @(posedge HCLK) Zywfh7 <= Orpfh7;
+ always @(posedge HCLK) Xzwfh7 <= Jrpfh7;
+ always @(posedge HCLK) V0xfh7 <= Erpfh7;
+ always @(posedge HCLK) T1xfh7 <= Zqpfh7;
+ always @(posedge HCLK) R2xfh7 <= Uqpfh7;
+endmodule
+
+/* Design Summary
+ modules: 1
+ udps: 0
+ mod flatinsts: 0
+ udp flatinsts: 0
+ nodes: 1136 (0)
+ node widths: 1220 (0)
+ process: 8 (0)
+ gates: 0 (0)
+ contassigns: 1156 (0)
+ ports: 13 (0)
+ modinsts: 0 (0)
+ udpinsts: 0 (0)
+ portconnects: 0 (0)
+*/
+
+// END: VCS tokens
+// Currnet Allocated Virtual Memory Size: 203.46 MB
+// ===================
+// DESIGN STATISTICS
+// ===================
+//
+// No. of design lines (note: includes comments and blank lines) 2337
+//
+// Static<!> Elaborated<@> Size(KB)
+// ------ ---------- --------
+// No. of all modules (module+interface+package+program): 1 1 0
+// No. of module instances: 1 1 0
+// No. of all processes: 8 8 0
+// No. of all nodes (variable+net): 1136 1136 0
+// No. of constants 101 101 0
+// No. of scalar nets: 1121 1121 0
+// No. of vector nets: 7 7 0
+// No. of scalar regs/logics: 8 8 0
+// No. of always blocks: 8 8 0
+// No. of operators: 1413 1413 0
+// No. of bit selects: 99 99 0
+// No. of non-blocking assignments: 8 8 0
+// No. of continuous assignments: 1156 1156 0
+//
+// No. of top level modules/programs/packages/interfaces: 1
+// modules: 1
+// No. of module+udp ports: 13
+//
+// Footnotes:
+// ---------
+// <!> No. of unique instances of a construct as it appears in the source.
+// <@> No. of instances of a construct when the design is elaborated.
+// K, M, B: Counted in thousands, millions and billions (if big numbers are present)
+//
+// <#> Multiple specify blocks in the SAME module are combined and counted
+// as ONE block.
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v
new file mode 100644
index 0000000000000000000000000000000000000000..f5b0e7f2e5c11f2e9c8dd7c2017e2e776e585bc9
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v
@@ -0,0 +1,267 @@
+module bootrom (
+ input wire CLK,
+ input wire EN,
+ input wire [9:2] ADDR,
+ output reg [31:0] RDATA );
+reg [9:2] addr_r;
+always @(posedge CLK) if (EN) addr_r <= ADDR;
+always @(addr_r) case(addr_r[9:2])
+ 8'h000 : RDATA <= 32'h20000368; // 0x0000
+ 8'h001 : RDATA <= 32'h010002d1; // 0x0004
+ 8'h002 : RDATA <= 32'h010002d9; // 0x0008
+ 8'h003 : RDATA <= 32'h010002db; // 0x000c
+ 8'h004 : RDATA <= 32'h00000000; // 0x0010
+ 8'h005 : RDATA <= 32'h00000000; // 0x0014
+ 8'h006 : RDATA <= 32'h00000000; // 0x0018
+ 8'h007 : RDATA <= 32'h00000000; // 0x001c
+ 8'h008 : RDATA <= 32'h00000000; // 0x0020
+ 8'h009 : RDATA <= 32'h00000000; // 0x0024
+ 8'h00a : RDATA <= 32'h00000000; // 0x0028
+ 8'h00b : RDATA <= 32'h010002dd; // 0x002c
+ 8'h00c : RDATA <= 32'h00000000; // 0x0030
+ 8'h00d : RDATA <= 32'h00000000; // 0x0034
+ 8'h00e : RDATA <= 32'h010002df; // 0x0038
+ 8'h00f : RDATA <= 32'h010002e1; // 0x003c
+ 8'h010 : RDATA <= 32'h010002e3; // 0x0040
+ 8'h011 : RDATA <= 32'h010002e3; // 0x0044
+ 8'h012 : RDATA <= 32'h010002e3; // 0x0048
+ 8'h013 : RDATA <= 32'h010002e3; // 0x004c
+ 8'h014 : RDATA <= 32'h010002e3; // 0x0050
+ 8'h015 : RDATA <= 32'h010002e3; // 0x0054
+ 8'h016 : RDATA <= 32'h010002e3; // 0x0058
+ 8'h017 : RDATA <= 32'h010002e3; // 0x005c
+ 8'h018 : RDATA <= 32'h010002e3; // 0x0060
+ 8'h019 : RDATA <= 32'h010002e3; // 0x0064
+ 8'h01a : RDATA <= 32'h010002e3; // 0x0068
+ 8'h01b : RDATA <= 32'h00000000; // 0x006c
+ 8'h01c : RDATA <= 32'h010002e3; // 0x0070
+ 8'h01d : RDATA <= 32'h010002e3; // 0x0074
+ 8'h01e : RDATA <= 32'h010002e3; // 0x0078
+ 8'h01f : RDATA <= 32'h010002e3; // 0x007c
+ 8'h020 : RDATA <= 32'h010002e3; // 0x0080
+ 8'h021 : RDATA <= 32'h010002e3; // 0x0084
+ 8'h022 : RDATA <= 32'h010002e3; // 0x0088
+ 8'h023 : RDATA <= 32'h010002e3; // 0x008c
+ 8'h024 : RDATA <= 32'h010002e3; // 0x0090
+ 8'h025 : RDATA <= 32'h010002e3; // 0x0094
+ 8'h026 : RDATA <= 32'h010002e3; // 0x0098
+ 8'h027 : RDATA <= 32'h010002e3; // 0x009c
+ 8'h028 : RDATA <= 32'h010002e3; // 0x00a0
+ 8'h029 : RDATA <= 32'h010002e3; // 0x00a4
+ 8'h02a : RDATA <= 32'h010002e3; // 0x00a8
+ 8'h02b : RDATA <= 32'h010002e3; // 0x00ac
+ 8'h02c : RDATA <= 32'h010002e3; // 0x00b0
+ 8'h02d : RDATA <= 32'h010002e3; // 0x00b4
+ 8'h02e : RDATA <= 32'h010002e3; // 0x00b8
+ 8'h02f : RDATA <= 32'h010002e3; // 0x00bc
+ 8'h030 : RDATA <= 32'hf802f000; // 0x00c0
+ 8'h031 : RDATA <= 32'hf83ef000; // 0x00c4
+ 8'h032 : RDATA <= 32'hc830a00c; // 0x00c8
+ 8'h033 : RDATA <= 32'h18243808; // 0x00cc
+ 8'h034 : RDATA <= 32'h46a2182d; // 0x00d0
+ 8'h035 : RDATA <= 32'h46ab1e67; // 0x00d4
+ 8'h036 : RDATA <= 32'h465d4654; // 0x00d8
+ 8'h037 : RDATA <= 32'hd10142ac; // 0x00dc
+ 8'h038 : RDATA <= 32'hf830f000; // 0x00e0
+ 8'h039 : RDATA <= 32'h3e0f467e; // 0x00e4
+ 8'h03a : RDATA <= 32'h46b6cc0f; // 0x00e8
+ 8'h03b : RDATA <= 32'h42332601; // 0x00ec
+ 8'h03c : RDATA <= 32'h1afbd000; // 0x00f0
+ 8'h03d : RDATA <= 32'h46ab46a2; // 0x00f4
+ 8'h03e : RDATA <= 32'h47184333; // 0x00f8
+ 8'h03f : RDATA <= 32'h00000278; // 0x00fc
+ 8'h040 : RDATA <= 32'h00000298; // 0x0100
+ 8'h041 : RDATA <= 32'hd3023a10; // 0x0104
+ 8'h042 : RDATA <= 32'hc178c878; // 0x0108
+ 8'h043 : RDATA <= 32'h0752d8fa; // 0x010c
+ 8'h044 : RDATA <= 32'hc830d301; // 0x0110
+ 8'h045 : RDATA <= 32'hd501c130; // 0x0114
+ 8'h046 : RDATA <= 32'h600c6804; // 0x0118
+ 8'h047 : RDATA <= 32'h00004770; // 0x011c
+ 8'h048 : RDATA <= 32'h24002300; // 0x0120
+ 8'h049 : RDATA <= 32'h26002500; // 0x0124
+ 8'h04a : RDATA <= 32'hd3013a10; // 0x0128
+ 8'h04b : RDATA <= 32'hd8fbc178; // 0x012c
+ 8'h04c : RDATA <= 32'hd3000752; // 0x0130
+ 8'h04d : RDATA <= 32'hd500c130; // 0x0134
+ 8'h04e : RDATA <= 32'h4770600b; // 0x0138
+ 8'h04f : RDATA <= 32'hbd1fb51f; // 0x013c
+ 8'h050 : RDATA <= 32'hbd10b510; // 0x0140
+ 8'h051 : RDATA <= 32'hf8e3f000; // 0x0144
+ 8'h052 : RDATA <= 32'hf7ff4611; // 0x0148
+ 8'h053 : RDATA <= 32'hf000fff7; // 0x014c
+ 8'h054 : RDATA <= 32'hf000f84a; // 0x0150
+ 8'h055 : RDATA <= 32'hb403f8fb; // 0x0154
+ 8'h056 : RDATA <= 32'hfff2f7ff; // 0x0158
+ 8'h057 : RDATA <= 32'hf000bc03; // 0x015c
+ 8'h058 : RDATA <= 32'h0000f901; // 0x0160
+ 8'h059 : RDATA <= 32'h68012000; // 0x0164
+ 8'h05a : RDATA <= 32'h6841468d; // 0x0168
+ 8'h05b : RDATA <= 32'h00004708; // 0x016c
+ 8'h05c : RDATA <= 32'h2110483c; // 0x0170
+ 8'h05d : RDATA <= 32'h21416101; // 0x0174
+ 8'h05e : RDATA <= 32'h493b6081; // 0x0178
+ 8'h05f : RDATA <= 32'h61882020; // 0x017c
+ 8'h060 : RDATA <= 32'h49384770; // 0x0180
+ 8'h061 : RDATA <= 32'h07d2684a; // 0x0184
+ 8'h062 : RDATA <= 32'h6008d1fc; // 0x0188
+ 8'h063 : RDATA <= 32'h49354770; // 0x018c
+ 8'h064 : RDATA <= 32'h2b007803; // 0x0190
+ 8'h065 : RDATA <= 32'h684ad006; // 0x0194
+ 8'h066 : RDATA <= 32'hd1fc07d2; // 0x0198
+ 8'h067 : RDATA <= 32'h1c40600b; // 0x019c
+ 8'h068 : RDATA <= 32'hd1f52b00; // 0x01a0
+ 8'h069 : RDATA <= 32'hb5104770; // 0x01a4
+ 8'h06a : RDATA <= 32'h68014830; // 0x01a8
+ 8'h06b : RDATA <= 32'hd0082900; // 0x01ac
+ 8'h06c : RDATA <= 32'h60012100; // 0x01b0
+ 8'h06d : RDATA <= 32'h8f4ff3bf; // 0x01b4
+ 8'h06e : RDATA <= 32'h8f6ff3bf; // 0x01b8
+ 8'h06f : RDATA <= 32'hffd2f7ff; // 0x01bc
+ 8'h070 : RDATA <= 32'h4828bd10; // 0x01c0
+ 8'h071 : RDATA <= 32'h781aa32a; // 0x01c4
+ 8'h072 : RDATA <= 32'hd0062a00; // 0x01c8
+ 8'h073 : RDATA <= 32'h07c96841; // 0x01cc
+ 8'h074 : RDATA <= 32'h6002d1fc; // 0x01d0
+ 8'h075 : RDATA <= 32'h2a001c5b; // 0x01d4
+ 8'h076 : RDATA <= 32'h2104d1f5; // 0x01d8
+ 8'h077 : RDATA <= 32'h07d26842; // 0x01dc
+ 8'h078 : RDATA <= 32'h6001d1fc; // 0x01e0
+ 8'h079 : RDATA <= 32'hb510e7fe; // 0x01e4
+ 8'h07a : RDATA <= 32'h2110481e; // 0x01e8
+ 8'h07b : RDATA <= 32'h21416101; // 0x01ec
+ 8'h07c : RDATA <= 32'h4a1d6081; // 0x01f0
+ 8'h07d : RDATA <= 32'h61912120; // 0x01f4
+ 8'h07e : RDATA <= 32'h781aa326; // 0x01f8
+ 8'h07f : RDATA <= 32'hd0062a00; // 0x01fc
+ 8'h080 : RDATA <= 32'h07c96841; // 0x0200
+ 8'h081 : RDATA <= 32'h6002d1fc; // 0x0204
+ 8'h082 : RDATA <= 32'h2a001c5b; // 0x0208
+ 8'h083 : RDATA <= 32'ha326d1f5; // 0x020c
+ 8'h084 : RDATA <= 32'h2a00781a; // 0x0210
+ 8'h085 : RDATA <= 32'h6841d006; // 0x0214
+ 8'h086 : RDATA <= 32'hd1fc07c9; // 0x0218
+ 8'h087 : RDATA <= 32'h1c5b6002; // 0x021c
+ 8'h088 : RDATA <= 32'hd1f52a00; // 0x0220
+ 8'h089 : RDATA <= 32'h680a4911; // 0x0224
+ 8'h08a : RDATA <= 32'hd0092a00; // 0x0228
+ 8'h08b : RDATA <= 32'h60082000; // 0x022c
+ 8'h08c : RDATA <= 32'h8f4ff3bf; // 0x0230
+ 8'h08d : RDATA <= 32'h8f6ff3bf; // 0x0234
+ 8'h08e : RDATA <= 32'hff94f7ff; // 0x0238
+ 8'h08f : RDATA <= 32'hbd102000; // 0x023c
+ 8'h090 : RDATA <= 32'h781aa30b; // 0x0240
+ 8'h091 : RDATA <= 32'hd0062a00; // 0x0244
+ 8'h092 : RDATA <= 32'h07c96841; // 0x0248
+ 8'h093 : RDATA <= 32'h6002d1fc; // 0x024c
+ 8'h094 : RDATA <= 32'h2a001c5b; // 0x0250
+ 8'h095 : RDATA <= 32'h2204d1f5; // 0x0254
+ 8'h096 : RDATA <= 32'h07c96841; // 0x0258
+ 8'h097 : RDATA <= 32'h6002d1fc; // 0x025c
+ 8'h098 : RDATA <= 32'h0000e7fe; // 0x0260
+ 8'h099 : RDATA <= 32'h40006000; // 0x0264
+ 8'h09a : RDATA <= 32'h40011000; // 0x0268
+ 8'h09b : RDATA <= 32'h4001f000; // 0x026c
+ 8'h09c : RDATA <= 32'h7245202d; // 0x0270
+ 8'h09d : RDATA <= 32'h3a726f72; // 0x0274
+ 8'h09e : RDATA <= 32'h4d455220; // 0x0278
+ 8'h09f : RDATA <= 32'h69205041; // 0x027c
+ 8'h0a0 : RDATA <= 32'h6c612073; // 0x0280
+ 8'h0a1 : RDATA <= 32'h64616572; // 0x0284
+ 8'h0a2 : RDATA <= 32'h6c632079; // 0x0288
+ 8'h0a3 : RDATA <= 32'h0a726165; // 0x028c
+ 8'h0a4 : RDATA <= 32'h00000000; // 0x0290
+ 8'h0a5 : RDATA <= 32'h534d430a; // 0x0294
+ 8'h0a6 : RDATA <= 32'h42204b44; // 0x0298
+ 8'h0a7 : RDATA <= 32'h20746f6f; // 0x029c
+ 8'h0a8 : RDATA <= 32'h64616f4c; // 0x02a0
+ 8'h0a9 : RDATA <= 32'h000a7265; // 0x02a4
+ 8'h0aa : RDATA <= 32'h6f6c202d; // 0x02a8
+ 8'h0ab : RDATA <= 32'h66206461; // 0x02ac
+ 8'h0ac : RDATA <= 32'h6873616c; // 0x02b0
+ 8'h0ad : RDATA <= 32'h0000000a; // 0x02b4
+ 8'h0ae : RDATA <= 32'h48034904; // 0x02b8
+ 8'h0af : RDATA <= 32'h47706008; // 0x02bc
+ 8'h0b0 : RDATA <= 32'h48014902; // 0x02c0
+ 8'h0b1 : RDATA <= 32'h47706008; // 0x02c4
+ 8'h0b2 : RDATA <= 32'h05f5e100; // 0x02c8
+ 8'h0b3 : RDATA <= 32'h20000000; // 0x02cc
+ 8'h0b4 : RDATA <= 32'h47804807; // 0x02d0
+ 8'h0b5 : RDATA <= 32'h47004807; // 0x02d4
+ 8'h0b6 : RDATA <= 32'he7fee7fe; // 0x02d8
+ 8'h0b7 : RDATA <= 32'he7fee7fe; // 0x02dc
+ 8'h0b8 : RDATA <= 32'he7fee7fe; // 0x02e0
+ 8'h0b9 : RDATA <= 32'h49054804; // 0x02e4
+ 8'h0ba : RDATA <= 32'h4b064a05; // 0x02e8
+ 8'h0bb : RDATA <= 32'h00004770; // 0x02ec
+ 8'h0bc : RDATA <= 32'h010002c1; // 0x02f0
+ 8'h0bd : RDATA <= 32'h010000c1; // 0x02f4
+ 8'h0be : RDATA <= 32'h20000068; // 0x02f8
+ 8'h0bf : RDATA <= 32'h20000368; // 0x02fc
+ 8'h0c0 : RDATA <= 32'h20000168; // 0x0300
+ 8'h0c1 : RDATA <= 32'h20000168; // 0x0304
+ 8'h0c2 : RDATA <= 32'h47704770; // 0x0308
+ 8'h0c3 : RDATA <= 32'h46754770; // 0x030c
+ 8'h0c4 : RDATA <= 32'hf824f000; // 0x0310
+ 8'h0c5 : RDATA <= 32'h000546ae; // 0x0314
+ 8'h0c6 : RDATA <= 32'h46534669; // 0x0318
+ 8'h0c7 : RDATA <= 32'h00c008c0; // 0x031c
+ 8'h0c8 : RDATA <= 32'hb0184685; // 0x0320
+ 8'h0c9 : RDATA <= 32'hf7ffb520; // 0x0324
+ 8'h0ca : RDATA <= 32'hbc60ffdd; // 0x0328
+ 8'h0cb : RDATA <= 32'h08492700; // 0x032c
+ 8'h0cc : RDATA <= 32'h260046b6; // 0x0330
+ 8'h0cd : RDATA <= 32'hc5c0c5c0; // 0x0334
+ 8'h0ce : RDATA <= 32'hc5c0c5c0; // 0x0338
+ 8'h0cf : RDATA <= 32'hc5c0c5c0; // 0x033c
+ 8'h0d0 : RDATA <= 32'hc5c0c5c0; // 0x0340
+ 8'h0d1 : RDATA <= 32'h00493d40; // 0x0344
+ 8'h0d2 : RDATA <= 32'h4770468d; // 0x0348
+ 8'h0d3 : RDATA <= 32'h4604b510; // 0x034c
+ 8'h0d4 : RDATA <= 32'h46c046c0; // 0x0350
+ 8'h0d5 : RDATA <= 32'hf7ff4620; // 0x0354
+ 8'h0d6 : RDATA <= 32'hbd10fefe; // 0x0358
+ 8'h0d7 : RDATA <= 32'h47704800; // 0x035c
+ 8'h0d8 : RDATA <= 32'h20000004; // 0x0360
+ 8'h0d9 : RDATA <= 32'h20184901; // 0x0364
+ 8'h0da : RDATA <= 32'he7febeab; // 0x0368
+ 8'h0db : RDATA <= 32'h00020026; // 0x036c
+ 8'h0dc : RDATA <= 32'h00004770; // 0x0370
+ 8'h0dd : RDATA <= 32'h01000394; // 0x0374
+ 8'h0de : RDATA <= 32'h20000000; // 0x0378
+ 8'h0df : RDATA <= 32'h00000004; // 0x037c
+ 8'h0e0 : RDATA <= 32'h01000104; // 0x0380
+ 8'h0e1 : RDATA <= 32'h01000398; // 0x0384
+ 8'h0e2 : RDATA <= 32'h20000004; // 0x0388
+ 8'h0e3 : RDATA <= 32'h00000364; // 0x038c
+ 8'h0e4 : RDATA <= 32'h01000120; // 0x0390
+ 8'h0e5 : RDATA <= 32'h05f5e100; // 0x0394
+ 8'h0e6 : RDATA <= 32'h00000000; // 0x0398
+ 8'h0e7 : RDATA <= 32'h00000000; // 0x039c
+ 8'h0e8 : RDATA <= 32'h00000000; // 0x03a0
+ 8'h0e9 : RDATA <= 32'h00000000; // 0x03a4
+ 8'h0ea : RDATA <= 32'h00000000; // 0x03a8
+ 8'h0eb : RDATA <= 32'h00000000; // 0x03ac
+ 8'h0ec : RDATA <= 32'h00000000; // 0x03b0
+ 8'h0ed : RDATA <= 32'h00000000; // 0x03b4
+ 8'h0ee : RDATA <= 32'h00000000; // 0x03b8
+ 8'h0ef : RDATA <= 32'h00000000; // 0x03bc
+ 8'h0f0 : RDATA <= 32'h00000000; // 0x03c0
+ 8'h0f1 : RDATA <= 32'h00000000; // 0x03c4
+ 8'h0f2 : RDATA <= 32'h00000000; // 0x03c8
+ 8'h0f3 : RDATA <= 32'h00000000; // 0x03cc
+ 8'h0f4 : RDATA <= 32'h00000000; // 0x03d0
+ 8'h0f5 : RDATA <= 32'h00000000; // 0x03d4
+ 8'h0f6 : RDATA <= 32'h00000000; // 0x03d8
+ 8'h0f7 : RDATA <= 32'h00000000; // 0x03dc
+ 8'h0f8 : RDATA <= 32'h00000000; // 0x03e0
+ 8'h0f9 : RDATA <= 32'h00000000; // 0x03e4
+ 8'h0fa : RDATA <= 32'h00000000; // 0x03e8
+ 8'h0fb : RDATA <= 32'h00000000; // 0x03ec
+ 8'h0fc : RDATA <= 32'h00000000; // 0x03f0
+ 8'h0fd : RDATA <= 32'h00000000; // 0x03f4
+ 8'h0fe : RDATA <= 32'h00000000; // 0x03f8
+ 8'h0ff : RDATA <= 32'h00000000; // 0x03fc
+ default : RDATA <=32'h0;
+ endcase
+endmodule
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
new file mode 100644
index 0000000000000000000000000000000000000000..240cef550f95a9422ce53cd8bb52dd740461d6e1
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
@@ -0,0 +1,1320 @@
+//-----------------------------------------------------------------------------
+// customised top-level example Cortex-M0 controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2021, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+
+`include "cmsdk_mcu_defs.v"
+
+`define SYNTHBOOTROM
+
+module cmsdk_mcu_chip #(
+ //-----------------------------------------
+ // CPU options
+
+`ifdef ARM_CMSDK_INCLUDE_CLKGATE
+ parameter CLKGATE_PRESENT = 1,
+`else
+ parameter CLKGATE_PRESENT = 0,
+`endif
+ parameter BE = 0, // Big or little endian
+ parameter BKPT = 4, // Number of breakpoint comparators
+ parameter DBG = 1, // Debug configuration
+ parameter NUMIRQ = 32, // NUM of IRQ
+ parameter SMUL = 0, // Multiplier configuration
+ parameter SYST = 1, // SysTick
+ parameter WIC = 1, // Wake-up interrupt controller support
+ parameter WICLINES = 34, // Supported WIC lines
+ parameter WPT = 2, // Number of DWT comparators
+ parameter RESET_ALL_REGS = 0, // Do not reset all registers
+
+ parameter BOOT_MEM_TYPE = `ARM_CMSDK_BOOT_MEM_TYPE, // Boot loader memory type
+
+ parameter ROM_MEM_TYPE = `ARM_CMSDK_ROM_MEM_TYPE, // ROM memory type
+
+ parameter RAM_MEM_TYPE = `ARM_CMSDK_RAM_MEM_TYPE, // RAM memory type
+
+ //-----------------------------------------
+ // System options
+
+`ifdef ARM_CMSDK_INCLUDE_DMA
+ parameter INCLUDE_DMA = 1, // Include instantiation of DMA-230
+ // This option also add a number of bus components
+ parameter DMA_CHANNEL_NUM = 1,
+`else
+ parameter INCLUDE_DMA = 0,
+ parameter DMA_CHANNEL_NUM = 1,
+`endif
+
+`ifdef ARM_CMSDK_INCLUDE_BITBAND
+ parameter INCLUDE_BITBAND = 1,
+ // Include instantiation of Bit-band wrapper
+ // This option add bit band wrapper to CPU interface
+`else
+ parameter INCLUDE_BITBAND = 0,
+`endif
+
+`ifdef ARM_CMSDK_INCLUDE_JTAG
+ parameter INCLUDE_JTAG = 1 // Include JTAG feature
+`else
+ parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
+`endif
+ )
+ (
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+`endif
+ input wire XTAL1, // input
+ output wire XTAL2, // output
+ input wire NRST, // active low reset
+ inout wire [15:0] P0,
+ inout wire [15:0] P1,
+
+`ifdef ARM_CMSDK_INCLUDE_JTAG
+ input wire nTRST,
+ input wire TDI,
+ output wire TDO,
+`endif
+ inout wire SWDIOTMS,
+ input wire SWCLKTCK);
+
+
+//------------------------------------
+// internal wires
+
+ wire xtal_clk_in;
+ wire xtal_clk_out;
+ wire nrst_in;
+ wire [15:0] p0_in; // level-shifted input from pad
+ wire [15:0] p0_out; // output port drive
+ wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_out_nen; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_in; // level-shifted input from pad
+ wire [15:0] p1_out; // output port drive
+ wire [15:0] p1_out_en; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_out_nen; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_out_mux; // output port drive
+ wire [15:0] p1_out_en_mux; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_out_nen_mux; // active low output drive enable (pad tech dependent)
+
+`ifdef ARM_CMSDK_INCLUDE_JTAG
+ wire ntrst_in;
+ wire tdi_in;
+ wire tdo_out;
+`endif
+ wire swdio_in;
+ wire swdio_out;
+ wire swdio_out_en;
+ wire swdio_out_nen;
+ wire swdclk_in;
+
+
+/*
+ cmsdk_mcu_core
+ #(.CLKGATE_PRESENT (CLKGATE_PRESENT),
+ .BE (BE),
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .NUMIRQ (NUMIRQ), // NUMIRQ
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+`ifdef CORTEX_M0PLUS
+ .AWIDTH (AWIDTH), // Micro Trace Buffer SRAM address width
+ .BASEADDR (BASEADDR), // ROM Table Base Address
+ .HWF (HWF), // Half Word Fetching
+ .IOP (IOP), // IO Port interface selected
+ .IRQDIS (IRQDIS), // Interrupt Disable
+ .MPU (MPU), // Memory Protection support
+ .MTB (MTB), // MTB select
+ .USER (USER), // User/Privilege
+ .VTOR (VTOR), // Vector Table Offset support
+`endif
+ .WPT (WPT), // Number of DWT comparators
+ .RESET_ALL_REGS (RESET_ALL_REGS), // Do not reset all registers
+ .BOOT_MEM_TYPE (BOOT_MEM_TYPE), // Boot loader memory type
+ .ROM_MEM_TYPE (ROM_MEM_TYPE), // ROM memory type
+ .RAM_MEM_TYPE (RAM_MEM_TYPE), // RAM loader memory type
+ .INCLUDE_BITBAND (INCLUDE_BITBAND), // Include bit band wrapper
+ .INCLUDE_DMA (INCLUDE_DMA), // Include DMA feature
+ .INCLUDE_JTAG (INCLUDE_JTAG) // Include JTAG feature
+ )
+ u_cmsdk_mcu_core (
+`ifdef POWER_PINS
+ .VDDIO (VDDIO),
+ .VSSIO (VSSIO),
+ .VDD (VDD),
+ .VSS (VSS),
+`endif
+ .clk (xtal_clk_in), // primary clock
+ .clk_out (xtal_clk_out), // inverted clock out
+ .nrst (nrst_in) // primary reset (active-low)
+
+ .p0_in (p0_in ), // level-shifted input from pad
+ .p0_out (p0_out ), // output port drive
+ .p0_out_en (p0_out_en ), // active high output drive enable (pad tech dependent)
+ .p0_out_nen (p0_out_nen), // active low output drive enable (pad tech dependent)
+
+ .p1_in (p1_in ), // level-shifted input from pad
+ .p1_out_mux (p1_out ), // output port drive
+ .p1_out_en_mux (p1_out_en ), // active high output drive enable (pad tech dependent)
+ .p1_out_nen_mux (p1_out_nen), // active low output drive enable (pad tech dependent)
+
+`ifdef ARM_CMSDK_INCLUDE_JTAG
+ .ntrst (ntrst_in), // JTAG reset (active-low)
+ .tdi (tdi_in), // JTAG reset (active-low)
+ .tdo (tdo_out), // inverted clock out
+`endif
+ .swdio_in (swdio_in), // Serial Wire Debug IO input
+ .swdio_out (swdio_out), // Serial Wire Debug IO output
+ .swdio_out_en (swdio_out_en), // Serial Wire Debug IO output drive enable (active high)
+ .swdio_out_nen (swdio_out_nen), // Serial Wire Debug IO output drive enable (active low)
+ .swdclk (swdclk_in) // Serial Wire Debug clock input
+ );
+*/
+
+//TIE_HI uTIEHI (.tiehi(tiehi));
+ wire tiehi = 1'b1;
+//TIE_LO uTIELO (.tielo(tielo));
+ wire tielo = 1'b0;
+
+ // --------------------------------------------------------------------------------
+ // IO pad (GLIB Generic Library napping)
+ // --------------------------------------------------------------------------------
+
+`ifdef POWER_PINS
+// Pad IO power supplies
+
+PAD_VDDIO uPAD_VDDIO_1(
+ .PAD(VDDIO)
+ );
+
+PAD_VDDIO uPAD_VSSIO_1(
+ .PAD(VSSIO)
+ );
+
+// Core power supplies
+
+PAD_VDDIO uPAD_VDD_1(
+ .PAD(VDD)
+ );
+
+PAD_VDDIO uPAD_VSS_1(
+ .PAD(VSS)
+ );
+`endif
+
+// Clock, Reset and Serial Wire Debug ports
+
+PAD_INOUT8MA_NOE uPAD_XTAL_I (
+ .PAD (XTAL1),
+ .O (tielo),
+ .I (xtal_clk_in),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_XTAL_O (
+ .PAD (XTAL2),
+ .O (xtal_clk_out),
+ .I (tielo),
+ .NOE (tielo)
+ );
+
+PAD_INOUT8MA_NOE uPAD_NRST_I (
+ .PAD (NRST),
+ .O (tielo),
+ .I (nrst_in),
+ .NOE (tiehi)
+ );
+
+PAD_INOUT8MA_NOE uPAD_SWDIO_I (
+ .PAD (SWDIOTMS),
+ .O (swdio_out),
+ .I (swdio_in),
+ .NOE (swdio_out_nen)
+ );
+
+PAD_INOUT8MA_NOE uPAD_SWDCLK_I (
+ .PAD (SWCLKTCK),
+ .O (tielo),
+ .I (swdclk_in),
+ .NOE (tiehi)
+ );
+
+// GPI.I Port 0 x 16
+
+PAD_INOUT8MA_NOE uPAD_P0_00 (
+ .PAD (P0[00]),
+ .O (p0_out[00]),
+ .I (p0_in[00]),
+ .NOE (p0_out_nen[00])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_01 (
+ .PAD (P0[01]),
+ .O (p0_out[01]),
+ .I (p0_in[01]),
+ .NOE (p0_out_nen[01])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_02 (
+ .PAD (P0[02]),
+ .O (p0_out[02]),
+ .I (p0_in[02]),
+ .NOE (p0_out_nen[02])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_03 (
+ .PAD (P0[03]),
+ .O (p0_out[03]),
+ .I (p0_in[03]),
+ .NOE (p0_out_nen[03])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_04 (
+ .PAD (P0[04]),
+ .O (p0_out[04]),
+ .I (p0_in[04]),
+ .NOE (p0_out_nen[04])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_05 (
+ .PAD (P0[05]),
+ .O (p0_out[05]),
+ .I (p0_in[05]),
+ .NOE (p0_out_nen[05])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_06 (
+ .PAD (P0[06]),
+ .O (p0_out[06]),
+ .I (p0_in[06]),
+ .NOE (p0_out_nen[06])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_07 (
+ .PAD (P0[07]),
+ .O (p0_out[07]),
+ .I (p0_in[07]),
+ .NOE (p0_out_nen[07])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_08 (
+ .PAD (P0[08]),
+ .O (p0_out[08]),
+ .I (p0_in[08]),
+ .NOE (p0_out_nen[08])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_09 (
+ .PAD (P0[09]),
+ .O (p0_out[09]),
+ .I (p0_in[09]),
+ .NOE (p0_out_nen[09])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_10 (
+ .PAD (P0[10]),
+ .O (p0_out[10]),
+ .I (p0_in[10]),
+ .NOE (p0_out_nen[10])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_11 (
+ .PAD (P0[11]),
+ .O (p0_out[11]),
+ .I (p0_in[11]),
+ .NOE (p0_out_nen[11])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_12 (
+ .PAD (P0[12]),
+ .O (p0_out[12]),
+ .I (p0_in[12]),
+ .NOE (p0_out_nen[12])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_13 (
+ .PAD (P0[13]),
+ .O (p0_out[13]),
+ .I (p0_in[13]),
+ .NOE (p0_out_nen[13])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_14 (
+ .PAD (P0[14]),
+ .O (p0_out[14]),
+ .I (p0_in[14]),
+ .NOE (p0_out_nen[14])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P0_15 (
+ .PAD (P0[15]),
+ .O (p0_out[15]),
+ .I (p0_in[15]),
+ .NOE (p0_out_nen[15])
+ );
+
+// GPI.I Port 1 x 16
+
+PAD_INOUT8MA_NOE uPAD_P1_00 (
+ .PAD (P1[00]),
+ .O (p1_out_mux[00]),
+ .I (p1_in[00]),
+ .NOE (p1_out_nen_mux[00])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_01 (
+ .PAD (P1[01]),
+ .O (p1_out_mux[01]),
+ .I (p1_in[01]),
+ .NOE (p1_out_nen_mux[01])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_02 (
+ .PAD (P1[02]),
+ .O (p1_out_mux[02]),
+ .I (p1_in[02]),
+ .NOE (p1_out_nen_mux[02])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_03 (
+ .PAD (P1[03]),
+ .O (p1_out_mux[03]),
+ .I (p1_in[03]),
+ .NOE (p1_out_nen_mux[03])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_04 (
+ .PAD (P1[04]),
+ .O (p1_out_mux[04]),
+ .I (p1_in[04]),
+ .NOE (p1_out_nen_mux[04])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_05 (
+ .PAD (P1[05]),
+ .O (p1_out_mux[05]),
+ .I (p1_in[05]),
+ .NOE (p1_out_nen_mux[05])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_06 (
+ .PAD (P1[06]),
+ .O (p1_out_mux[06]),
+ .I (p1_in[06]),
+ .NOE (p1_out_nen_mux[06])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_07 (
+ .PAD (P1[07]),
+ .O (p1_out_mux[07]),
+ .I (p1_in[07]),
+ .NOE (p1_out_nen_mux[07])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_08 (
+ .PAD (P1[08]),
+ .O (p1_out_mux[08]),
+ .I (p1_in[08]),
+ .NOE (p1_out_nen_mux[08])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_09 (
+ .PAD (P1[09]),
+ .O (p1_out_mux[09]),
+ .I (p1_in[09]),
+ .NOE (p1_out_nen_mux[09])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_10 (
+ .PAD (P1[10]),
+ .O (p1_out_mux[10]),
+ .I (p1_in[10]),
+ .NOE (p1_out_nen_mux[10])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_11 (
+ .PAD (P1[11]),
+ .O (p1_out_mux[11]),
+ .I (p1_in[11]),
+ .NOE (p1_out_nen_mux[11])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_12 (
+ .PAD (P1[12]),
+ .O (p1_out_mux[12]),
+ .I (p1_in[12]),
+ .NOE (p1_out_nen_mux[12])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_13 (
+ .PAD (P1[13]),
+ .O (p1_out_mux[13]),
+ .I (p1_in[13]),
+ .NOE (p1_out_nen_mux[13])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_14 (
+ .PAD (P1[14]),
+ .O (p1_out_mux[14]),
+ .I (p1_in[14]),
+ .NOE (p1_out_nen_mux[14])
+ );
+
+PAD_INOUT8MA_NOE uPAD_P1_15 (
+ .PAD (P1[15]),
+ .O (p1_out_mux[15]),
+ .I (p1_in[15]),
+ .NOE (p1_out_nen_mux[15])
+ );
+
+//------------------------------------
+// internal wires
+
+ assign p0_out_nen = ~p0_out_en; //active low pad drive option
+ assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
+
+ wire SLEEPING;
+ wire APBACTIVE;
+ wire SYSRESETREQ; // processor system reset request
+ wire WDOGRESETREQ; // watchdog system reset request
+ wire HRESETREQ; // Combined system reset request
+ wire cmsdk_SYSRESETREQ; // Combined system reset request
+ wire clk_ctrl_sys_reset_req;
+ wire PMUHRESETREQ;
+ wire PMUDBGRESETREQ;
+ wire LOCKUP;
+ wire LOCKUPRESET;
+ wire PMUENABLE;
+ wire SLEEPDEEP;
+
+
+`ifdef CORTEX_M0DESIGNSTART
+ // if using DesignStart CortexM0, remove these signals
+`else
+ wire WAKEUP;
+ wire GATEHCLK;
+ wire WICENREQ;
+ wire WICENACK;
+ wire CDBGPWRUPREQ;
+ wire CDBGPWRUPACK;
+ wire SLEEPHOLDREQn;
+ wire SLEEPHOLDACKn;
+
+ wire SYSPWRDOWNACK;
+ wire DBGPWRDOWNACK;
+ wire SYSPWRDOWN;
+ wire DBGPWRDOWN;
+ wire SYSISOLATEn;
+ wire SYSRETAINn;
+ wire DBGISOLATEn;
+`endif
+
+ wire PORESETn;// Power on reset
+ wire HRESETn; // AHB reset
+ wire PRESETn; // APB and peripheral reset
+`ifndef CORTEX_M0DESIGNSTART
+ wire DBGRESETn; // Debug system reset
+`endif
+ wire FCLK; // Free running system clock
+ wire HCLK; // System clock from PMU
+`ifndef CORTEX_M0DESIGNSTART
+ wire DCLK;
+`endif
+ wire SCLK;
+ wire PCLK; // Peripheral clock
+ wire PCLKG; // Gated PCLK for APB
+ wire HCLKSYS; // System clock for memory
+ wire PCLKEN; // Clock divider for AHB to APB bridge
+ // Common AHB signals
+ wire [31:0] HADDR;
+ wire [1:0] HTRANS;
+ wire [2:0] HSIZE;
+ wire HWRITE;
+ wire [31:0] HWDATA;
+ wire HREADY;
+
+// DMA controller master interface
+ wire [31:0] dmac_haddr;
+ wire [1:0] dmac_htrans;
+ wire [2:0] dmac_hsize;
+ wire [2:0] dmac_hburst;
+ wire [3:0] dmac_hprot;
+ wire dmac_hmastlock;
+ wire dmac_hwrite;
+ wire [31:0] dmac_hwdata;
+ wire [31:0] dmac_hrdata;
+ wire dmac_hready;
+ wire dmac_hresp;
+
+ wire dmac_done;
+ wire dmac_err;
+ wire dmac_psel;
+ wire dmac_pready;
+ wire exp_penable;
+ wire exp_pwrite;
+ wire [11:0] exp_paddr;
+ wire [31:0] exp_pwdata;
+ wire dmac_pslverr;
+ wire [31:0] dmac_prdata;
+
+ // Flash memory AHB signals
+ wire flash_hsel;
+ wire flash_hreadyout;
+ wire [31:0] flash_hrdata;
+ wire flash_hresp;
+
+ // SRAM AHB signals
+ wire sram_hsel;
+ wire sram_hreadyout;
+ wire [31:0] sram_hrdata;
+ wire sram_hresp;
+
+ // Boot loader/firmware AHB signals
+ // Only use if BOOT_MEM_TYPE is not zero
+ wire boot_hsel;
+ wire boot_hreadyout;
+ wire [31:0] boot_hrdata;
+ wire boot_hresp;
+
+ // internal peripheral signals
+ wire uart0_rxd;
+ wire uart0_txd;
+ wire uart0_txen;
+ wire uart1_rxd;
+ wire uart1_txd;
+ wire uart1_txen;
+ wire uart2_rxd;
+ wire uart2_txd;
+ wire uart2_txen;
+
+ wire timer0_extin;
+ wire timer1_extin;
+
+ wire [15:0] p0_altfunc;
+
+ wire [15:0] p1_altfunc;
+
+ localparam BASEADDR_GPIO0 = 32'h4001_0000;
+ localparam BASEADDR_GPIO1 = 32'h4001_1000;
+ localparam BASEADDR_SYSROMTABLE = 32'hF000_0000;
+
+`ifdef CORTEX_M0PLUS
+`ifdef ARM_CMSDK_INCLUDE_MTB
+ // MTB Control
+ wire TSTART;
+ wire TSTOP;
+
+ // EMBEDDED SRAM (MTB) INTERFACE
+ wire RAMHCLK;
+ wire [31:0] RAMRD;
+ wire [AWIDTH-3:0] RAMAD;
+ wire [31:0] RAMWD;
+ wire RAMCS;
+ wire [ 3:0] RAMWE;
+
+ localparam BASEADDR_MTBSRAM = 32'hF021_0000;
+
+ wire [31:0] SRAMBASEADDR = BASEADDR_MTBSRAM;
+`endif
+`endif
+
+ // Internal Debug signals
+ wire i_trst_n;
+ wire i_swditms;
+ wire i_swclktck;
+ wire i_tdi;
+ wire i_tdo;
+ wire i_tdoen_n;
+ wire i_swdo;
+ wire i_swdoen;
+
+ wire TESTMODE;
+
+`ifdef ARM_CMSDK_INCLUDE_JTAG
+`else
+ // Serial wire debug is used. nTRST, TDI and TDO are not needed
+ wire nTRST = 1'b0;
+ wire TDI = 1'b1;
+ wire TDO;
+`endif
+
+ assign TESTMODE = 1'b0;
+
+//----------------------------------------
+// Clock and reset controller
+//----------------------------------------
+`ifdef CORTEX_M0DESIGNSTART
+ // Clock controller generates reset if PMU request (PMUHRESETREQ),
+ // CPU request or watchdog request (SYSRESETREQ)
+ assign clk_ctrl_sys_reset_req = PMUHRESETREQ | cmsdk_SYSRESETREQ;
+`else
+ // Clock controller generates reset if PMU request (PMUHRESETREQ),
+ // CPU request or watchdog request (HRESETREQ)
+ assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
+`endif
+
+ // Clock controller to generate reset and clock signals
+ cmsdk_mcu_clkctrl
+ #(.CLKGATE_PRESENT(CLKGATE_PRESENT))
+ u_cmsdk_mcu_clkctrl(
+ // inputs
+ .XTAL1 (xtal_clk_in),
+ .NRST (nrst_in),
+
+ .APBACTIVE (APBACTIVE),
+ .SLEEPING (SLEEPING),
+ .SLEEPDEEP (SLEEPDEEP),
+ .LOCKUP (LOCKUP),
+ .LOCKUPRESET (LOCKUPRESET),
+ .SYSRESETREQ (clk_ctrl_sys_reset_req),
+ .DBGRESETREQ (PMUDBGRESETREQ),
+ .CGBYPASS (TESTMODE),
+ .RSTBYPASS (TESTMODE),
+
+ // outputs
+ .XTAL2 (xtal_clk_out),
+
+ .FCLK (FCLK),
+
+ .PCLK (PCLK),
+ .PCLKG (PCLKG),
+ .PCLKEN (PCLKEN),
+`ifdef CORTEX_M0DESIGNSTART
+ .PORESETn (PORESETn), // for cm0 designstart
+ .HRESETn (HRESETn), // for cm0 designstart
+`endif
+ .PRESETn (PRESETn)
+ );
+
+//----------------------------------------
+//
+ // System Reset request can be from processor or watchdog
+ // or when lockup happens and the control flag is set.
+ assign cmsdk_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
+ (LOCKUP & LOCKUPRESET);
+
+`ifdef CORTEX_M0DESIGNSTART
+ // Power Management Unit will not be available
+ assign HCLK = FCLK; // connect HCLK to FCLK
+ assign SCLK = FCLK; // connect SCLK to FCLK
+
+ // Since there is no PMU, these signals are not used
+ assign PMUDBGRESETREQ = 1'b0;
+ assign PMUHRESETREQ = 1'b0;
+
+`else
+
+ wire gated_hclk;
+ wire gated_dclk;
+ wire gated_sclk;
+
+`ifdef CORTEX_M0
+ // Cortex-M0 Power management unit
+ cortexm0_pmu u_cortexm0_pmu
+ ( // Inputs
+ .FCLK (FCLK),
+ .PORESETn (PORESETn),
+ .HRESETREQ (cmsdk_SYSRESETREQ), // from processor / watchdog
+ .PMUENABLE (PMUENABLE), // from System Controller
+ .WICENACK (WICENACK), // from WIC in integration
+
+ .WAKEUP (WAKEUP), // from WIC in integration
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+
+ .SLEEPDEEP (SLEEPDEEP),
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .GATEHCLK (GATEHCLK),
+ .SYSPWRDOWNACK (SYSPWRDOWNACK),
+ .DBGPWRDOWNACK (DBGPWRDOWNACK),
+ .CGBYPASS (TESTMODE),
+
+ // Outputs
+ .HCLK (gated_hclk),
+ .DCLK (gated_dclk),
+ .SCLK (gated_sclk),
+ .WICENREQ (WICENREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+ .SYSISOLATEn (SYSISOLATEn),
+ .SYSRETAINn (SYSRETAINn),
+ .SYSPWRDOWN (SYSPWRDOWN),
+ .DBGISOLATEn (DBGISOLATEn),
+ .DBGPWRDOWN (DBGPWRDOWN),
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ)
+ );
+
+ cortexm0_rst_ctl u_rst_ctl
+ (// Inputs
+ .GLOBALRESETn (NRST),
+ .FCLK (FCLK),
+ .HCLK (gated_hclk),
+ .DCLK (gated_dclk),
+ .SYSRESETREQ (cmsdk_SYSRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .RSTBYPASS (1'b0),
+ .SE (1'b0),
+
+ // Outputs
+ .PORESETn (PORESETn),
+ .HRESETn (HRESETn),
+ .DBGRESETn (DBGRESETn),
+ .HRESETREQ (HRESETREQ));
+
+`else
+ // Cortex-M0+ Power management unit
+ cm0p_ik_pmu u_cortexm0plus_pmu
+ ( // Inputs
+ .FCLK (FCLK),
+ .PORESETn (PORESETn),
+ .HRESETREQ (HRESETREQ),
+ .PMUENABLE (PMUENABLE),
+ .WICENACK (WICENACK),
+
+ .WAKEUP (WAKEUP),
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+
+ .SLEEPDEEP (SLEEPDEEP),
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .GATEHCLK (GATEHCLK),
+ .SYSPWRDOWNACK (SYSPWRDOWNACK),
+ .DBGPWRDOWNACK (DBGPWRDOWNACK),
+ .DFTSE (1'b0),
+
+ // Outputs
+ .HCLK (gated_hclk),
+ .DCLK (gated_dclk),
+ .SCLK (gated_sclk),
+ .WICENREQ (WICENREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+ .SYSISOLATEn (SYSISOLATEn),
+ .SYSRETAINn (SYSRETAINn),
+ .SYSPWRDOWN (SYSPWRDOWN),
+ .DBGISOLATEn (DBGISOLATEn),
+ .DBGPWRDOWN (DBGPWRDOWN),
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .PMUHRESETREQ (PMUHRESETREQ),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ)
+ );
+
+ cm0p_ik_rst_ctl u_rst_ctl
+ (// Inputs
+ .GLOBALRESETn (NRST),
+ .FCLK (FCLK),
+ .HCLK (gated_hclk),
+ .DCLK (gated_dclk),
+ .SYSRESETREQ (cmsdk_SYSRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .HREADY (HREADY),
+ .DFTRSTDISABLE (1'b0),
+ .DFTSE (1'b0),
+
+ // Outputs
+ .PORESETn (PORESETn),
+ .HRESETn (HRESETn),
+ .DBGRESETn (DBGRESETn),
+ .HRESETREQ (HRESETREQ));
+
+`endif
+
+ // Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
+ assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
+ assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
+ assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;
+
+ // In this example system, power control takes place immediately.
+ // In a real circuit you might need to add delays in the next two
+ // signal assignments for correct operation.
+ assign SYSPWRDOWNACK = SYSPWRDOWN;
+ assign DBGPWRDOWNACK = DBGPWRDOWN;
+
+`endif
+
+ // -------------------------------
+ // DMA Controller
+ // -------------------------------
+
+ // DMA interface not used in this example system
+ wire [DMA_CHANNEL_NUM-1:0] dma230_tie0; // tie off signal.
+
+ assign dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
+
+ // DMA done per channel
+ wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
+
+ generate if (INCLUDE_DMA != 0) begin : gen_pl230_udma
+ // DMA controller present
+ pl230_udma u_pl230_udma (
+ // Clock and Reset
+ .hclk (HCLKSYS),
+ .hresetn (HRESETn),
+ // DMA Control
+ .dma_req (dma230_tie0),
+ .dma_sreq (dma230_tie0),
+ .dma_waitonreq (dma230_tie0),
+ .dma_stall (1'b0),
+ .dma_active (),
+ .dma_done (dma230_done_ch),
+ .dma_err (dmac_err),
+ // AHB-Lite Master Interface
+ .hready (dmac_hready),
+ .hresp (dmac_hresp),
+ .hrdata (dmac_hrdata),
+ .htrans (dmac_htrans),
+ .hwrite (dmac_hwrite),
+ .haddr (dmac_haddr),
+ .hsize (dmac_hsize),
+ .hburst (dmac_hburst),
+ .hmastlock (dmac_hmastlock),
+ .hprot (dmac_hprot),
+ .hwdata (dmac_hwdata),
+ // APB Slave Interface
+ .pclken (PCLKEN),
+ .psel (dmac_psel),
+ .pen (exp_penable),
+ .pwrite (exp_pwrite),
+ .paddr (exp_paddr[11:0]),
+ .pwdata (exp_pwdata[31:0]),
+ .prdata (dmac_prdata)
+ );
+
+ assign dmac_pready = 1'b1;
+ assign dmac_pslverr = 1'b0;
+ assign dmac_done = |dma230_done_ch; // OR all the DMA done together
+
+ end else begin : gen_no_pl230_udma
+ // DMA controller not present
+ assign dmac_htrans = 2'b00;
+ assign dmac_hwrite = 1'b0;
+ assign dmac_haddr = 32'h00000000;
+ assign dmac_hsize = 3'b000;
+ assign dmac_hburst = 3'b000;
+ assign dmac_hmastlock = 1'b0;
+ assign dmac_hprot = 4'b0000;
+ assign dmac_hwdata = 32'h00000000;
+
+ assign dmac_done = 1'b0;
+ assign dmac_err = 1'b0;
+ assign dmac_pready = 1'b1;
+ assign dmac_pslverr = 1'b0;
+ assign dmac_prdata = 32'h00000000;
+ assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
+
+ end endgenerate
+
+//---------------------------------------------------
+// System design for example Cortex-M0/Cortex-M0+ MCU
+//---------------------------------------------------
+ cmsdk_mcu_system
+ #(.CLKGATE_PRESENT (CLKGATE_PRESENT),
+ .BE (BE),
+ .BASEADDR_GPIO0 (BASEADDR_GPIO0), // GPIO0 Base Address
+ .BASEADDR_GPIO1 (BASEADDR_GPIO1), // GPIO1 Base Address
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .NUMIRQ (NUMIRQ), // NUMIRQ
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT), // Number of DWT comparators
+ .RESET_ALL_REGS (RESET_ALL_REGS), // Do not reset all registers
+ .BOOT_MEM_TYPE (BOOT_MEM_TYPE), // Boot loader memory type
+ .INCLUDE_DMA (INCLUDE_DMA), // Include DMA feature
+ .INCLUDE_BITBAND (INCLUDE_BITBAND), // Include bit band wrapper
+ .INCLUDE_JTAG (INCLUDE_JTAG), // Include JTAG feature
+ .BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE) // System ROM Table base address
+ )
+ u_cmsdk_mcu_system (
+ .FCLK (FCLK),
+ .HCLK (HCLK),
+`ifndef CORTEX_M0DESIGNSTART
+ .DCLK (DCLK),
+`endif
+ .SCLK (SCLK),
+ .HRESETn (HRESETn),
+ .PORESETn (PORESETn),
+`ifdef CORTEX_M0
+ .DBGRESETn (DBGRESETn),
+ .RSTBYPASS (TESTMODE),
+`endif
+
+ .PCLK (PCLK),
+ .PCLKG (PCLKG),
+ .PRESETn (PRESETn),
+ .PCLKEN (PCLKEN),
+
+ // Common AHB signals
+ .HADDR (HADDR),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ // Flash
+ .flash_hsel (flash_hsel),
+ .flash_hreadyout (flash_hreadyout),
+ .flash_hrdata (flash_hrdata),
+ .flash_hresp (flash_hresp),
+
+ // SRAM
+ .sram_hsel (sram_hsel),
+ .sram_hreadyout (sram_hreadyout),
+ .sram_hrdata (sram_hrdata),
+ .sram_hresp (sram_hresp),
+
+ // Optional boot loader
+ // Only use if BOOT_MEM_TYPE is not zero
+ .boot_hsel (boot_hsel),
+ .boot_hreadyout (boot_hreadyout),
+ .boot_hrdata (boot_hrdata),
+ .boot_hresp (boot_hresp),
+
+ // Status
+ .APBACTIVE (APBACTIVE),
+ .SLEEPING (SLEEPING),
+ .SYSRESETREQ (SYSRESETREQ),
+ .WDOGRESETREQ (WDOGRESETREQ),
+ .LOCKUP (LOCKUP),
+ .LOCKUPRESET (LOCKUPRESET),
+ .PMUENABLE (PMUENABLE),
+ .SLEEPDEEP (SLEEPDEEP),
+
+`ifdef CORTEX_M0DESIGNSTART
+`else //if using DesignStart CortexM0, remove these signals
+
+ .GATEHCLK (GATEHCLK),
+ .WAKEUP (WAKEUP),
+ .WICENREQ (WICENREQ),
+ .WICENACK (WICENACK),
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+
+ // Debug
+ .nTRST (i_trst_n),
+ .SWDITMS (i_swditms),
+ .SWCLKTCK (i_swclktck),
+ .TDI (i_tdi),
+ .TDO (i_tdo),
+ .nTDOEN (i_tdoen_n),
+ .SWDO (i_swdo),
+ .SWDOEN (i_swdoen),
+`endif
+
+ // UART
+ .uart0_rxd (uart0_rxd),
+ .uart0_txd (uart0_txd),
+ .uart0_txen (uart0_txen),
+ .uart1_rxd (uart1_rxd),
+ .uart1_txd (uart1_txd),
+ .uart1_txen (uart1_txen),
+ .uart2_rxd (uart2_rxd),
+ .uart2_txd (uart2_txd),
+ .uart2_txen (uart2_txen),
+
+ // Timer
+ .timer0_extin (timer0_extin),
+ .timer1_extin (timer1_extin),
+
+ // IO Ports
+ .p0_in (p0_in),
+ .p0_out (p0_out),
+ .p0_outen (p0_out_en),
+ .p0_altfunc (p0_altfunc),
+
+ .p1_in (p1_in),
+ .p1_out (p1_out),
+ .p1_outen (p1_out_en),
+ .p1_altfunc (p1_altfunc),
+
+
+ // DMA Control
+ // .dma_req (dma230_tie0),
+ // .dma_sreq (dma230_tie0),
+ // .dma_waitonreq (dma230_tie0),
+ // .dma_stall (1'b0),
+ // .dma_active (),
+ .dma_done (dmac_done),
+ .dma_err (dmac_err),
+ // AHB-Lite Master Interface
+ .dmac_hready (dmac_hready),
+ .dmac_hresp (dmac_hresp),
+ .dmac_hrdata (dmac_hrdata),
+ .dmac_htrans (dmac_htrans),
+ .dmac_hwrite (dmac_hwrite),
+ .dmac_haddr (dmac_haddr),
+ .dmac_hsize (dmac_hsize),
+ .dmac_hburst (dmac_hburst),
+ .dmac_hmastlock (dmac_hmastlock),
+ .dmac_hprot (dmac_hprot),
+ .dmac_hwdata (dmac_hwdata),
+ // APB Slave Interface
+ .dmac_psel (dmac_psel),
+ .exp_penable (exp_penable),
+ .exp_pwrite (exp_pwrite),
+ .exp_paddr (exp_paddr[11:0]),
+ .exp_pwdata (exp_pwdata[31:0]),
+ .dmac_prdata (dmac_prdata),
+ .dmac_pready (1'b1),
+ .dmac_pslverr (1'b0),
+
+ .DFTSE (1'b0)
+ );
+
+//----------------------------------------
+// If DMA is present, use SCLK for system HCLK so that
+// DMA can run even if processor is in sleep mode.
+// Otherwise there is only one master (cpu), so AHB system
+// clock can be stopped when DMA take place.
+
+// assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
+ assign HCLKSYS = SCLK;
+
+//----------------------------------------
+// Flash memory
+//----------------------------------------
+cmsdk_ahb_rom
+ #(.MEM_TYPE(ROM_MEM_TYPE),
+ .AW(16), // 64K bytes flash ROM
+// .AW(13), // 8K bytes flash ROM -Dhry
+// .AW(10), // 1K bytes flash ROM - Hello
+ .filename("image.hex"),
+ .WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
+ .WS_S(`ARM_CMSDK_ROM_MEM_WS_S),
+ .BE (BE))
+ u_ahb_rom (
+ .HCLK (HCLKSYS),
+ .HRESETn (HRESETn),
+ .HSEL (flash_hsel), // AHB inputs
+ .HADDR (HADDR[15:0]),
+// .HADDR (HADDR[12:0]),
+// .HADDR (HADDR[ 9:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ .HREADYOUT (flash_hreadyout), // Outputs
+ .HRDATA (flash_hrdata),
+ .HRESP (flash_hresp)
+ );
+
+//----------------------------------------
+// Boot loader / Firmware
+//----------------------------------------
+
+`ifdef SYNTHBOOTROM
+ahb_bootrom__mangled
+// #(.AW(10) ) // 1K bytes ROM
+ u_ahb_bootloader (
+ .HCLK (HCLKSYS),
+ .HRESETn (HRESETn),
+ .HSEL (boot_hsel), // AHB inputs
+ .HADDR (HADDR[ 9:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ .HREADYOUT (boot_hreadyout), // Outputs
+ .HRDATA (boot_hrdata),
+ .HRESP (boot_hresp)
+ );
+
+`else
+// Only use if BOOT_MEM_TYPE is not zero
+cmsdk_ahb_rom
+ #(.MEM_TYPE(BOOT_MEM_TYPE),
+// .AW(12), // 4K bytes ROM
+ .AW(10), // 1K bytes ROM
+ .filename("bootloader.hex"),
+ .WS_N(`ARM_CMSDK_BOOT_MEM_WS_N),
+ .WS_S(`ARM_CMSDK_BOOT_MEM_WS_S),
+ .BE (BE))
+ u_ahb_bootloader (
+ .HCLK (HCLKSYS),
+ .HRESETn (HRESETn),
+ .HSEL (boot_hsel), // AHB inputs
+// .HADDR (HADDR[11:0]),
+ .HADDR (HADDR[ 9:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ .HREADYOUT (boot_hreadyout), // Outputs
+ .HRDATA (boot_hrdata),
+ .HRESP (boot_hresp)
+ );
+`endif
+
+//----------------------------------------
+// SRAM
+//----------------------------------------
+cmsdk_ahb_ram
+ #(.MEM_TYPE(RAM_MEM_TYPE),
+ .AW(16), // 64K bytes SRAM
+// .AW( 9), // 1K bytes SRAM
+ .WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
+ .WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
+ u_ahb_ram (
+ .HCLK (HCLKSYS),
+ .HRESETn (HRESETn),
+ .HSEL (sram_hsel), // AHB inputs
+ .HADDR (HADDR[15:0]),
+// .HADDR (HADDR[ 8:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ .HREADYOUT (sram_hreadyout), // Outputs
+ .HRDATA (sram_hrdata),
+ .HRESP (sram_hresp)
+ );
+
+//----------------------------------------
+// MTB SRAM Memory
+//----------------------------------------
+`ifdef CORTEX_M0PLUS
+`ifdef ARM_CMSDK_INCLUDE_MTB
+
+ cm0p_ik_sram
+ #(.MEMNAME ("MTB SRAM"),
+ .DATAWIDTH (32),
+ .ADDRWIDTH (AWIDTH-2),
+ .MEMBASE (BASEADDR_MTBSRAM))
+ u_mtbram
+ (//Output
+ .RDATA (RAMRD),
+ //Inputs
+ .CLK (RAMHCLK),
+ .ADDRESS (RAMAD[AWIDTH-3:0]),
+ .CS (RAMCS),
+ .WE (RAMWE),
+ .WDATA (RAMWD));
+
+`endif
+`endif
+
+//----------------------------------------
+// I/O port pin muxing and tristate
+//----------------------------------------
+
+ assign i_swclktck = swdclk_in;
+ assign i_swditms = swdio_in;
+ assign swdio_out = i_swdo;
+ assign swdio_out_en = i_swdoen;
+ assign swdio_out_nen = !i_swdoen;
+
+ cmsdk_mcu_pin_mux
+ u_pin_mux (
+ // UART
+ .uart0_rxd (uart0_rxd),
+ .uart0_txd (uart0_txd),
+ .uart0_txen (uart0_txen),
+ .uart1_rxd (uart1_rxd),
+ .uart1_txd (uart1_txd),
+ .uart1_txen (uart1_txen),
+ .uart2_rxd (uart2_rxd),
+ .uart2_txd (uart2_txd),
+ .uart2_txen (uart2_txen),
+
+ // Timer
+ .timer0_extin (timer0_extin),
+ .timer1_extin (timer1_extin),
+
+`ifdef CORTEX_M0PLUS
+`ifdef ARM_CMSDK_INCLUDE_MTB
+ // MTB CONTROL
+ .TSTART (TSTART),
+ .TSTOP (TSTOP),
+`endif
+`endif
+
+ // IO Ports
+ .p0_in ( ), // was (p0_in) now from pad inputs),
+ .p0_out (p0_out),
+ .p0_outen (p0_out_en),
+ .p0_altfunc (p0_altfunc),
+
+ .p1_in ( ), // was(p1_in) now from pad inputs),
+ .p1_out (p1_out),
+ .p1_outen (p1_out_en),
+ .p1_altfunc (p1_altfunc),
+
+ // Debug
+ .i_trst_n (i_trst_n),
+ .i_swditms ( ), //i_swditms),
+ .i_swclktck ( ), //i_swclktck),
+ .i_tdi (i_tdi),
+ .i_tdo (i_tdo),
+ .i_tdoen_n (i_tdoen_n),
+ .i_swdo (i_swdo),
+ .i_swdoen (i_swdoen),
+
+ // IO pads
+ .p1_out_mux (p1_out_mux),
+ .p1_out_en_mux (p1_out_en_mux),
+ .P0 ( ), //P0),
+ .P1 ( ), //P1),
+
+ .nTRST (nTRST), // Not needed if serial-wire debug is used
+ .TDI (TDI), // Not needed if serial-wire debug is used
+ .SWDIOTMS ( ), //SWDIOTMS),
+ .SWCLKTCK ( ), //SWCLKTCK),
+ .TDO (TDO) // Not needed if serial-wire debug is used
+
+ );
+
+endmodule
+
+
+
diff --git a/GLIB/mem/verilog/SROM_Ax32.v b/GLIB/mem/verilog/SROM_Ax32.v
new file mode 100644
index 0000000000000000000000000000000000000000..47ebf21162f7faffbb56569ed43278a7cf2c6917
--- /dev/null
+++ b/GLIB/mem/verilog/SROM_Ax32.v
@@ -0,0 +1,96 @@
+//-----------------------------------------------------------------------------
+//
+// Synthesizable byte-write addressible R/W (random-access) memory
+//
+// Synchronous data write, flow-though (non-pipeline registered) read data
+//
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2021, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SROM_Ax32
+ #(parameter ADDRWIDTH = 10,
+ parameter filename = "rom32.hex",
+ parameter romgen = 0
+ )
+ (input wire CLK,
+ input wire [ADDRWIDTH-1:0] ADDR, //Address Input
+ input wire SEL, //Select (active-high)
+ output wire [31:0] RDATA); //Read Data
+
+ localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1;
+ localparam romgenfile = "rom32_bootmem.v";
+
+ // Reg declarations
+ reg [7:0] rombyte0 [0:MEMDEPTH];
+ reg [7:0] rombyte1 [0:MEMDEPTH];
+ reg [7:0] rombyte2 [0:MEMDEPTH];
+ reg [7:0] rombyte3 [0:MEMDEPTH];
+
+ reg [ADDRWIDTH-1:0] addr_r; // registered Address for read access
+
+// optional simulation RAM_INIT option to suppress 'X' initial contents
+`ifdef MEM_INIT
+ reg [7:0] fileimage [((4<<ADDRWIDTH)-1):0];
+ function [31:0] NoX32; input [31:0] n; NoX32 = (((^n) === 1'bx) ? 32'h0 : n); endfunction
+ integer fd; // file descriptor for file output
+ integer i;
+initial
+ begin
+ for (i=0; i<= MEMDEPTH; i=i+1) begin
+ rombyte0[i] <= 8'he5;
+ rombyte1[i] <= 8'he5;
+ rombyte2[i] <= 8'he5;
+ rombyte3[i] <= 8'he5;
+ end
+ if (filename != "") begin
+ $readmemh(filename, fileimage);
+ for (i = 0; i <= MEMDEPTH; i=i+1) begin
+ rombyte0[i] <= fileimage[(i<<2)+0];
+ rombyte1[i] <= fileimage[(i<<2)+1];
+ rombyte2[i] <= fileimage[(i<<2)+2];
+ rombyte3[i] <= fileimage[(i<<2)+3];
+ end
+ end
+ if (romgen != 0)
+ begin
+ fd = $fopen(romgenfile);
+ if(fd == 0) begin
+ $display("rom32gen: Error, zero returned in response to $fopen\n");
+ end
+ else begin
+ $display(fd,"rom32gen: Generating output file\n");
+ $fwrite(fd,"module bootrom (\n");
+ $fwrite(fd," input wire CLK,\n");
+ $fwrite(fd," input wire EN,\n");
+ $fwrite(fd," input wire [%0d:2] ADDR,\n", ADDRWIDTH+1);
+ $fwrite(fd," output reg [31:0] RDATA );\n");
+ $fwrite(fd,"reg [%0d:2] addr_r;\n", ADDRWIDTH+1);
+ $fwrite(fd,"always @(posedge CLK) if (EN) addr_r <= ADDR;\n");
+ $fwrite(fd,"always @(addr_r)");
+ $fwrite(fd," case(addr_r[%0d:2]) \n", ADDRWIDTH+1);
+ for (i = 0; i < 4 << (ADDRWIDTH); i=i+4)
+ $fwrite(fd," %2d'h%2x : RDATA <= 32'h%8x; // 0x%04x\n", ADDRWIDTH, i>>2, NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}), i );
+ $fwrite(fd," default : RDATA <=32'h0;\n");
+ $fwrite(fd," endcase\n");
+ $fwrite(fd,"endmodule\n");
+ $fclose(fd);
+ end
+ end
+ end
+`endif
+
+// synchonous address and control
+
+ always @(posedge CLK) // update on any byte lane read
+ if (SEL)
+ addr_r <= ADDR[ADDRWIDTH-1:0];
+
+ assign RDATA = {rombyte3[addr_r],rombyte2[addr_r],rombyte1[addr_r],rombyte0[addr_r]};
+
+endmodule
diff --git a/GLIB/pads/verilog/GLIB_PADLIB.v b/GLIB/pads/verilog/GLIB_PADLIB.v
new file mode 100755
index 0000000000000000000000000000000000000000..8ac1ac4b760a7af4a9954c058a782ed8834abb0f
--- /dev/null
+++ b/GLIB/pads/verilog/GLIB_PADLIB.v
@@ -0,0 +1,146 @@
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+// (C) COPYRIGHT 2009-2010 ARM Limited.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+// Revision : $Revision: $
+//
+// Release Information : $ $
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+ // Inouts
+ PAD,
+ // Outputs
+ O,
+ // Inputs
+ I,
+ NOE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input NOE;
+
+`ifdef BEHAVIORAL_PADS
+ assign I = PAD;
+ assign PAD = ~NOE ? O : 1'bz;
+`else
+ bufif1 #2 (PAD, O, ~NOE);
+ buf #1 (I, PAD);
+ always @(PAD)
+ begin
+ if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+ $display("%t ++BUS CONFLICT++ : %m", $realtime);
+ end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_NOE
+
+module PAD_INOUT8MA_OE (
+ // Inouts
+ PAD,
+ // Outputs
+ O,
+ // Inputs
+ I,
+ OE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input OE;
+`ifdef BEHAVIORAL_PADS
+ assign I = PAD;
+ assign PAD = OE ? O : 1'bz;
+`else
+ bufif1 #2 (PAD, O, OE);
+ buf #1 (I, PAD);
+
+ always @(PAD)
+ begin
+ if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+ $display("%t ++BUS CONFLICT++ : %m", $realtime);
+ end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_OE
+
+module PAD_VDDIO (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VDDIO
+
+module PAD_VSSIO (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VSSSIO
+
+// core logic supply rails (1V0, 0V)
+module PAD_VDDSOC (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VDDSOC
+
+module PAD_VSS (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_VSS
+
+// VDDISOL
+module PAD_ANALOG (
+ PAD
+ );
+ inout PAD;
+endmodule // PAD_ANALOG
+
+`ifdef TSMC_PADS
+
+// VDDSOC
+module PVDD1CDG (
+ inout wire VDD
+ );
+endmodule // PVDD1CDG
+
+//VDDIO
+module PVDD2CDG (
+ inout wire VDDPST
+ );
+endmodule // PVDD2CDG
+
+module PVDD2POC (
+ inout wire VDDPST
+ );
+endmodule // PVDD2CDG
+
+module PVSS3CDG (
+ inout wire VSS
+ );
+endmodule // PVSS3CDG
+
+// VDDISOL
+module PVDD1ANA (
+ inout wire AVDD
+ );
+endmodule // PVDD1ANA
+
+
+module PCORNER ( ); endmodule
+module PFILLER20 ( ); endmodule
+module PFILLER1 ( ); endmodule
+module PFILLER0005 ( ); endmodule
+
+module PAD60LU ( ); endmodule
+
+`endif