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pads/verilog/PAD_INOUT8MA_NOE.v
View file @ 57e20563
......@@ -26,6 +26,7 @@ module PAD_INOUT8MA_NOE (
input O;
input NOE;
bufif1 #2 (PAD, O, ~NOE);
buf #1 (I, PAD);
assign PAD = NOE ? 1'bz : O;
assign I = PAD;
endmodule // PAD_INOUT8MA_NOE