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pads/verilog/PAD_INOUT8MA_NOE.v
View file @ 57e20563
...@@ -26,6 +26,7 @@ module PAD_INOUT8MA_NOE ( ...@@ -26,6 +26,7 @@ module PAD_INOUT8MA_NOE (
input O; input O;
input NOE; input NOE;
bufif1 #2 (PAD, O, ~NOE); assign PAD = NOE ? 1'bz : O;
buf #1 (I, PAD); assign I = PAD;
endmodule // PAD_INOUT8MA_NOE endmodule // PAD_INOUT8MA_NOE