update pad model for ASIC with no technology pads

pads/verilog/PAD_INOUT8MA_NOE.v

@@ -26,6 +26,7 @@ module PAD_INOUT8MA_NOE (
    input O;
    input NOE;
 
-   bufif1 #2 (PAD, O, ~NOE);
-   buf #1 (I, PAD);
+   assign PAD = NOE ? 1'bz : O;
+   assign I = PAD;
+
 endmodule // PAD_INOUT8MA_NOE