diff --git a/pads/verilog/PAD_INOUT8MA_NOE.v b/pads/verilog/PAD_INOUT8MA_NOE.v index fa9b73f5d204311402182b29293545e074757203..c2a22a665656b54a31ce3036fc20398af585a46b 100644 --- a/pads/verilog/PAD_INOUT8MA_NOE.v +++ b/pads/verilog/PAD_INOUT8MA_NOE.v @@ -26,6 +26,7 @@ module PAD_INOUT8MA_NOE ( input O; input NOE; - bufif1 #2 (PAD, O, ~NOE); - buf #1 (I, PAD); + assign PAD = NOE ? 1'bz : O; + assign I = PAD; + endmodule // PAD_INOUT8MA_NOE