From 57e2056366551367fedfdd983eb659dc2076a8b1 Mon Sep 17 00:00:00 2001 From: Daniel Newbrook <dwn1c21@soton.ac.uk> Date: Mon, 28 Oct 2024 20:26:09 +0000 Subject: [PATCH] update pad model for ASIC with no technology pads --- pads/verilog/PAD_INOUT8MA_NOE.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/pads/verilog/PAD_INOUT8MA_NOE.v b/pads/verilog/PAD_INOUT8MA_NOE.v index fa9b73f..c2a22a6 100644 --- a/pads/verilog/PAD_INOUT8MA_NOE.v +++ b/pads/verilog/PAD_INOUT8MA_NOE.v @@ -26,6 +26,7 @@ module PAD_INOUT8MA_NOE ( input O; input NOE; - bufif1 #2 (PAD, O, ~NOE); - buf #1 (I, PAD); + assign PAD = NOE ? 1'bz : O; + assign I = PAD; + endmodule // PAD_INOUT8MA_NOE -- GitLab