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Commit 3f50e0f6 authored by Daniel Newbrook's avatar Daniel Newbrook
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Fix clock connection

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sram/verilog/sl_sram.v
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...@@ -53,7 +53,7 @@ generate ...@@ -53,7 +53,7 @@ generate
.VSS (VSS), .VSS (VSS),
`endif `endif
.Q (RDATA32), .Q (RDATA32),
.CLK (HCLK), .CLK (CLK),
.CEN (CEN), .CEN (CEN),
.WEN (WEN32), .WEN (WEN32),
.A (ADDR12), .A (ADDR12),
...@@ -73,7 +73,7 @@ generate ...@@ -73,7 +73,7 @@ generate
.VSS (VSS), .VSS (VSS),
`endif `endif
.Q (RDATA32), .Q (RDATA32),
.CLK (HCLK), .CLK (CLK),
.CEN (CEN), .CEN (CEN),
.WEN (WEN32), .WEN (WEN32),
.A (ADDR12), .A (ADDR12),
......
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