diff --git a/sram/verilog/sl_sram.v b/sram/verilog/sl_sram.v
index 64b0786b37457254a5da272f245eebf0c915ba6b..05642bd7face42d3b2962ffe80f2dfc0323e9d19 100644
--- a/sram/verilog/sl_sram.v
+++ b/sram/verilog/sl_sram.v
@@ -53,7 +53,7 @@ generate
       .VSS  (VSS),
   `endif
       .Q     (RDATA32),
-      .CLK   (HCLK),
+      .CLK   (CLK),
       .CEN   (CEN),
       .WEN   (WEN32),
       .A     (ADDR12),
@@ -73,7 +73,7 @@ generate
       .VSS  (VSS),
   `endif
       .Q     (RDATA32),
-      .CLK   (HCLK),
+      .CLK   (CLK),
       .CEN   (CEN),
       .WEN   (WEN32),
       .A     (ADDR12),