From 3f50e0f6361cbe7eead4aaad8711a7aa67e88e9d Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 12 Dec 2023 10:56:27 +0000
Subject: [PATCH] Fix clock connection
---
sram/verilog/sl_sram.v | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sram/verilog/sl_sram.v b/sram/verilog/sl_sram.v
index 64b0786..05642bd 100644
--- a/sram/verilog/sl_sram.v
+++ b/sram/verilog/sl_sram.v
@@ -53,7 +53,7 @@ generate
.VSS (VSS),
`endif
.Q (RDATA32),
- .CLK (HCLK),
+ .CLK (CLK),
.CEN (CEN),
.WEN (WEN32),
.A (ADDR12),
@@ -73,7 +73,7 @@ generate
.VSS (VSS),
`endif
.Q (RDATA32),
- .CLK (HCLK),
+ .CLK (CLK),
.CEN (CEN),
.WEN (WEN32),
.A (ADDR12),
--
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