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Commit c62601bf authored by dam1n19's avatar dam1n19
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Distributed filelists to appropriate repositories

parent f01c10a6
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1 merge request!1Changed set_env flow to source script in soctools and breadcrumb left in...
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flist/ahb/ahb_ip.flist
+ 4
− 4
View file @ c62601bf
...@@ -16,8 +16,8 @@ ...@@ -16,8 +16,8 @@
+libext+.v+.vlib +libext+.v+.vlib
// ============= Accelerator Module search path ============= // ============= Accelerator Module search path =============
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog // CMSDK AHB Slave Mux IP
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog // CMSDK AHB Default Slave IP
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
\ No newline at end of file \ No newline at end of file
flist/ahb/ahb_vip.flist
+ 4
− 3
View file @ c62601bf
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
+libext+.v+.vlib +libext+.v+.vlib
// ============= Accelerator Module search path ============= // ============= Accelerator Module search path =============
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v
flist/apb/apb_ip.flist
+ 2
− 7
View file @ c62601bf
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// Accelerator Wrapper CMSDK Filelist // CMSDK APB IP Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
...@@ -15,12 +15,7 @@ ...@@ -15,12 +15,7 @@
// ============= Verilog library extensions =========== // ============= Verilog library extensions ===========
+libext+.v+.vlib +libext+.v+.vlib
// ============= Accelerator Module search path ============= // ============= CMSDK APB IP search path =============
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v
......
flist/corstone-101/corstone-101_ip.flist deleted 100644 → 0
+ 0
− 36
View file @ f01c10a6
//-----------------------------------------------------------------------------
// NanoSoC Corstone-101 Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Arm Corstone-101
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Corstone-101 search path =============
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
\ No newline at end of file
flist/corstone-101/corstone-101_vip.flist deleted 100644 → 0
+ 0
− 25
View file @ f01c10a6
//-----------------------------------------------------------------------------
// NanoSoC Corstone-101 VIP Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Arm Corstone-101 VIP
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= DMA-230 search path =============
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
\ No newline at end of file
flist/cortex-m0/cortex-m0_ip.flist deleted 100644 → 0
+ 0
− 31
View file @ f01c10a6
//-----------------------------------------------------------------------------
// NanoSoC Cortex-M0 Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Arm Cortex-M0
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
flist/dma-230/pl230_ip.flist deleted 100644 → 0
+ 0
− 26
View file @ f01c10a6
//-----------------------------------------------------------------------------
// NanoSoC DMA-230 Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Arm DMA-230
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= DMA-230 search path =============
+incdir+$(SOCLABS_PROJECT_DIR)/system/defines/pl230
$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v
$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v
$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_dma_data.v
$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_udma.v
$(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_undefs.v
flist/primitives/primitives.flist
+ 0
− 3
View file @ c62601bf
...@@ -16,7 +16,4 @@ ...@@ -16,7 +16,4 @@
+libext+.v+.vlib +libext+.v+.vlib
// ============= RTL Primitives search path ============= // ============= RTL Primitives search path =============
-y $(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
+incdir+$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv $(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv
flist/project/system.flist
+ 1
− 10
View file @ c62601bf
...@@ -43,16 +43,7 @@ ...@@ -43,16 +43,7 @@
-f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist -f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
// - CMSDK VIP // - CMSDK VIP
-f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_vip.flist -f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
// - Corstone-101 System components
-f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_ip.flist
// - DMA controller
-f $(SOCLABS_PROJECT_DIR)/flist/dma-230/pl230_ip.flist
// - Cortex-M0 IP
-f $(SOCLABS_PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
// - NanoSoC Custom Expansion Region // - NanoSoC Custom Expansion Region
//$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v //$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v
......
flist/project/wrapper.flist
+ 0
− 2
View file @ c62601bf
...@@ -21,8 +21,6 @@ ...@@ -21,8 +21,6 @@
-f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist -f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
// ============= Accelerator Module search path ============= // ============= Accelerator Module search path =============
-y $(SOCLABS_PROJECT_DIR)/wrapper/src/
+incdir+$(SOCLABS_PROJECT_DIR)/wrapper/src/
// Add the source files related to your custom wrapper // Add the source files related to your custom wrapper
// $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v // $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v
flist/wrapper/wrapper_ip.flist
+ 0
− 4
View file @ c62601bf
...@@ -16,12 +16,8 @@ ...@@ -16,12 +16,8 @@
+libext+.v+.vlib +libext+.v+.vlib
// ============= Accelerator Module search path ============= // ============= Accelerator Module search path =============
-y $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/
+incdir+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/
$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
......
nanosoc_tech @ d0ddcf03
Compare 226b723d...d0ddcf03
Subproject commit 226b723d27c500624446478a2303588500b3eddd Subproject commit d0ddcf03185befc43936756573f3bc4aa7d496b1
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